2 * This file implements the node emitter.
3 * @author Christian Wuerdig, Matthias Braun
21 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX ".L"
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
125 const arch_register_t *reg = NULL;
127 assert(get_irn_arity(irn) > pos && "Invalid IN position");
129 /* The out register of the operator at position pos is the
130 in register we need. */
131 op = get_irn_n(irn, pos);
133 reg = arch_get_irn_register(arch_env, op);
135 assert(reg && "no in register found");
137 /* in case of a joker register: just return a valid register */
138 if (arch_register_type_is(reg, joker)) {
139 arch_register_req_t req;
140 const arch_register_req_t *p_req;
142 /* ask for the requirements */
143 p_req = arch_get_register_req(arch_env, &req, irn, pos);
145 if (arch_register_req_is(p_req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
148 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
151 p_req->limited(p_req->limited_env, bs);
152 idx = bitset_next_set(bs, 0);
153 reg = arch_register_for_index(p_req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(p_req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
168 const arch_register_t *reg = NULL;
170 /* 1st case: irn is not of mode_T, so it has only */
171 /* one OUT register -> good */
172 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
173 /* Proj with the corresponding projnum for the register */
175 if (get_irn_mode(irn) != mode_T) {
176 reg = arch_get_irn_register(arch_env, irn);
177 } else if (is_ia32_irn(irn)) {
178 reg = get_ia32_out_reg(irn, pos);
180 const ir_edge_t *edge;
182 foreach_out_edge(irn, edge) {
183 proj = get_edge_src_irn(edge);
184 assert(is_Proj(proj) && "non-Proj from mode_T node");
185 if (get_Proj_proj(proj) == pos) {
186 reg = arch_get_irn_register(arch_env, proj);
192 assert(reg && "no out register found");
197 * Returns an ident for the given tarval tv.
199 static ident *get_ident_for_tv(tarval *tv) {
201 int len = tarval_snprintf(buf, sizeof(buf), tv);
203 return new_id_from_str(buf);
207 * Determine the gnu assembler suffix that indicates a mode
209 static char get_mode_suffix(const ir_mode *mode) {
210 if(mode_is_float(mode)) {
211 switch(get_mode_size_bits(mode)) {
220 assert(mode_is_int(mode) || mode_is_reference(mode));
221 switch(get_mode_size_bits(mode)) {
232 panic("Can't output mode_suffix for %+F\n", mode);
235 static int produces_result(const ir_node *node) {
236 return !(is_ia32_St(node) ||
237 is_ia32_Store8Bit(node) ||
238 is_ia32_CondJmp(node) ||
239 is_ia32_xCondJmp(node) ||
240 is_ia32_CmpSet(node) ||
241 is_ia32_xCmpSet(node) ||
242 is_ia32_SwitchJmp(node));
245 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
246 switch(get_mode_size_bits(mode)) {
248 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
250 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
252 return (char *)arch_register_get_name(reg);
258 * Determines the SSE suffix depending on the mode.
260 static int ia32_print_mode_suffix(lc_appendable_t *app,
261 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
263 ir_node *irn = arg->v_ptr;
264 ir_mode *mode = get_ia32_ls_mode(irn);
266 if (mode_is_float(mode)) {
267 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
269 if(get_mode_size_bits(mode) == 32)
272 if(mode_is_signed(mode))
273 lc_appendable_chadd(app, 's');
275 lc_appendable_chadd(app, 'z');
277 lc_appendable_chadd(app, get_mode_suffix(mode));
284 * Add a number to a prefix. This number will not be used a second time.
286 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
287 static unsigned long id = 0;
288 snprintf(buf, buflen, "%s%lu", prefix, ++id);
292 /*************************************************************
294 * (_) | | / _| | | | |
295 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
296 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
297 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
298 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
301 *************************************************************/
303 void ia32_emit_ident(ia32_emit_env_t *env, ident *id)
305 size_t len = get_id_strlen(id);
306 const char* str = get_id_str(id);
308 ia32_emit_string_len(env, str, len);
311 void ia32_emit_irprintf(ia32_emit_env_t *env, const char *fmt, ...)
317 ir_vsnprintf(buf, sizeof(buf), fmt, ap);
320 ia32_emit_string(env, buf);
323 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
325 const arch_register_t *reg = get_in_reg(node, pos);
326 const char *reg_name = arch_register_get_name(reg);
328 assert(pos < get_irn_arity(node));
330 ia32_emit_char(env, '%');
331 ia32_emit_string(env, reg_name);
334 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
335 const arch_register_t *reg = get_out_reg(node, pos);
336 const char *reg_name = arch_register_get_name(reg);
338 ia32_emit_char(env, '%');
339 ia32_emit_string(env, reg_name);
342 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
344 ia32_attr_t *attr = get_ia32_attr(node);
347 ia32_emit_char(env, '%');
348 ia32_emit_string(env, attr->x87[pos]->name);
351 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
356 switch(get_ia32_immop_type(node)) {
358 tv = get_ia32_Immop_tarval(node);
359 id = get_ident_for_tv(tv);
361 case ia32_ImmSymConst:
362 id = get_ia32_Immop_symconst(node);
366 ia32_emit_string(env, "BAD");
370 ia32_emit_ident(env, id);
373 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode)
375 ia32_emit_char(env, get_mode_suffix(mode));
378 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
380 ir_mode *mode = get_ia32_ls_mode(node);
382 ia32_emit_mode_suffix(env, mode);
385 static char get_xmm_mode_suffix(ir_mode *mode)
387 assert(mode_is_float(mode));
388 switch(get_mode_size_bits(mode)) {
399 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
401 ir_mode *mode = get_ia32_ls_mode(node);
402 assert(mode != NULL);
403 ia32_emit_char(env, 's');
404 ia32_emit_char(env, get_xmm_mode_suffix(mode));
407 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
409 ir_mode *mode = get_ia32_ls_mode(node);
410 assert(mode != NULL);
411 ia32_emit_char(env, get_xmm_mode_suffix(mode));
414 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
416 if(get_mode_size_bits(mode) == 32)
418 if(mode_is_signed(mode)) {
419 ia32_emit_char(env, 's');
421 ia32_emit_char(env, 'z');
426 * Emits registers and/or address mode of a binary operation.
428 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
429 switch(get_ia32_op_type(node)) {
431 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
432 ia32_emit_char(env, '$');
433 ia32_emit_immediate(env, node);
434 ia32_emit_cstring(env, ", ");
435 ia32_emit_source_register(env, node, 2);
437 const arch_register_t *in1 = get_in_reg(node, 2);
438 const arch_register_t *in2 = get_in_reg(node, 3);
439 const arch_register_t *out = produces_result(node) ? get_out_reg(node, 0) : NULL;
440 const arch_register_t *in;
443 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
444 out = out ? out : in1;
445 in_name = arch_register_get_name(in);
447 if (is_ia32_emit_cl(node)) {
448 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
452 ia32_emit_char(env, '%');
453 ia32_emit_string(env, in_name);
454 ia32_emit_cstring(env, ", %");
455 ia32_emit_string(env, arch_register_get_name(out));
459 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
460 assert(!produces_result(node) && "Source AM with Const must not produce result");
461 ia32_emit_am(env, node);
462 ia32_emit_cstring(env, ", $");
463 ia32_emit_immediate(env, node);
464 } else if (produces_result(node)) {
465 ia32_emit_am(env, node);
466 ia32_emit_cstring(env, ", ");
467 ia32_emit_dest_register(env, node, 0);
469 ia32_emit_am(env, node);
470 ia32_emit_cstring(env, ", ");
471 ia32_emit_source_register(env, node, 2);
475 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
476 ia32_emit_char(env, '$');
477 ia32_emit_immediate(env, node);
478 ia32_emit_cstring(env, ", ");
479 ia32_emit_am(env, node);
481 const arch_register_t *in1 = get_in_reg(node, get_irn_arity(node) == 5 ? 3 : 2);
482 ir_mode *mode = get_ia32_ls_mode(node);
485 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
487 if (is_ia32_emit_cl(node)) {
488 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
492 ia32_emit_char(env, '%');
493 ia32_emit_string(env, in_name);
494 ia32_emit_cstring(env, ", ");
495 ia32_emit_am(env, node);
499 assert(0 && "unsupported op type");
504 * Emits registers and/or address mode of a binary operation.
506 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
507 switch(get_ia32_op_type(node)) {
509 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
510 // should not happen...
513 ia32_attr_t *attr = get_ia32_attr(node);
514 const arch_register_t *in1 = attr->x87[0];
515 const arch_register_t *in2 = attr->x87[1];
516 const arch_register_t *out = attr->x87[2];
517 const arch_register_t *in;
519 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
520 out = out ? out : in1;
522 ia32_emit_char(env, '%');
523 ia32_emit_string(env, arch_register_get_name(in));
524 ia32_emit_cstring(env, ", %");
525 ia32_emit_string(env, arch_register_get_name(out));
530 ia32_emit_am(env, node);
533 assert(0 && "unsupported op type");
538 * Emits registers and/or address mode of a unary operation.
540 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node) {
541 switch(get_ia32_op_type(node)) {
543 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
544 ia32_emit_char(env, '$');
545 ia32_emit_immediate(env, node);
547 if (is_ia32_Mul(node) || is_ia32_IMul1OP(node)) {
548 ia32_emit_source_register(env, node, 3);
549 } else if(is_ia32_IDiv(node) || is_ia32_Div(node)) {
550 ia32_emit_source_register(env, node, 4);
551 } else if(is_ia32_Push(node)) {
552 ia32_emit_source_register(env, node, 2);
553 } else if(is_ia32_Pop(node)) {
554 ia32_emit_dest_register(env, node, 1);
556 ia32_emit_dest_register(env, node, 0);
562 ia32_emit_am(env, node);
565 assert(0 && "unsupported op type");
570 * Emits address mode.
572 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
573 ia32_am_flavour_t am_flav = get_ia32_am_flavour(node);
574 ident *id = get_ia32_am_sc(node);
575 int offs = get_ia32_am_offs_int(node);
577 /* just to be sure... */
578 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
582 if (is_ia32_am_sc_sign(node))
583 ia32_emit_char(env, '-');
584 ia32_emit_ident(env, id);
589 ia32_emit_irprintf(env, "%+d", offs);
591 ia32_emit_irprintf(env, "%d", offs);
595 if (am_flav & (ia32_B | ia32_I)) {
596 ia32_emit_char(env, '(');
599 if (am_flav & ia32_B) {
600 ia32_emit_source_register(env, node, 0);
603 /* emit index + scale */
604 if (am_flav & ia32_I) {
605 ia32_emit_char(env, ',');
606 ia32_emit_source_register(env, node, 1);
608 if (am_flav & ia32_S) {
609 ia32_emit_irprintf(env, ",%d", 1 << get_ia32_am_scale(node));
612 ia32_emit_char(env, ')');
618 * Formated print of commands and comments.
620 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
622 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
625 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
627 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
631 void ia32_write_line(ia32_emit_env_t *env)
633 char *finished_line = obstack_finish(env->obst);
635 fwrite(finished_line, env->linelength, 1, env->out);
637 obstack_free(env->obst, finished_line);
640 void ia32_pad_comment(ia32_emit_env_t *env)
642 while(env->linelength <= 30) {
643 ia32_emit_char(env, ' ');
645 ia32_emit_cstring(env, " ");
648 void ia32_emit_finish_line(ia32_emit_env_t *env, const ir_node *node)
651 const char *sourcefile;
655 ia32_emit_char(env, '\n');
656 ia32_write_line(env);
660 ia32_pad_comment(env);
661 ia32_emit_cstring(env, "/* ");
662 ia32_emit_irprintf(env, "%+F ", node);
664 dbg = get_irn_dbg_info(node);
665 sourcefile = be_retrieve_dbg_info(dbg, &lineno);
666 if(sourcefile != NULL) {
667 ia32_emit_string(env, sourcefile);
668 ia32_emit_irprintf(env, ":%u", lineno);
670 ia32_emit_cstring(env, " */\n");
671 ia32_write_line(env);
675 /*************************************************
678 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
679 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
680 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
681 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
683 *************************************************/
686 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
689 * coding of conditions
691 struct cmp2conditon_t {
697 * positive conditions for signed compares
699 static const struct cmp2conditon_t cmp2condition_s[] = {
700 { NULL, pn_Cmp_False }, /* always false */
701 { "e", pn_Cmp_Eq }, /* == */
702 { "l", pn_Cmp_Lt }, /* < */
703 { "le", pn_Cmp_Le }, /* <= */
704 { "g", pn_Cmp_Gt }, /* > */
705 { "ge", pn_Cmp_Ge }, /* >= */
706 { "ne", pn_Cmp_Lg }, /* != */
707 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
708 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
709 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
710 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
711 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
712 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
713 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
714 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
715 { NULL, pn_Cmp_True }, /* always true */
719 * positive conditions for unsigned compares
721 static const struct cmp2conditon_t cmp2condition_u[] = {
722 { NULL, pn_Cmp_False }, /* always false */
723 { "e", pn_Cmp_Eq }, /* == */
724 { "b", pn_Cmp_Lt }, /* < */
725 { "be", pn_Cmp_Le }, /* <= */
726 { "a", pn_Cmp_Gt }, /* > */
727 { "ae", pn_Cmp_Ge }, /* >= */
728 { "ne", pn_Cmp_Lg }, /* != */
729 { NULL, pn_Cmp_True }, /* always true */
733 * returns the condition code
735 static const char *get_cmp_suffix(int cmp_code)
737 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
738 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
740 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
741 return cmp2condition_u[cmp_code & 7].name;
743 return cmp2condition_s[cmp_code & 15].name;
747 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
749 ia32_emit_string(env, get_cmp_suffix(pnc));
754 * Returns the target block for a control flow node.
756 static ir_node *get_cfop_target_block(const ir_node *irn) {
757 return get_irn_link(irn);
761 * Returns the target label for a control flow node.
763 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
764 ir_node *block = get_cfop_target_block(node);
766 ia32_emit_cstring(env, BLOCK_PREFIX);
767 ia32_emit_irprintf(env, "%d", get_irn_node_nr(block));
770 /** Return the next block in Block schedule */
771 static ir_node *next_blk_sched(const ir_node *block) {
772 return get_irn_link(block);
776 * Returns the Proj with projection number proj and NOT mode_M
778 static ir_node *get_proj(const ir_node *node, long proj) {
779 const ir_edge_t *edge;
782 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
784 foreach_out_edge(node, edge) {
785 src = get_edge_src_irn(edge);
787 assert(is_Proj(src) && "Proj expected");
788 if (get_irn_mode(src) == mode_M)
791 if (get_Proj_proj(src) == proj)
798 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
800 static void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node,
801 ir_mode *mode, long pnc) {
802 const ir_node *proj_true;
803 const ir_node *proj_false;
804 const ir_node *block;
805 const ir_node *next_block;
808 /* get both Proj's */
809 proj_true = get_proj(node, pn_Cond_true);
810 assert(proj_true && "CondJmp without true Proj");
812 proj_false = get_proj(node, pn_Cond_false);
813 assert(proj_false && "CondJmp without false Proj");
815 /* for now, the code works for scheduled and non-schedules blocks */
816 block = get_nodes_block(node);
818 /* we have a block schedule */
819 next_block = next_blk_sched(block);
821 if (get_cfop_target_block(proj_true) == next_block) {
822 /* exchange both proj's so the second one can be omitted */
823 const ir_node *t = proj_true;
825 proj_true = proj_false;
828 pnc = get_negated_pnc(pnc, mode);
831 /* in case of unordered compare, check for parity */
832 if (pnc & pn_Cmp_Uo) {
833 ia32_emit_cstring(env, "\tjp ");
834 ia32_emit_cfop_target(env, proj_true);
835 ia32_emit_finish_line(env, proj_true);
838 ia32_emit_cstring(env, "\tj");
839 ia32_emit_cmp_suffix(env, pnc);
840 ia32_emit_char(env, ' ');
841 ia32_emit_cfop_target(env, proj_true);
842 ia32_emit_finish_line(env, proj_true);
844 /* the second Proj might be a fallthrough */
845 if (get_cfop_target_block(proj_false) != next_block) {
846 ia32_emit_cstring(env, "\tjmp ");
847 ia32_emit_cfop_target(env, proj_false);
848 ia32_emit_finish_line(env, proj_false);
850 ia32_emit_cstring(env, "\t/* fallthrough to");
851 ia32_emit_cfop_target(env, proj_false);
852 ia32_emit_cstring(env, " */");
853 ia32_emit_finish_line(env, proj_false);
858 * Emits code for conditional jump.
860 static void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
861 ia32_emit_cstring(env, "\tcmp ");
862 ia32_emit_binop(env, node);
863 ia32_emit_finish_line(env, node);
865 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
869 * Emits code for conditional jump with two variables.
871 static void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
872 CondJmp_emitter(env, node);
876 * Emits code for conditional test and jump.
878 static void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
879 if(is_ia32_ImmSymConst(node) || is_ia32_ImmConst(node)) {
880 ia32_emit_cstring(env, "\ttest $");
881 ia32_emit_immediate(env, node);
882 ia32_emit_cstring(env, ", ");
883 ia32_emit_source_register(env, node, 0);
884 ia32_emit_finish_line(env, node);
886 ia32_emit_cstring(env, "\ttest ");
887 ia32_emit_source_register(env, node, 1);
888 ia32_emit_cstring(env, ", ");
889 ia32_emit_source_register(env, node, 0);
890 ia32_emit_finish_line(env, node);
892 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
896 * Emits code for conditional test and jump with two variables.
898 static void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
899 TestJmp_emitter(env, node);
902 static void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
903 ia32_emit_cstring(env, "/* omitted redundant test */");
904 ia32_emit_finish_line(env, node);
906 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
909 static void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
910 ia32_emit_cstring(env, "/* omitted redundant test/cmp */");
911 ia32_emit_finish_line(env, node);
913 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
917 * Emits code for conditional SSE floating point jump with two variables.
919 static void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
920 ia32_emit_cstring(env, "\tucomi");
921 ia32_emit_xmm_mode_suffix(env, node);
922 ia32_emit_char(env, ' ');
923 ia32_emit_binop(env, node);
924 ia32_emit_finish_line(env, node);
926 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
930 * Emits code for conditional x87 floating point jump with two variables.
932 static void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
933 ia32_attr_t *attr = get_ia32_attr(node);
934 const char *reg = attr->x87[1]->name;
935 long pnc = get_ia32_pncode(node);
937 switch (get_ia32_irn_opcode(node)) {
938 case iro_ia32_fcomrJmp:
939 pnc = get_inversed_pnc(pnc);
940 case iro_ia32_fcomJmp:
942 ia32_emit_cstring(env, "\tfucom ");
944 case iro_ia32_fcomrpJmp:
945 pnc = get_inversed_pnc(pnc);
946 case iro_ia32_fcompJmp:
947 ia32_emit_cstring(env, "\tfucomp ");
949 case iro_ia32_fcomrppJmp:
950 pnc = get_inversed_pnc(pnc);
951 case iro_ia32_fcomppJmp:
952 ia32_emit_cstring(env, "\tfucompp ");
958 ia32_emit_char(env, '%');
959 ia32_emit_string(env, reg);
961 ia32_emit_finish_line(env, node);
963 ia32_emit_cstring(env, "\tfnstsw %ax");
964 ia32_emit_finish_line(env, node);
965 ia32_emit_cstring(env, "\tsahf");
966 ia32_emit_finish_line(env, node);
968 finish_CondJmp(env, node, mode_E, pnc);
971 static void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
972 long pnc = get_ia32_pncode(node);
973 int is_PsiCondCMov = is_ia32_PsiCondCMov(node);
974 int idx_left = 2 - is_PsiCondCMov;
975 int idx_right = 3 - is_PsiCondCMov;
976 const arch_register_t *in1, *in2, *out;
978 out = arch_get_irn_register(env->arch_env, node);
979 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_left));
980 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_right));
982 /* we have to emit the cmp first, because the destination register */
983 /* could be one of the compare registers */
984 if (is_ia32_CmpCMov(node)) {
985 ia32_emit_cstring(env, "\tcmp ");
986 ia32_emit_source_register(env, node, 1);
987 ia32_emit_cstring(env, ", ");
988 ia32_emit_source_register(env, node, 0);
989 } else if (is_ia32_xCmpCMov(node)) {
990 ia32_emit_cstring(env, "\tucomis");
991 ia32_emit_mode_suffix(env, get_irn_mode(node));
992 ia32_emit_char(env, ' ');
993 ia32_emit_source_register(env, node, 1);
994 ia32_emit_cstring(env, ", ");
995 ia32_emit_source_register(env, node, 0);
996 } else if (is_PsiCondCMov) {
997 /* omit compare because flags are already set by And/Or */
998 ia32_emit_cstring(env, "\ttest ");
999 ia32_emit_source_register(env, node, 0);
1000 ia32_emit_cstring(env, ", ");
1001 ia32_emit_source_register(env, node, 0);
1003 assert(0 && "unsupported CMov");
1005 ia32_emit_finish_line(env, node);
1007 if (REGS_ARE_EQUAL(out, in2)) {
1008 /* best case: default in == out -> do nothing */
1009 } else if (REGS_ARE_EQUAL(out, in1)) {
1010 ir_node *n = (ir_node*) node;
1011 /* true in == out -> need complement compare and exchange true and default in */
1012 ir_node *t = get_irn_n(n, idx_left);
1013 set_irn_n(n, idx_left, get_irn_n(n, idx_right));
1014 set_irn_n(n, idx_right, t);
1016 pnc = get_negated_pnc(pnc, get_irn_mode(node));
1018 /* out is different from in: need copy default -> out */
1019 if (is_PsiCondCMov) {
1020 ia32_emit_cstring(env, "\tmovl ");
1021 ia32_emit_dest_register(env, node, 2);
1022 ia32_emit_cstring(env, ", ");
1023 ia32_emit_dest_register(env, node, 0);
1025 ia32_emit_cstring(env, "\tmovl ");
1026 ia32_emit_source_register(env, node, 3);
1027 ia32_emit_cstring(env, ", ");
1028 ia32_emit_dest_register(env, node, 0);
1030 ia32_emit_finish_line(env, node);
1033 if (is_PsiCondCMov) {
1034 ia32_emit_cstring(env, "\tcmov");
1035 ia32_emit_cmp_suffix(env, pnc);
1036 ia32_emit_cstring(env, "l ");
1037 ia32_emit_source_register(env, node, 1);
1038 ia32_emit_cstring(env, ", ");
1039 ia32_emit_dest_register(env, node, 0);
1041 ia32_emit_cstring(env, "\tcmov");
1042 ia32_emit_cmp_suffix(env, pnc);
1043 ia32_emit_cstring(env, "l ");
1044 ia32_emit_source_register(env, node, 2);
1045 ia32_emit_cstring(env, ", ");
1046 ia32_emit_dest_register(env, node, 0);
1048 ia32_emit_finish_line(env, node);
1051 static void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1052 CMov_emitter(env, node);
1055 static void emit_ia32_PsiCondCMov(ia32_emit_env_t *env, const ir_node *node) {
1056 CMov_emitter(env, node);
1059 static void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1060 CMov_emitter(env, node);
1063 static void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
1064 int pnc = get_ia32_pncode(node);
1065 const char *reg8bit;
1066 const arch_register_t *out;
1068 out = arch_get_irn_register(env->arch_env, node);
1069 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1071 if (is_ia32_CmpSet(node)) {
1072 ia32_emit_cstring(env, "\tcmp ");
1073 ia32_emit_binop(env, node);
1074 } else if (is_ia32_xCmpSet(node)) {
1075 ia32_emit_cstring(env, "\tucomis");
1076 ia32_emit_mode_suffix(env, get_irn_mode(get_irn_n(node, 2)));
1077 ia32_emit_char(env, ' ');
1078 ia32_emit_binop(env, node);
1079 } else if (is_ia32_PsiCondSet(node)) {
1080 ia32_emit_cstring(env, "\tcmp $0, ");
1081 ia32_emit_source_register(env, node, 0);
1083 assert(0 && "unsupported Set");
1085 ia32_emit_finish_line(env, node);
1087 /* use mov to clear target because it doesn't affect the eflags */
1088 ia32_emit_cstring(env, "\tmovl $0, %");
1089 ia32_emit_string(env, arch_register_get_name(out));
1090 ia32_emit_finish_line(env, node);
1092 ia32_emit_cstring(env, "\tset");
1093 ia32_emit_cmp_suffix(env, pnc);
1094 ia32_emit_cstring(env, " %");
1095 ia32_emit_string(env, reg8bit);
1096 ia32_emit_finish_line(env, node);
1099 static void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1100 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1103 static void emit_ia32_PsiCondSet(ia32_emit_env_t *env, const ir_node *node) {
1104 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 0)));
1107 static void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1108 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1111 static void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1113 long pnc = get_ia32_pncode(node);
1114 long unord = pnc & pn_Cmp_Uo;
1116 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1119 case pn_Cmp_Leg: /* odered */
1122 case pn_Cmp_Uo: /* unordered */
1126 case pn_Cmp_Eq: /* == */
1130 case pn_Cmp_Lt: /* < */
1134 case pn_Cmp_Le: /* <= */
1138 case pn_Cmp_Gt: /* > */
1142 case pn_Cmp_Ge: /* >= */
1146 case pn_Cmp_Lg: /* != */
1151 assert(sse_pnc >= 0 && "unsupported compare");
1153 if (unord && sse_pnc != 3) {
1155 We need a separate compare against unordered.
1156 Quick and Dirty solution:
1157 - get some memory on stack
1161 - and result and stored result
1164 ia32_emit_cstring(env, "\tsubl $8, %esp");
1165 ia32_emit_finish_line(env, node);
1167 ia32_emit_cstring(env, "\tcmpsd $3, ");
1168 ia32_emit_binop(env, node);
1169 ia32_emit_finish_line(env, node);
1171 ia32_emit_cstring(env, "\tmovsd ");
1172 ia32_emit_dest_register(env, node, 0);
1173 ia32_emit_cstring(env, ", (%esp)");
1174 ia32_emit_finish_line(env, node);
1177 ia32_emit_cstring(env, "\tcmpsd ");
1178 ia32_emit_irprintf(env, "%d, ", sse_pnc);
1179 ia32_emit_binop(env, node);
1180 ia32_emit_finish_line(env, node);
1182 if (unord && sse_pnc != 3) {
1183 ia32_emit_cstring(env, "\tandpd (%esp), ");
1184 ia32_emit_dest_register(env, node, 0);
1185 ia32_emit_finish_line(env, node);
1187 ia32_emit_cstring(env, "\taddl $8, %esp");
1188 ia32_emit_finish_line(env, node);
1192 /*********************************************************
1195 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1196 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1197 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1198 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1201 *********************************************************/
1203 /* jump table entry (target and corresponding number) */
1204 typedef struct _branch_t {
1209 /* jump table for switch generation */
1210 typedef struct _jmp_tbl_t {
1211 ir_node *defProj; /**< default target */
1212 int min_value; /**< smallest switch case */
1213 int max_value; /**< largest switch case */
1214 int num_branches; /**< number of jumps */
1215 char *label; /**< label of the jump table */
1216 branch_t *branches; /**< jump array */
1220 * Compare two variables of type branch_t. Used to sort all switch cases
1222 static int ia32_cmp_branch_t(const void *a, const void *b) {
1223 branch_t *b1 = (branch_t *)a;
1224 branch_t *b2 = (branch_t *)b;
1226 if (b1->value <= b2->value)
1233 * Emits code for a SwitchJmp (creates a jump table if
1234 * possible otherwise a cmp-jmp cascade). Port from
1237 static void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1238 unsigned long interval;
1243 const ir_edge_t *edge;
1245 /* fill the table structure */
1246 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1247 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1249 tbl.num_branches = get_irn_n_edges(node);
1250 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1251 tbl.min_value = INT_MAX;
1252 tbl.max_value = INT_MIN;
1255 /* go over all proj's and collect them */
1256 foreach_out_edge(node, edge) {
1257 proj = get_edge_src_irn(edge);
1258 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1260 pnc = get_Proj_proj(proj);
1262 /* create branch entry */
1263 tbl.branches[i].target = proj;
1264 tbl.branches[i].value = pnc;
1266 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1267 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1269 /* check for default proj */
1270 if (pnc == get_ia32_pncode(node)) {
1271 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1278 /* sort the branches by their number */
1279 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1281 /* two-complement's magic make this work without overflow */
1282 interval = tbl.max_value - tbl.min_value;
1284 /* emit the table */
1285 ia32_emit_cstring(env, "\tcmpl $");
1286 ia32_emit_irprintf(env, "%u, ", interval);
1287 ia32_emit_source_register(env, node, 0);
1288 ia32_emit_finish_line(env, node);
1290 ia32_emit_cstring(env, "\tja ");
1291 ia32_emit_cfop_target(env, tbl.defProj);
1292 ia32_emit_finish_line(env, node);
1294 if (tbl.num_branches > 1) {
1296 ia32_emit_cstring(env, "\tjmp *");
1297 ia32_emit_string(env, tbl.label);
1298 ia32_emit_cstring(env, "(,");
1299 ia32_emit_source_register(env, node, 0);
1300 ia32_emit_cstring(env, ",4)");
1301 ia32_emit_finish_line(env, node);
1303 ia32_switch_section(env->out, SECTION_RODATA);
1304 ia32_emit_cstring(env, "\t.align 4\n");
1305 ia32_write_line(env);
1307 ia32_emit_string(env, tbl.label);
1308 ia32_emit_cstring(env, ":\n");
1309 ia32_write_line(env);
1311 ia32_emit_cstring(env, ".long ");
1312 ia32_emit_cfop_target(env, tbl.branches[0].target);
1313 ia32_emit_finish_line(env, NULL);
1315 last_value = tbl.branches[0].value;
1316 for (i = 1; i < tbl.num_branches; ++i) {
1317 while (++last_value < tbl.branches[i].value) {
1318 ia32_emit_cstring(env, ".long ");
1319 ia32_emit_cfop_target(env, tbl.defProj);
1320 ia32_emit_finish_line(env, NULL);
1322 ia32_emit_cstring(env, ".long ");
1323 ia32_emit_cfop_target(env, tbl.branches[i].target);
1324 ia32_emit_finish_line(env, NULL);
1326 ia32_switch_section(env->out, SECTION_TEXT);
1328 /* one jump is enough */
1329 ia32_emit_cstring(env, "\tjmp ");
1330 ia32_emit_cfop_target(env, tbl.branches[0].target);
1331 ia32_emit_finish_line(env, node);
1341 * Emits code for a unconditional jump.
1343 static void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1344 ir_node *block, *next_block;
1346 /* for now, the code works for scheduled and non-schedules blocks */
1347 block = get_nodes_block(node);
1349 /* we have a block schedule */
1350 next_block = next_blk_sched(block);
1351 if (get_cfop_target_block(node) != next_block) {
1352 ia32_emit_cstring(env, "\tjmp ");
1353 ia32_emit_cfop_target(env, node);
1355 ia32_emit_cstring(env, "\t/* fallthrough to ");
1356 ia32_emit_cfop_target(env, node);
1357 ia32_emit_cstring(env, " */");
1359 ia32_emit_finish_line(env, node);
1362 /**********************************
1365 * | | ___ _ __ _ _| |_) |
1366 * | | / _ \| '_ \| | | | _ <
1367 * | |___| (_) | |_) | |_| | |_) |
1368 * \_____\___/| .__/ \__, |____/
1371 **********************************/
1374 * Emit movsb/w instructions to make mov count divideable by 4
1376 static void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1377 ia32_emit_cstring(env, "\tcld");
1378 ia32_emit_finish_line(env, NULL);
1382 ia32_emit_cstring(env, "\tmovsb");
1383 ia32_emit_finish_line(env, NULL);
1386 ia32_emit_cstring(env, "\tmovsw");
1387 ia32_emit_finish_line(env, NULL);
1390 ia32_emit_cstring(env, "\tmovsb");
1391 ia32_emit_finish_line(env, NULL);
1392 ia32_emit_cstring(env, "\tmovsw");
1393 ia32_emit_finish_line(env, NULL);
1399 * Emit rep movsd instruction for memcopy.
1401 static void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1402 tarval *tv = get_ia32_Immop_tarval(node);
1403 int rem = get_tarval_long(tv);
1405 emit_CopyB_prolog(env, rem);
1407 ia32_emit_cstring(env, "\trep movsd");
1408 ia32_emit_finish_line(env, node);
1412 * Emits unrolled memcopy.
1414 static void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1415 tarval *tv = get_ia32_Immop_tarval(node);
1416 int size = get_tarval_long(tv);
1418 emit_CopyB_prolog(env, size & 0x3);
1422 ia32_emit_cstring(env, "\tmovsd");
1423 ia32_emit_finish_line(env, NULL);
1429 /***************************
1433 * | | / _ \| '_ \ \ / /
1434 * | |___| (_) | | | \ V /
1435 * \_____\___/|_| |_|\_/
1437 ***************************/
1440 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1442 static void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1443 ir_mode *ls_mode = get_ia32_ls_mode(node);
1444 int ls_bits = get_mode_size_bits(ls_mode);
1446 ia32_emit_cstring(env, "\tcvt");
1448 if(is_ia32_Conv_I2FP(node)) {
1450 ia32_emit_cstring(env, "si2ss");
1452 ia32_emit_cstring(env, "si2sd");
1454 } else if(is_ia32_Conv_FP2I(node)) {
1456 ia32_emit_cstring(env, "ss2si");
1458 ia32_emit_cstring(env, "sd2si");
1461 assert(is_ia32_Conv_FP2FP(node));
1463 ia32_emit_cstring(env, "sd2ss");
1465 ia32_emit_cstring(env, "ss2sd");
1468 ia32_emit_char(env, ' ');
1470 switch(get_ia32_op_type(node)) {
1472 ia32_emit_source_register(env, node, 2);
1473 ia32_emit_cstring(env, ", ");
1474 ia32_emit_dest_register(env, node, 0);
1476 case ia32_AddrModeS:
1477 ia32_emit_dest_register(env, node, 0);
1478 ia32_emit_cstring(env, ", ");
1479 ia32_emit_am(env, node);
1482 assert(0 && "unsupported op type for Conv");
1484 ia32_emit_finish_line(env, node);
1487 static void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1488 emit_ia32_Conv_with_FP(env, node);
1491 static void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1492 emit_ia32_Conv_with_FP(env, node);
1495 static void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1496 emit_ia32_Conv_with_FP(env, node);
1500 * Emits code for an Int conversion.
1502 static void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1503 const char *sign_suffix;
1504 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1505 int smaller_bits = get_mode_size_bits(smaller_mode);
1507 const arch_register_t *in_reg, *out_reg;
1509 assert(!mode_is_float(smaller_mode));
1510 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1512 signed_mode = mode_is_signed(smaller_mode);
1513 if(smaller_bits == 32) {
1514 // this should not happen as it's no convert
1518 sign_suffix = signed_mode ? "s" : "z";
1521 switch(get_ia32_op_type(node)) {
1523 in_reg = get_in_reg(node, 2);
1524 out_reg = get_out_reg(node, 0);
1526 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1527 REGS_ARE_EQUAL(out_reg, in_reg) &&
1530 /* argument and result are both in EAX and */
1531 /* signedness is ok: -> use converts */
1532 if (smaller_bits == 8) {
1533 ia32_emit_cstring(env, "\tcbtw");
1534 } else if (smaller_bits == 16) {
1535 ia32_emit_cstring(env, "\tcwtl");
1539 } else if (REGS_ARE_EQUAL(out_reg, in_reg) && !signed_mode) {
1540 /* argument and result are in the same register */
1541 /* and signedness is ok: -> use and with mask */
1542 int mask = (1 << smaller_bits) - 1;
1543 ia32_emit_cstring(env, "\tandl $0x");
1544 ia32_emit_irprintf(env, "%x, ", mask);
1545 ia32_emit_dest_register(env, node, 0);
1547 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1549 ia32_emit_cstring(env, "\tmov");
1550 ia32_emit_string(env, sign_suffix);
1551 ia32_emit_mode_suffix(env, smaller_mode);
1552 ia32_emit_cstring(env, "l %");
1553 ia32_emit_string(env, sreg);
1554 ia32_emit_cstring(env, ", ");
1555 ia32_emit_dest_register(env, node, 0);
1558 case ia32_AddrModeS: {
1559 ia32_emit_cstring(env, "\tmov");
1560 ia32_emit_string(env, sign_suffix);
1561 ia32_emit_mode_suffix(env, smaller_mode);
1562 ia32_emit_cstring(env, "l %");
1563 ia32_emit_am(env, node);
1564 ia32_emit_cstring(env, ", ");
1565 ia32_emit_dest_register(env, node, 0);
1569 assert(0 && "unsupported op type for Conv");
1571 ia32_emit_finish_line(env, node);
1575 * Emits code for an 8Bit Int conversion.
1577 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1578 emit_ia32_Conv_I2I(env, node);
1582 /*******************************************
1585 * | |__ ___ _ __ ___ __| | ___ ___
1586 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1587 * | |_) | __/ | | | (_) | (_| | __/\__ \
1588 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1590 *******************************************/
1593 * Emits a backend call
1595 static void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1596 ir_entity *ent = be_Call_get_entity(node);
1598 ia32_emit_cstring(env, "\tcall ");
1600 ia32_emit_string(env, get_entity_ld_name(ent));
1602 ia32_emit_char(env, '*');
1603 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1605 ia32_emit_finish_line(env, node);
1609 * Emits code to increase stack pointer.
1611 static void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1612 int offs = be_get_IncSP_offset(node);
1618 ia32_emit_cstring(env, "\tsubl $");
1619 ia32_emit_irprintf(env, "%u, ", offs);
1620 ia32_emit_source_register(env, node, 0);
1622 ia32_emit_cstring(env, "\taddl $");
1623 ia32_emit_irprintf(env, "%u, ", -offs);
1624 ia32_emit_source_register(env, node, 0);
1626 ia32_emit_finish_line(env, node);
1630 * Emits code to set stack pointer.
1632 static void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1633 ia32_emit_cstring(env, "\tmovl ");
1634 ia32_emit_source_register(env, node, 2);
1635 ia32_emit_cstring(env, ", ");
1636 ia32_emit_dest_register(env, node, 0);
1637 ia32_emit_finish_line(env, node);
1641 * Emits code for Copy/CopyKeep.
1643 static void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op) {
1644 const arch_env_t *aenv = env->arch_env;
1646 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1647 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1650 if (mode_is_float(get_irn_mode(node))) {
1651 ia32_emit_cstring(env, "\tmovsd ");
1652 ia32_emit_source_register(env, node, 0);
1653 ia32_emit_cstring(env, ", ");
1654 ia32_emit_dest_register(env, node, 0);
1656 ia32_emit_cstring(env, "\tmovl ");
1657 ia32_emit_source_register(env, node, 0);
1658 ia32_emit_cstring(env, ", ");
1659 ia32_emit_dest_register(env, node, 0);
1661 ia32_emit_finish_line(env, node);
1664 static void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1665 Copy_emitter(env, node, be_get_Copy_op(node));
1668 static void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1669 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1673 * Emits code for exchange.
1675 static void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1676 const arch_register_t *in1, *in2;
1677 const arch_register_class_t *cls1, *cls2;
1679 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1680 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1682 cls1 = arch_register_get_class(in1);
1683 cls2 = arch_register_get_class(in2);
1685 assert(cls1 == cls2 && "Register class mismatch at Perm");
1687 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1689 if(emit_env->isa->opt_arch == arch_athlon) {
1690 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1691 // it is often beneficial to use the 3 xor trick instead of an xchg
1693 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1695 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1697 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1700 ia32_emit_cstring(env, "\txchg ");
1701 ia32_emit_source_register(env, node, 1);
1702 ia32_emit_cstring(env, ", ");
1703 ia32_emit_source_register(env, node, 0);
1704 ia32_emit_finish_line(env, node);
1708 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1709 ia32_emit_cstring(env, "\tpxorq ");
1710 ia32_emit_source_register(env, node, 1);
1711 ia32_emit_cstring(env, ", ");
1712 ia32_emit_source_register(env, node, 0);
1713 ia32_emit_finish_line(env, NULL);
1715 ia32_emit_cstring(env, "\tpxorq ");
1716 ia32_emit_source_register(env, node, 0);
1717 ia32_emit_cstring(env, ", ");
1718 ia32_emit_source_register(env, node, 1);
1719 ia32_emit_finish_line(env, NULL);
1721 ia32_emit_cstring(env, "\tpxorq ");
1722 ia32_emit_source_register(env, node, 1);
1723 ia32_emit_cstring(env, ", ");
1724 ia32_emit_source_register(env, node, 0);
1725 ia32_emit_finish_line(env, node);
1726 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1728 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1734 * Emits code for Constant loading.
1736 static void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1737 ir_mode *mode = get_irn_mode(node);
1738 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1740 if (imm_tp == ia32_ImmSymConst) {
1741 ia32_emit_cstring(env, "\tmovl $");
1742 ia32_emit_immediate(env, node);
1743 ia32_emit_cstring(env, ", ");
1744 ia32_emit_dest_register(env, node, 0);
1746 tarval *tv = get_ia32_Immop_tarval(node);
1747 assert(mode == mode_Iu);
1748 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1749 if (tarval_is_null(tv)) {
1750 if (env->isa->opt_arch == arch_pentium_4) {
1751 /* P4 prefers sub r, r, others xor r, r */
1752 ia32_emit_cstring(env, "\tsubl ");
1754 ia32_emit_cstring(env, "\txorl ");
1756 ia32_emit_dest_register(env, node, 0);
1757 ia32_emit_cstring(env, ", ");
1758 ia32_emit_dest_register(env, node, 0);
1760 ia32_emit_cstring(env, "\tmovl $");
1761 ia32_emit_immediate(env, node);
1762 ia32_emit_cstring(env, ", ");
1763 ia32_emit_dest_register(env, node, 0);
1766 ia32_emit_finish_line(env, node);
1770 * Emits code to load the TLS base
1772 static void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1773 ia32_emit_cstring(env, "\tmovl %gs:0, ");
1774 ia32_emit_dest_register(env, node, 0);
1775 ia32_emit_finish_line(env, node);
1778 static void emit_be_Return(ia32_emit_env_t *env, const ir_node *node) {
1779 ia32_emit_cstring(env, "\tret");
1780 ia32_emit_finish_line(env, node);
1783 static void emit_Nothing(ia32_emit_env_t *env, const ir_node *node) {
1787 /***********************************************************************************
1790 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1791 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1792 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1793 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1795 ***********************************************************************************/
1798 * Enters the emitter functions for handled nodes into the generic
1799 * pointer of an opcode.
1801 static void ia32_register_emitters(void) {
1803 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1804 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1805 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1806 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1807 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1808 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1810 /* first clear the generic function pointer for all ops */
1811 clear_irp_opcodes_generic_func();
1813 /* register all emitter functions defined in spec */
1814 ia32_register_spec_emitters();
1816 /* other ia32 emitter functions */
1822 IA32_EMIT(PsiCondCMov);
1824 IA32_EMIT(PsiCondSet);
1825 IA32_EMIT(SwitchJmp);
1828 IA32_EMIT(Conv_I2FP);
1829 IA32_EMIT(Conv_FP2I);
1830 IA32_EMIT(Conv_FP2FP);
1831 IA32_EMIT(Conv_I2I);
1832 IA32_EMIT(Conv_I2I8Bit);
1837 IA32_EMIT(xCmpCMov);
1838 IA32_EMIT(xCondJmp);
1839 IA32_EMIT2(fcomJmp, x87CondJmp);
1840 IA32_EMIT2(fcompJmp, x87CondJmp);
1841 IA32_EMIT2(fcomppJmp, x87CondJmp);
1842 IA32_EMIT2(fcomrJmp, x87CondJmp);
1843 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1844 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1846 /* benode emitter */
1872 static const char *last_name = NULL;
1873 static unsigned last_line = -1;
1874 static unsigned num = -1;
1877 * Emit the debug support for node node.
1879 static void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
1880 dbg_info *db = get_irn_dbg_info(node);
1882 const char *fname = be_retrieve_dbg_info(db, &lineno);
1884 if (! env->cg->birg->main_env->options->stabs_debug_support)
1888 if (last_name != fname) {
1890 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
1893 if (last_line != lineno) {
1897 snprintf(name, sizeof(name), ".LM%u", ++num);
1899 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
1900 fprintf(F, "%s:\n", name);
1905 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
1908 * Emits code for a node.
1910 static void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
1911 ir_op *op = get_irn_op(node);
1912 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1914 DBG((mod, LEVEL_1, "emitting code for %+F\n", node));
1916 if (op->ops.generic) {
1917 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1918 ia32_emit_dbg(env, node);
1919 (*func) (env, node);
1921 emit_Nothing(env, node);
1922 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
1927 * Emits gas alignment directives
1929 static void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
1930 ia32_emit_cstring(env, "\t.p2align ");
1931 ia32_emit_irprintf(env, "%u,,%u\n", align, skip);
1932 ia32_write_line(env);
1936 * Emits gas alignment directives for Functions depended on cpu architecture.
1938 static void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
1940 unsigned maximum_skip;
1955 maximum_skip = (1 << align) - 1;
1956 ia32_emit_alignment(env, align, maximum_skip);
1960 * Emits gas alignment directives for Labels depended on cpu architecture.
1962 static void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
1963 unsigned align; unsigned maximum_skip;
1978 maximum_skip = (1 << align) - 1;
1979 ia32_emit_alignment(env, align, maximum_skip);
1982 static int is_first_loop_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev_block) {
1983 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
1984 double block_freq, prev_freq;
1985 static const double DELTA = .0001;
1986 cpu_support cpu = env->isa->opt_arch;
1988 if(exec_freq == NULL)
1990 if(cpu == arch_i386 || cpu == arch_i486)
1993 block_freq = get_block_execfreq(exec_freq, block);
1994 prev_freq = get_block_execfreq(exec_freq, prev_block);
1996 if(block_freq < DELTA || prev_freq < DELTA)
1999 block_freq /= prev_freq;
2003 case arch_athlon_64:
2005 return block_freq > 3;
2010 return block_freq > 2;
2014 * Walks over the nodes in a block connected by scheduling edges
2015 * and emits code for each node.
2017 static void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block) {
2018 ir_graph *irg = get_irn_irg(block);
2019 ir_node *start_block = get_irg_start_block(irg);
2021 const ir_node *node;
2024 assert(is_Block(block));
2026 if (block == start_block)
2029 if (need_label && get_irn_arity(block) == 1) {
2030 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2032 if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2036 /* special case: if one of our cfg preds is a switch-jmp we need a label, */
2037 /* otherwise there might be jump table entries jumping to */
2038 /* non-existent (omitted) labels */
2039 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2040 ir_node *pred = get_Block_cfgpred(block, i);
2042 if (is_Proj(pred)) {
2043 assert(get_irn_mode(pred) == mode_X);
2044 if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
2054 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2056 /* align the loop headers */
2057 if (! is_first_loop_block(env, block, last_block)) {
2058 /* align blocks where the previous block has no fallthrough */
2059 arity = get_irn_arity(block);
2061 for (i = 0; i < arity; ++i) {
2062 ir_node *predblock = get_Block_cfgpred_block(block, i);
2064 if (predblock == last_block) {
2072 ia32_emit_align_label(env, env->isa->opt_arch);
2074 ia32_emit_cstring(env, BLOCK_PREFIX);
2075 ia32_emit_irprintf(env, "%d:", get_irn_node_nr(block));
2076 ia32_pad_comment(env);
2077 ia32_emit_cstring(env, " /* preds:");
2079 /* emit list of pred blocks in comment */
2080 arity = get_irn_arity(block);
2081 for (i = 0; i < arity; ++i) {
2082 ir_node *predblock = get_Block_cfgpred_block(block, i);
2083 ia32_emit_irprintf(env, " %d", get_irn_node_nr(predblock));
2086 if (exec_freq != NULL) {
2087 ia32_emit_irprintf(env, " freq: %f", get_block_execfreq(exec_freq, block));
2089 ia32_emit_cstring(env, " */\n");
2090 ia32_write_line(env);
2093 /* emit the contents of the block */
2094 ia32_emit_dbg(env, block);
2095 sched_foreach(block, node) {
2096 ia32_emit_node(env, node);
2101 * Emits code for function start.
2103 static void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2105 ir_entity *irg_ent = get_irg_entity(irg);
2106 const char *irg_name = get_entity_ld_name(irg_ent);
2107 cpu_support cpu = env->isa->opt_arch;
2108 const be_irg_t *birg = env->cg->birg;
2111 ia32_switch_section(F, SECTION_TEXT);
2112 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2113 ia32_emit_align_func(env, cpu);
2114 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2115 fprintf(F, ".globl %s\n", irg_name);
2117 ia32_dump_function_object(F, irg_name);
2118 fprintf(F, "%s:\n", irg_name);
2122 * Emits code for function end
2124 static void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2125 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2126 const be_irg_t *birg = env->cg->birg;
2129 ia32_dump_function_size(F, irg_name);
2130 be_dbg_method_end(birg->main_env->db_handle);
2136 * Sets labels for control flow nodes (jump target)
2138 static void ia32_gen_labels(ir_node *block, void *data) {
2140 int n = get_Block_n_cfgpreds(block);
2142 for (n--; n >= 0; n--) {
2143 pred = get_Block_cfgpred(block, n);
2144 set_irn_link(pred, block);
2149 * Main driver. Emits the code for one routine.
2151 void ia32_gen_routine(ia32_code_gen_t *cg, FILE *F, ir_graph *irg) {
2152 ia32_emit_env_t env;
2154 ir_node *last_block = NULL;
2156 struct obstack obst;
2158 obstack_init(&obst);
2161 env.arch_env = cg->arch_env;
2163 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2166 FIRM_DBG_REGISTER(env.mod, "firm.be.ia32.emitter");
2168 /* set the global arch_env (needed by print hooks) */
2169 arch_env = cg->arch_env;
2171 ia32_register_emitters();
2173 ia32_emit_func_prolog(&env, irg);
2174 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2176 n = ARR_LEN(cg->blk_sched);
2177 for (i = 0; i < n;) {
2180 block = cg->blk_sched[i];
2182 next_bl = i < n ? cg->blk_sched[i] : NULL;
2184 /* set here the link. the emitter expects to find the next block here */
2185 set_irn_link(block, next_bl);
2186 ia32_gen_block(&env, block, last_block);
2190 ia32_emit_func_epilog(&env, irg);