2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
131 /* We always pass the ir_node which is a pointer. */
132 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
133 return lc_arg_type_ptr;
138 * Returns the register at in position pos.
140 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
142 const arch_register_t *reg = NULL;
144 assert(get_irn_arity(irn) > pos && "Invalid IN position");
146 /* The out register of the operator at position pos is the
147 in register we need. */
148 op = get_irn_n(irn, pos);
150 reg = arch_get_irn_register(arch_env, op);
152 assert(reg && "no in register found");
154 /* in case of a joker register: just return a valid register */
155 if (arch_register_type_is(reg, joker)) {
156 arch_register_req_t req;
157 const arch_register_req_t *p_req;
159 /* ask for the requirements */
160 p_req = arch_get_register_req(arch_env, &req, irn, pos);
162 if (arch_register_req_is(p_req, limited)) {
163 /* in case of limited requirements: get the first allowed register */
165 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
168 p_req->limited(p_req->limited_env, bs);
169 idx = bitset_next_set(bs, 0);
170 reg = arch_register_for_index(p_req->cls, idx);
173 /* otherwise get first register in class */
174 reg = arch_register_for_index(p_req->cls, 0);
182 * Returns the register at out position pos.
184 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
186 const arch_register_t *reg = NULL;
188 /* 1st case: irn is not of mode_T, so it has only */
189 /* one OUT register -> good */
190 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
191 /* Proj with the corresponding projnum for the register */
193 if (get_irn_mode(irn) != mode_T) {
194 reg = arch_get_irn_register(arch_env, irn);
196 else if (is_ia32_irn(irn)) {
197 reg = get_ia32_out_reg(irn, pos);
200 const ir_edge_t *edge;
202 foreach_out_edge(irn, edge) {
203 proj = get_edge_src_irn(edge);
204 assert(is_Proj(proj) && "non-Proj from mode_T node");
205 if (get_Proj_proj(proj) == pos) {
206 reg = arch_get_irn_register(arch_env, proj);
212 assert(reg && "no out register found");
222 * Returns the name of the in register at position pos.
224 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
225 const arch_register_t *reg;
227 if (in_out == IN_REG) {
228 reg = get_in_reg(irn, pos);
230 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
231 /* FIXME: works for binop only */
232 assert(2 <= pos && pos <= 3);
233 reg = get_ia32_attr(irn)->x87[pos - 2];
237 /* destination address mode nodes don't have outputs */
238 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
242 reg = get_out_reg(irn, pos);
243 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
244 reg = get_ia32_attr(irn)->x87[pos + 2];
246 return arch_register_get_name(reg);
250 * Get the register name for a node.
252 static int ia32_get_reg_name(lc_appendable_t *app,
253 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
256 ir_node *irn = arg->v_ptr;
257 int nr = occ->width - 1;
260 return lc_appendable_snadd(app, "(null)", 6);
262 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
264 /* append the stupid % to register names */
265 lc_appendable_chadd(app, '%');
266 return lc_appendable_snadd(app, buf, strlen(buf));
270 * Get the x87 register name for a node.
272 static int ia32_get_x87_name(lc_appendable_t *app,
273 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
276 ir_node *irn = arg->v_ptr;
277 int nr = occ->width - 1;
281 return lc_appendable_snadd(app, "(null)", 6);
283 attr = get_ia32_attr(irn);
284 buf = attr->x87[nr]->name;
285 lc_appendable_chadd(app, '%');
286 return lc_appendable_snadd(app, buf, strlen(buf));
290 * Returns the tarval, offset or scale of an ia32 as a string.
292 static int ia32_const_to_str(lc_appendable_t *app,
293 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
296 ir_node *irn = arg->v_ptr;
299 return lc_arg_append(app, occ, "(null)", 6);
301 if (occ->conversion == 'C') {
302 buf = get_ia32_cnst(irn);
305 buf = get_ia32_am_offs(irn);
308 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
312 * Determines the SSE suffix depending on the mode.
314 static int ia32_get_mode_suffix(lc_appendable_t *app,
315 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
317 ir_node *irn = arg->v_ptr;
318 ir_mode *mode = get_irn_mode(irn);
320 if (mode == mode_T) {
321 mode = get_ia32_res_mode(irn);
323 mode = get_ia32_ls_mode(irn);
327 return lc_arg_append(app, occ, "(null)", 6);
329 if (mode_is_float(mode)) {
330 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
333 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
338 * Return the ia32 printf arg environment.
339 * We use the firm environment with some additional handlers.
341 const lc_arg_env_t *ia32_get_arg_env(void) {
342 static lc_arg_env_t *env = NULL;
344 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
345 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
346 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
347 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
350 /* extend the firm printer */
351 env = firm_get_arg_env();
353 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
354 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
355 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
356 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
357 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
358 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
364 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
365 switch(get_mode_size_bits(mode)) {
367 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
369 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
371 return (char *)arch_register_get_name(reg);
376 * Emits registers and/or address mode of a binary operation.
378 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
379 static char *buf = NULL;
381 /* verify that this function is never called on non-AM supporting operations */
382 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
384 #define PRODUCES_RESULT(n) \
385 (!(is_ia32_St(n) || \
386 is_ia32_Store8Bit(n) || \
387 is_ia32_CondJmp(n) || \
388 is_ia32_xCondJmp(n) || \
389 is_ia32_CmpSet(n) || \
390 is_ia32_xCmpSet(n) || \
391 is_ia32_SwitchJmp(n)))
394 buf = xcalloc(1, SNPRINTF_BUF_LEN);
397 memset(buf, 0, SNPRINTF_BUF_LEN);
400 switch(get_ia32_op_type(n)) {
402 if (is_ia32_ImmConst(n)) {
403 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
405 else if (is_ia32_ImmSymConst(n)) {
406 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
409 const arch_register_t *in1 = get_in_reg(n, 2);
410 const arch_register_t *in2 = get_in_reg(n, 3);
411 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
412 const arch_register_t *in;
415 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
416 out = out ? out : in1;
417 in_name = arch_register_get_name(in);
419 if (is_ia32_emit_cl(n)) {
420 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
424 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
428 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
429 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
430 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
433 if (PRODUCES_RESULT(n)) {
434 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
437 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
442 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
443 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
444 ia32_emit_am(n, env),
445 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
446 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
449 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
450 ir_mode *mode = get_ia32_res_mode(n);
453 mode = mode ? mode : get_ia32_ls_mode(n);
454 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
456 if (is_ia32_emit_cl(n)) {
457 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
461 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
465 assert(0 && "unsupported op type");
468 #undef PRODUCES_RESULT
474 * Returns the xxx PTR string for a given mode
476 * @param mode the mode
477 * @param x87_insn if non-zero returns the string for a x87 instruction
478 * else for a SSE instruction
480 static const char *pointer_size(ir_mode *mode, int x87_insn)
483 switch (get_mode_size_bits(mode)) {
484 case 8: return "BYTE PTR";
485 case 16: return "WORD PTR";
486 case 32: return "DWORD PTR";
492 case 96: return "XWORD PTR";
493 default: return NULL;
500 * Emits registers and/or address mode of a binary operation.
502 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
503 static char *buf = NULL;
505 /* verify that this function is never called on non-AM supporting operations */
506 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
509 buf = xcalloc(1, SNPRINTF_BUF_LEN);
512 memset(buf, 0, SNPRINTF_BUF_LEN);
515 switch(get_ia32_op_type(n)) {
517 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
518 ir_mode *mode = get_ia32_ls_mode(n);
519 const char *p = pointer_size(mode, 1);
520 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
523 ia32_attr_t *attr = get_ia32_attr(n);
524 const arch_register_t *in1 = attr->x87[0];
525 const arch_register_t *in2 = attr->x87[1];
526 const arch_register_t *out = attr->x87[2];
527 const arch_register_t *in;
530 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
531 out = out ? out : in1;
532 in_name = arch_register_get_name(in);
534 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
539 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
542 assert(0 && "unsupported op type");
549 * Emits registers and/or address mode of a unary operation.
551 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
552 static char *buf = NULL;
555 buf = xcalloc(1, SNPRINTF_BUF_LEN);
558 memset(buf, 0, SNPRINTF_BUF_LEN);
561 switch(get_ia32_op_type(n)) {
563 if (is_ia32_ImmConst(n)) {
564 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
566 else if (is_ia32_ImmSymConst(n)) {
567 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
570 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
571 /* MulS and Mulh implicitly multiply by EAX */
572 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
573 } else if(is_ia32_Push(n)) {
574 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
576 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
581 assert(!is_ia32_Push(n));
582 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
586 Mulh is emitted via emit_unop
587 imul [MEM] means EDX:EAX <- EAX * [MEM]
589 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
590 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
593 assert(0 && "unsupported op type");
600 * Emits address mode.
602 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
603 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
607 static struct obstack *obst = NULL;
608 ir_mode *mode = get_ia32_ls_mode(n);
610 if (! is_ia32_Lea(n))
611 assert(mode && "AM node must have ls_mode attribute set.");
614 obst = xcalloc(1, sizeof(*obst));
617 obstack_free(obst, NULL);
620 /* obstack_free with NULL results in an uninitialized obstack */
623 p = pointer_size(mode, ia32_has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
625 obstack_printf(obst, "%s ", p);
627 /* emit address mode symconst */
628 if (get_ia32_am_sc(n)) {
629 if (is_ia32_am_sc_sign(n))
630 obstack_printf(obst, "-");
631 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
634 if (am_flav & ia32_B) {
635 obstack_printf(obst, "[");
636 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
640 if (am_flav & ia32_I) {
642 obstack_printf(obst, "+");
645 obstack_printf(obst, "[");
648 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
650 if (am_flav & ia32_S) {
651 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
657 if (am_flav & ia32_O) {
658 int offs = get_ia32_am_offs_int(n);
661 /* omit explicit + if there was no base or index */
663 obstack_printf(obst, "[%d", offs);
665 obstack_printf(obst, "%+d", offs);
673 obstack_printf(obst, "] ");
675 obstack_1grow(obst, '\0');
676 s = obstack_finish(obst);
684 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
686 static char buf[SNPRINTF_BUF_LEN];
687 ir_mode *mode = get_ia32_ls_mode(irn);
688 const char *adr = get_ia32_cnst(irn);
689 const char *pref = pointer_size(mode, ia32_has_x87_register(irn));
691 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
696 * Formated print of commands and comments.
698 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
700 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
703 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
705 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
711 * Add a number to a prefix. This number will not be used a second time.
713 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
714 static unsigned long id = 0;
715 snprintf(buf, buflen, "%s%lu", prefix, ++id);
721 /*************************************************
724 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
725 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
726 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
727 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
729 *************************************************/
732 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
735 * coding of conditions
737 struct cmp2conditon_t {
743 * positive conditions for signed compares
745 static const struct cmp2conditon_t cmp2condition_s[] = {
746 { NULL, pn_Cmp_False }, /* always false */
747 { "e", pn_Cmp_Eq }, /* == */
748 { "l", pn_Cmp_Lt }, /* < */
749 { "le", pn_Cmp_Le }, /* <= */
750 { "g", pn_Cmp_Gt }, /* > */
751 { "ge", pn_Cmp_Ge }, /* >= */
752 { "ne", pn_Cmp_Lg }, /* != */
753 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
754 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
755 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
756 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
757 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
758 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
759 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
760 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
761 { NULL, pn_Cmp_True }, /* always true */
765 * positive conditions for unsigned compares
767 static const struct cmp2conditon_t cmp2condition_u[] = {
768 { NULL, pn_Cmp_False }, /* always false */
769 { "e", pn_Cmp_Eq }, /* == */
770 { "b", pn_Cmp_Lt }, /* < */
771 { "be", pn_Cmp_Le }, /* <= */
772 { "a", pn_Cmp_Gt }, /* > */
773 { "ae", pn_Cmp_Ge }, /* >= */
774 { "ne", pn_Cmp_Lg }, /* != */
775 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
776 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
777 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
778 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
779 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
780 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
781 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
782 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
783 { NULL, pn_Cmp_True }, /* always true */
787 * returns the condition code
789 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
791 assert(cmp2condition_s[cmp_code].num == cmp_code);
792 assert(cmp2condition_u[cmp_code].num == cmp_code);
794 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
798 * Returns the target block for a control flow node.
800 static ir_node *get_cfop_target_block(const ir_node *irn) {
801 return get_irn_link(irn);
805 * Returns the target label for a control flow node.
807 static char *get_cfop_target(const ir_node *irn, char *buf) {
808 ir_node *bl = get_cfop_target_block(irn);
810 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
814 /** Return the next block in Block schedule */
815 static ir_node *next_blk_sched(const ir_node *block) {
816 return get_irn_link(block);
820 * Returns the Proj with projection number proj and NOT mode_M
822 static ir_node *get_proj(const ir_node *irn, long proj) {
823 const ir_edge_t *edge;
826 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
828 foreach_out_edge(irn, edge) {
829 src = get_edge_src_irn(edge);
831 assert(is_Proj(src) && "Proj expected");
832 if (get_irn_mode(src) == mode_M)
835 if (get_Proj_proj(src) == proj)
842 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
844 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
845 const ir_node *proj_true;
846 const ir_node *proj_false;
847 const ir_node *block;
848 const ir_node *next_block;
849 char buf[SNPRINTF_BUF_LEN];
850 char cmd_buf[SNPRINTF_BUF_LEN];
851 char cmnt_buf[SNPRINTF_BUF_LEN];
856 /* get both Proj's */
857 proj_true = get_proj(irn, pn_Cond_true);
858 assert(proj_true && "CondJmp without true Proj");
860 proj_false = get_proj(irn, pn_Cond_false);
861 assert(proj_false && "CondJmp without false Proj");
863 pnc = get_ia32_pncode(irn);
865 /* for now, the code works for scheduled and non-schedules blocks */
866 block = get_nodes_block(irn);
868 /* we have a block schedule */
869 next_block = next_blk_sched(block);
871 if (get_cfop_target_block(proj_true) == next_block) {
872 /* exchange both proj's so the second one can be omitted */
873 const ir_node *t = proj_true;
874 proj_true = proj_false;
878 pnc = get_negated_pnc(pnc, mode);
881 /* the first Proj must always be created */
882 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
883 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
884 get_cmp_suffix(pnc, is_unsigned),
885 get_cfop_target(proj_true, buf));
886 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
887 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
890 /* the second Proj might be a fallthrough */
891 if (get_cfop_target_block(proj_false) != next_block) {
892 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
893 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
897 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
903 * Emits code for conditional jump.
905 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
907 char cmd_buf[SNPRINTF_BUF_LEN];
908 char cmnt_buf[SNPRINTF_BUF_LEN];
910 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
911 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
913 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
917 * Emits code for conditional jump with two variables.
919 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
920 CondJmp_emitter(irn, env);
924 * Emits code for conditional test and jump.
926 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
928 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
931 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
932 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
933 char cmd_buf[SNPRINTF_BUF_LEN];
934 char cmnt_buf[SNPRINTF_BUF_LEN];
937 op2 = arch_register_get_name(get_in_reg(irn, 1));
939 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
940 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
943 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
949 * Emits code for conditional test and jump with two variables.
951 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
952 TestJmp_emitter(irn, env);
955 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
957 char cmd_buf[SNPRINTF_BUF_LEN];
958 char cmnt_buf[SNPRINTF_BUF_LEN];
960 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
961 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
963 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
966 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
968 char cmd_buf[SNPRINTF_BUF_LEN];
969 char cmnt_buf[SNPRINTF_BUF_LEN];
971 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
972 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
974 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
978 * Emits code for conditional SSE floating point jump with two variables.
980 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
982 char cmd_buf[SNPRINTF_BUF_LEN];
983 char cmnt_buf[SNPRINTF_BUF_LEN];
985 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
986 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
988 finish_CondJmp(F, irn, mode_F);
993 * Emits code for conditional x87 floating point jump with two variables.
995 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
997 char cmd_buf[SNPRINTF_BUF_LEN];
998 char cmnt_buf[SNPRINTF_BUF_LEN];
999 ia32_attr_t *attr = get_ia32_attr(irn);
1000 const char *reg = attr->x87[1]->name;
1001 const char *instr = "fcom";
1004 switch (get_ia32_irn_opcode(irn)) {
1005 case iro_ia32_fcomrJmp:
1007 case iro_ia32_fcomJmp:
1011 case iro_ia32_fcomrpJmp:
1013 case iro_ia32_fcompJmp:
1016 case iro_ia32_fcomrppJmp:
1018 case iro_ia32_fcomppJmp:
1025 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1027 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1028 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1030 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1031 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1033 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1034 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1037 /* the compare flags must be evaluated using carry , ie unsigned */
1038 finish_CondJmp(F, irn, mode_Iu);
1041 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1043 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1044 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1045 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1046 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1047 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1048 int idx_left = 2 - is_PsiCondCMov;
1049 int idx_right = 3 - is_PsiCondCMov;
1051 char cmd_buf[SNPRINTF_BUF_LEN];
1052 char cmnt_buf[SNPRINTF_BUF_LEN];
1053 const arch_register_t *in1, *in2, *out;
1055 out = arch_get_irn_register(env->arch_env, irn);
1056 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1057 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1059 /* we have to emit the cmp first, because the destination register */
1060 /* could be one of the compare registers */
1061 if (is_ia32_CmpCMov(irn)) {
1062 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1064 else if (is_ia32_xCmpCMov(irn)) {
1065 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1067 else if (is_PsiCondCMov) {
1068 /* omit compare because flags are already set by And/Or */
1069 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1072 assert(0 && "unsupported CMov");
1074 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1077 if (REGS_ARE_EQUAL(out, in2)) {
1078 /* best case: default in == out -> do nothing */
1080 else if (REGS_ARE_EQUAL(out, in1)) {
1081 /* true in == out -> need complement compare and exchange true and default in */
1082 ir_node *t = get_irn_n(irn, idx_left);
1083 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1084 set_irn_n(irn, idx_right, t);
1086 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1090 /* out is different from in: need copy default -> out */
1092 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1094 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1096 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1101 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1103 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1105 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1109 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1110 CMov_emitter(irn, env);
1113 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1114 CMov_emitter(irn, env);
1117 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1118 CMov_emitter(irn, env);
1121 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1123 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1124 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1125 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1126 const char *reg8bit;
1128 char cmd_buf[SNPRINTF_BUF_LEN];
1129 char cmnt_buf[SNPRINTF_BUF_LEN];
1130 const arch_register_t *out;
1132 out = arch_get_irn_register(env->arch_env, irn);
1133 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1135 if (is_ia32_CmpSet(irn)) {
1136 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1138 else if (is_ia32_xCmpSet(irn)) {
1139 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1141 else if (is_ia32_PsiCondSet(irn)) {
1142 /* omit compare because flags are already set by And/Or */
1143 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1146 assert(0 && "unsupported Set");
1148 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1151 /* use mov to clear target because it doesn't affect the eflags */
1152 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1153 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1156 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1157 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1161 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1162 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1165 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1166 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1169 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1170 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1173 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1175 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1177 long pnc = get_ia32_pncode(irn);
1178 long unord = pnc & pn_Cmp_Uo;
1179 char cmd_buf[SNPRINTF_BUF_LEN];
1180 char cmnt_buf[SNPRINTF_BUF_LEN];
1183 case pn_Cmp_Leg: /* odered */
1186 case pn_Cmp_Uo: /* unordered */
1190 case pn_Cmp_Eq: /* == */
1194 case pn_Cmp_Lt: /* < */
1198 case pn_Cmp_Le: /* <= */
1202 case pn_Cmp_Gt: /* > */
1206 case pn_Cmp_Ge: /* >= */
1210 case pn_Cmp_Lg: /* != */
1215 assert(sse_pnc >= 0 && "unsupported compare");
1217 if (unord && sse_pnc != 3) {
1219 We need a separate compare against unordered.
1220 Quick and Dirty solution:
1221 - get some memory on stack
1225 - and result and stored result
1228 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1229 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1231 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1232 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1234 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1235 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1239 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1240 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1243 if (unord && sse_pnc != 3) {
1244 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1245 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1247 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1248 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1253 /*********************************************************
1256 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1257 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1258 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1259 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1262 *********************************************************/
1264 /* jump table entry (target and corresponding number) */
1265 typedef struct _branch_t {
1270 /* jump table for switch generation */
1271 typedef struct _jmp_tbl_t {
1272 ir_node *defProj; /**< default target */
1273 int min_value; /**< smallest switch case */
1274 int max_value; /**< largest switch case */
1275 int num_branches; /**< number of jumps */
1276 char *label; /**< label of the jump table */
1277 branch_t *branches; /**< jump array */
1281 * Compare two variables of type branch_t. Used to sort all switch cases
1283 static int ia32_cmp_branch_t(const void *a, const void *b) {
1284 branch_t *b1 = (branch_t *)a;
1285 branch_t *b2 = (branch_t *)b;
1287 if (b1->value <= b2->value)
1294 * Emits code for a SwitchJmp (creates a jump table if
1295 * possible otherwise a cmp-jmp cascade). Port from
1298 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1299 unsigned long interval;
1300 char buf[SNPRINTF_BUF_LEN];
1301 int last_value, i, pn;
1304 const ir_edge_t *edge;
1305 const lc_arg_env_t *env = ia32_get_arg_env();
1306 FILE *F = emit_env->out;
1307 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1309 /* fill the table structure */
1310 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1311 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1313 tbl.num_branches = get_irn_n_edges(irn);
1314 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1315 tbl.min_value = INT_MAX;
1316 tbl.max_value = INT_MIN;
1319 /* go over all proj's and collect them */
1320 foreach_out_edge(irn, edge) {
1321 proj = get_edge_src_irn(edge);
1322 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1324 pn = get_Proj_proj(proj);
1326 /* create branch entry */
1327 tbl.branches[i].target = proj;
1328 tbl.branches[i].value = pn;
1330 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1331 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1333 /* check for default proj */
1334 if (pn == get_ia32_pncode(irn)) {
1335 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1342 /* sort the branches by their number */
1343 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1345 /* two-complement's magic make this work without overflow */
1346 interval = tbl.max_value - tbl.min_value;
1348 /* emit the table */
1349 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1350 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1353 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1354 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1357 if (tbl.num_branches > 1) {
1360 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1361 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1364 ia32_switch_section(F, SECTION_RODATA);
1365 fprintf(F, "\t.align 4\n");
1367 fprintf(F, "%s:\n", tbl.label);
1369 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1370 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1373 last_value = tbl.branches[0].value;
1374 for (i = 1; i < tbl.num_branches; ++i) {
1375 while (++last_value < tbl.branches[i].value) {
1376 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1377 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1380 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1381 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1384 ia32_switch_section(F, SECTION_TEXT);
1387 /* one jump is enough */
1388 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1389 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1400 * Emits code for a unconditional jump.
1402 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1403 ir_node *block, *next_bl;
1405 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1407 /* for now, the code works for scheduled and non-schedules blocks */
1408 block = get_nodes_block(irn);
1410 /* we have a block schedule */
1411 next_bl = next_blk_sched(block);
1412 if (get_cfop_target_block(irn) != next_bl) {
1413 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1414 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1418 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1423 /****************************
1426 * _ __ _ __ ___ _ ___
1427 * | '_ \| '__/ _ \| |/ __|
1428 * | |_) | | | (_) | |\__ \
1429 * | .__/|_| \___/| ||___/
1432 ****************************/
1435 * Emits code for a proj -> node
1437 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1438 ir_node *pred = get_Proj_pred(irn);
1440 if (get_irn_op(pred) == op_Start) {
1441 switch(get_Proj_proj(irn)) {
1442 case pn_Start_X_initial_exec:
1451 /**********************************
1454 * | | ___ _ __ _ _| |_) |
1455 * | | / _ \| '_ \| | | | _ <
1456 * | |___| (_) | |_) | |_| | |_) |
1457 * \_____\___/| .__/ \__, |____/
1460 **********************************/
1463 * Emit movsb/w instructions to make mov count divideable by 4
1465 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1466 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1468 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1470 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1471 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1476 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1477 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1481 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1482 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1486 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1487 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1489 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1490 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1498 * Emit rep movsd instruction for memcopy.
1500 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1501 FILE *F = emit_env->out;
1502 tarval *tv = get_ia32_Immop_tarval(irn);
1503 int rem = get_tarval_long(tv);
1504 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1506 emit_CopyB_prolog(F, irn, rem);
1508 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1509 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1514 * Emits unrolled memcopy.
1516 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1517 tarval *tv = get_ia32_Immop_tarval(irn);
1518 int size = get_tarval_long(tv);
1519 FILE *F = emit_env->out;
1520 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1522 emit_CopyB_prolog(F, irn, size & 0x3);
1526 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1527 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1534 /***************************
1538 * | | / _ \| '_ \ \ / /
1539 * | |___| (_) | | | \ V /
1540 * \_____\___/|_| |_|\_/
1542 ***************************/
1545 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1547 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1548 FILE *F = emit_env->out;
1549 const lc_arg_env_t *env = ia32_get_arg_env();
1550 ir_mode *src_mode = get_ia32_src_mode(irn);
1551 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1552 char *from, *to, buf[64];
1553 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1555 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1556 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1558 switch(get_ia32_op_type(irn)) {
1560 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1562 case ia32_AddrModeS:
1563 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1566 assert(0 && "unsupported op type for Conv");
1569 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1570 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1574 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1575 emit_ia32_Conv_with_FP(irn, emit_env);
1578 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1579 emit_ia32_Conv_with_FP(irn, emit_env);
1582 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1583 emit_ia32_Conv_with_FP(irn, emit_env);
1587 * Emits code for an Int conversion.
1589 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1590 FILE *F = emit_env->out;
1591 const lc_arg_env_t *env = ia32_get_arg_env();
1592 char *move_cmd = "movzx";
1593 char *conv_cmd = NULL;
1594 ir_mode *src_mode = get_ia32_src_mode(irn);
1595 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1598 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1599 const arch_register_t *in_reg, *out_reg;
1601 n = get_mode_size_bits(src_mode);
1602 m = get_mode_size_bits(tgt_mode);
1604 assert(n == 8 || n == 16 || n == 32);
1605 assert(m == 8 || m == 16 || m == 32);
1608 signed_mode = mode_is_signed(n < m ? src_mode : tgt_mode);
1613 switch(get_ia32_op_type(irn)) {
1615 in_reg = get_in_reg(irn, 2);
1616 out_reg = get_out_reg(irn, 0);
1618 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1619 REGS_ARE_EQUAL(out_reg, in_reg) &&
1622 if (n == 8 || m == 8)
1624 else if (n == 16 || m == 16)
1627 /* argument and result are both in EAX and */
1628 /* signedness is ok: -> use converts */
1629 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1631 else if (REGS_ARE_EQUAL(out_reg, in_reg) && ! signed_mode)
1633 /* argument and result are in the same register */
1634 /* and signedness is ok: -> use and with mask */
1635 int mask = (1 << (n < m ? n : m)) - 1;
1636 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1639 /* use move w/o sign extension */
1640 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1641 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1645 case ia32_AddrModeS:
1646 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1647 move_cmd, irn, ia32_emit_am(irn, emit_env));
1650 assert(0 && "unsupported op type for Conv");
1653 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1654 irn, n, src_mode, m, tgt_mode);
1660 * Emits code for an 8Bit Int conversion.
1662 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1663 emit_ia32_Conv_I2I(irn, emit_env);
1667 /*******************************************
1670 * | |__ ___ _ __ ___ __| | ___ ___
1671 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1672 * | |_) | __/ | | | (_) | (_| | __/\__ \
1673 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1675 *******************************************/
1678 * Emits a backend call
1680 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1681 FILE *F = emit_env->out;
1682 entity *ent = be_Call_get_entity(irn);
1683 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1686 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1689 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1692 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1698 * Emits code to increase stack pointer.
1700 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1701 FILE *F = emit_env->out;
1702 int offs = be_get_IncSP_offset(irn);
1703 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1707 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1709 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1710 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1713 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1714 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1721 * Emits code to set stack pointer.
1723 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1724 FILE *F = emit_env->out;
1725 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1727 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1728 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1733 * Emits code for Copy/CopyKeep.
1735 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1736 FILE *F = emit_env->out;
1737 const arch_env_t *aenv = emit_env->arch_env;
1738 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1740 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1741 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1744 if (mode_is_float(get_irn_mode(irn)))
1745 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1747 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1748 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1752 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1753 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1756 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1757 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1761 * Emits code for exchange.
1763 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1764 FILE *F = emit_env->out;
1765 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1766 const arch_register_t *in1, *in2;
1767 const arch_register_class_t *cls1, *cls2;
1769 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1770 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1772 cls1 = arch_register_get_class(in1);
1773 cls2 = arch_register_get_class(in2);
1775 assert(cls1 == cls2 && "Register class mismatch at Perm");
1777 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1778 if(emit_env->isa->opt_arch == arch_athlon) {
1779 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1780 // it is nearly always beneficial to use the 3 xor trick instead of an xchg
1782 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1784 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1786 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1788 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1791 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1792 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1793 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1795 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1799 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1804 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1809 * Emits code for Constant loading.
1811 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1813 char cmd_buf[256], cmnt_buf[256];
1814 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1815 ir_mode *mode = get_irn_mode(n);
1816 tarval *tv = get_ia32_Immop_tarval(n);
1818 if (get_ia32_op_type(n) == ia32_SymConst) {
1819 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1820 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1822 assert(mode == get_tarval_mode(tv));
1823 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1824 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1825 const char *instr = "xor";
1826 if (env->isa->opt_arch == arch_pentium_4) {
1827 /* P4 prefers sub r, r, others xor r, r */
1830 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1831 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1833 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1834 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1837 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1841 * Emits code to increase stack pointer.
1843 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1844 FILE *F = emit_env->out;
1845 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1847 if (is_ia32_ImmConst(irn)) {
1848 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1850 else if (is_ia32_ImmSymConst(irn)) {
1851 if (get_ia32_op_type(irn) == ia32_Normal)
1852 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1853 else /* source address mode */
1854 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1857 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1859 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1865 * Emits code to increase stack pointer.
1867 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1868 FILE *F = emit_env->out;
1869 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1871 if (is_ia32_ImmConst(irn)) {
1872 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1874 else if (is_ia32_ImmSymConst(irn)) {
1875 if (get_ia32_op_type(irn) == ia32_Normal)
1876 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1877 else /* source address mode */
1878 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1881 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1883 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1889 * Emits code to load the TLS base
1891 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1892 FILE *F = emit_env->out;
1893 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1895 switch (asm_flavour) {
1897 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1900 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1903 assert(0 && "unsupported TLS");
1906 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1911 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1913 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1915 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1918 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1921 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1925 /***********************************************************************************
1928 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1929 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1930 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1931 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1933 ***********************************************************************************/
1936 * Enters the emitter functions for handled nodes into the generic
1937 * pointer of an opcode.
1939 static void ia32_register_emitters(void) {
1941 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1942 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1943 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1944 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1945 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1946 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1948 /* first clear the generic function pointer for all ops */
1949 clear_irp_opcodes_generic_func();
1951 /* register all emitter functions defined in spec */
1952 ia32_register_spec_emitters();
1954 /* other ia32 emitter functions */
1960 IA32_EMIT(PsiCondCMov);
1962 IA32_EMIT(PsiCondSet);
1963 IA32_EMIT(SwitchJmp);
1966 IA32_EMIT(Conv_I2FP);
1967 IA32_EMIT(Conv_FP2I);
1968 IA32_EMIT(Conv_FP2FP);
1969 IA32_EMIT(Conv_I2I);
1970 IA32_EMIT(Conv_I2I8Bit);
1977 IA32_EMIT(xCmpCMov);
1978 IA32_EMIT(xCondJmp);
1979 IA32_EMIT2(fcomJmp, x87CondJmp);
1980 IA32_EMIT2(fcompJmp, x87CondJmp);
1981 IA32_EMIT2(fcomppJmp, x87CondJmp);
1982 IA32_EMIT2(fcomrJmp, x87CondJmp);
1983 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1984 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1986 /* benode emitter */
2012 static const char *last_name = NULL;
2013 static unsigned last_line = -1;
2014 static unsigned num = -1;
2017 * Emit the debug support for node irn.
2019 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2020 dbg_info *db = get_irn_dbg_info(irn);
2022 const char *fname = be_retrieve_dbg_info(db, &lineno);
2025 if (last_name != fname) {
2027 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2030 if (last_line != lineno) {
2034 snprintf(name, sizeof(name), ".LM%u", ++num);
2036 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2037 fprintf(F, "%s:\n", name);
2043 * Emits code for a node.
2045 static void ia32_emit_node(const ir_node *irn, void *env) {
2046 ia32_emit_env_t *emit_env = env;
2047 ir_op *op = get_irn_op(irn);
2048 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2050 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2052 if (op->ops.generic) {
2053 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2054 ia32_emit_dbg(irn, emit_env);
2058 emit_Nothing(irn, env);
2059 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2064 * Emits gas alignment directives
2066 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2067 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2071 * Emits gas alignment directives for Functions depended on cpu architecture.
2073 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2075 unsigned maximum_skip;
2090 maximum_skip = (1 << align) - 1;
2091 ia32_emit_alignment(F, align, maximum_skip);
2095 * Emits gas alignment directives for Labels depended on cpu architecture.
2097 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2098 unsigned align; unsigned maximum_skip;
2113 maximum_skip = (1 << align) - 1;
2114 ia32_emit_alignment(F, align, maximum_skip);
2117 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2118 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2119 double block_freq, prev_freq;
2120 static const double DELTA = .0001;
2121 cpu_support cpu = env->isa->opt_arch;
2123 if(execfreqs == NULL)
2125 if(cpu == arch_i386 || cpu == arch_i486)
2128 block_freq = get_block_execfreq(execfreqs, block);
2129 prev_freq = get_block_execfreq(execfreqs, prev_block);
2131 if(block_freq < DELTA || prev_freq < DELTA)
2134 block_freq /= prev_freq;
2138 case arch_athlon_64:
2140 return block_freq > 3;
2145 return block_freq > 2;
2149 * Walks over the nodes in a block connected by scheduling edges
2150 * and emits code for each node.
2152 static void ia32_gen_block(ir_node *block, ir_node *last_block, ia32_emit_env_t *env) {
2153 ir_graph *irg = get_irn_irg(block);
2154 ir_node *start_block = get_irg_start_block(irg);
2159 assert(is_Block(block));
2161 if(block == start_block)
2164 if (need_label && get_irn_arity(block) == 1) {
2165 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2167 if(pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2171 // special case because the start block contains no jump instruction
2172 if(last_block == start_block) {
2173 const ir_edge_t *edge;
2174 ir_node *startsucc = NULL;
2176 foreach_block_succ(start_block, edge) {
2177 startsucc = get_edge_src_irn(edge);
2178 if(startsucc != start_block)
2181 assert(startsucc != NULL);
2183 if(startsucc != block) {
2184 char buf[SNPRINTF_BUF_LEN];
2185 ir_snprintf(buf, sizeof(buf), BLOCK_PREFIX("%d"),
2186 get_irn_node_nr(startsucc));
2187 ir_fprintf(F, "\tjmp %s\n", buf);
2192 char cmd_buf[SNPRINTF_BUF_LEN];
2195 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2197 // align the loop headers
2198 if(!is_first_loop_block(block, last_block, env)) {
2200 // align blocks where the previous block has no fallthrough
2201 arity = get_irn_arity(block);
2202 for(i = 0; i < arity; ++i) {
2203 ir_node *predblock = get_Block_cfgpred_block(block, i);
2204 if(predblock == last_block) {
2212 ia32_emit_align_label(env->out, env->isa->opt_arch);
2214 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2215 get_irn_node_nr(block));
2216 fprintf(F, "%-43s ", cmd_buf);
2218 /* emit list of pred blocks in comment */
2219 fprintf(F, "/* preds:");
2221 arity = get_irn_arity(block);
2222 for(i = 0; i < arity; ++i) {
2223 ir_node *predblock = get_Block_cfgpred_block(block, i);
2224 fprintf(F, " %ld", get_irn_node_nr(predblock));
2226 if(execfreqs != NULL) {
2227 fprintf(F, " freq: %f", get_block_execfreq(execfreqs, block));
2230 fprintf(F, " */\n");
2233 /* emit the contents of the block */
2234 ia32_emit_dbg(block, env);
2235 sched_foreach(block, irn) {
2236 ia32_emit_node(irn, env);
2241 * Emits code for function start.
2243 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2244 entity *irg_ent = get_irg_entity(irg);
2245 const char *irg_name = get_entity_ld_name(irg_ent);
2246 cpu_support cpu = emit_env->isa->opt_arch;
2247 const be_irg_t *birg = emit_env->cg->birg;
2250 ia32_switch_section(F, SECTION_TEXT);
2251 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2252 ia32_emit_align_func(F, cpu);
2253 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2254 fprintf(F, ".globl %s\n", irg_name);
2256 ia32_dump_function_object(F, irg_name);
2257 fprintf(F, "%s:\n", irg_name);
2261 * Emits code for function end
2263 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2264 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2265 const be_irg_t *birg = emit_env->cg->birg;
2267 ia32_dump_function_size(F, irg_name);
2268 be_dbg_method_end(birg->main_env->db_handle);
2274 * Sets labels for control flow nodes (jump target)
2275 * TODO: Jump optimization
2277 static void ia32_gen_labels(ir_node *block, void *env) {
2279 int n = get_Block_n_cfgpreds(block);
2281 for (n--; n >= 0; n--) {
2282 pred = get_Block_cfgpred(block, n);
2283 set_irn_link(pred, block);
2288 * Main driver. Emits the code for one routine.
2290 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2291 ia32_emit_env_t emit_env;
2293 ir_node *last_block = NULL;
2296 emit_env.arch_env = cg->arch_env;
2298 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2299 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2301 /* set the global arch_env (needed by print hooks) */
2302 arch_env = cg->arch_env;
2304 ia32_register_emitters();
2306 ia32_emit_func_prolog(F, irg, &emit_env);
2307 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2309 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2310 int i, n = ARR_LEN(cg->blk_sched);
2312 for (i = 0; i < n;) {
2315 block = cg->blk_sched[i];
2317 next_bl = i < n ? cg->blk_sched[i] : NULL;
2319 /* set here the link. the emitter expects to find the next block here */
2320 set_irn_link(block, next_bl);
2321 ia32_gen_block(block, last_block, &emit_env);
2326 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2327 in the block schedule. As this number should NEVER be equal the next block,
2328 we does not need a clear block link here. */
2330 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2334 ia32_emit_func_epilog(F, irg, &emit_env);