2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
131 /* We always pass the ir_node which is a pointer. */
132 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
133 return lc_arg_type_ptr;
138 * Returns the register at in position pos.
140 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
142 const arch_register_t *reg = NULL;
144 assert(get_irn_arity(irn) > pos && "Invalid IN position");
146 /* The out register of the operator at position pos is the
147 in register we need. */
148 op = get_irn_n(irn, pos);
150 reg = arch_get_irn_register(arch_env, op);
152 assert(reg && "no in register found");
154 /* in case of a joker register: just return a valid register */
155 if (arch_register_type_is(reg, joker)) {
156 arch_register_req_t req;
157 const arch_register_req_t *p_req;
159 /* ask for the requirements */
160 p_req = arch_get_register_req(arch_env, &req, irn, pos);
162 if (arch_register_req_is(p_req, limited)) {
163 /* in case of limited requirements: get the first allowed register */
165 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
168 p_req->limited(p_req->limited_env, bs);
169 idx = bitset_next_set(bs, 0);
170 reg = arch_register_for_index(p_req->cls, idx);
173 /* otherwise get first register in class */
174 reg = arch_register_for_index(p_req->cls, 0);
182 * Returns the register at out position pos.
184 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
186 const arch_register_t *reg = NULL;
188 /* 1st case: irn is not of mode_T, so it has only */
189 /* one OUT register -> good */
190 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
191 /* Proj with the corresponding projnum for the register */
193 if (get_irn_mode(irn) != mode_T) {
194 reg = arch_get_irn_register(arch_env, irn);
196 else if (is_ia32_irn(irn)) {
197 reg = get_ia32_out_reg(irn, pos);
200 const ir_edge_t *edge;
202 foreach_out_edge(irn, edge) {
203 proj = get_edge_src_irn(edge);
204 assert(is_Proj(proj) && "non-Proj from mode_T node");
205 if (get_Proj_proj(proj) == pos) {
206 reg = arch_get_irn_register(arch_env, proj);
212 assert(reg && "no out register found");
222 * Returns the name of the in register at position pos.
224 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
225 const arch_register_t *reg;
227 if (in_out == IN_REG) {
228 reg = get_in_reg(irn, pos);
230 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
231 /* FIXME: works for binop only */
232 assert(2 <= pos && pos <= 3);
233 reg = get_ia32_attr(irn)->x87[pos - 2];
237 /* destination address mode nodes don't have outputs */
238 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
242 reg = get_out_reg(irn, pos);
243 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
244 reg = get_ia32_attr(irn)->x87[pos + 2];
246 return arch_register_get_name(reg);
250 * Get the register name for a node.
252 static int ia32_get_reg_name(lc_appendable_t *app,
253 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
256 ir_node *irn = arg->v_ptr;
257 int nr = occ->width - 1;
260 return lc_appendable_snadd(app, "(null)", 6);
262 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
264 /* append the stupid % to register names */
265 lc_appendable_chadd(app, '%');
266 return lc_appendable_snadd(app, buf, strlen(buf));
270 * Get the x87 register name for a node.
272 static int ia32_get_x87_name(lc_appendable_t *app,
273 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
276 ir_node *irn = arg->v_ptr;
277 int nr = occ->width - 1;
282 return lc_appendable_snadd(app, "(null)", 6);
284 attr = get_ia32_attr(irn);
285 buf = attr->x87[nr]->name;
287 res += lc_appendable_chadd(app, '%');
288 res += lc_appendable_snadd(app, buf, strlen(buf));
294 * Returns the tarval, offset or scale of an ia32 as a string.
296 static int ia32_const_to_str(lc_appendable_t *app,
297 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
300 ir_node *irn = arg->v_ptr;
303 return lc_arg_append(app, occ, "(null)", 6);
305 if (occ->conversion == 'C') {
306 buf = get_ia32_cnst(irn);
309 buf = get_ia32_am_offs(irn);
312 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
316 * Determines the SSE suffix depending on the mode.
318 static int ia32_get_mode_suffix(lc_appendable_t *app,
319 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
321 ir_node *irn = arg->v_ptr;
322 ir_mode *mode = get_irn_mode(irn);
324 if (mode == mode_T) {
325 mode = get_ia32_res_mode(irn);
327 mode = get_ia32_ls_mode(irn);
331 return lc_arg_append(app, occ, "(null)", 6);
333 if (mode_is_float(mode)) {
334 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
337 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
342 * Return the ia32 printf arg environment.
343 * We use the firm environment with some additional handlers.
345 const lc_arg_env_t *ia32_get_arg_env(void) {
346 static lc_arg_env_t *env = NULL;
348 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
349 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
350 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
351 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
354 /* extend the firm printer */
355 env = firm_get_arg_env();
357 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
358 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
359 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
360 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
361 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
362 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
368 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
369 switch(get_mode_size_bits(mode)) {
371 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
373 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
375 return (char *)arch_register_get_name(reg);
380 * Emits registers and/or address mode of a binary operation.
382 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
383 static char *buf = NULL;
385 /* verify that this function is never called on non-AM supporting operations */
386 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
388 #define PRODUCES_RESULT(n) \
389 (!(is_ia32_St(n) || \
390 is_ia32_Store8Bit(n) || \
391 is_ia32_CondJmp(n) || \
392 is_ia32_xCondJmp(n) || \
393 is_ia32_CmpSet(n) || \
394 is_ia32_xCmpSet(n) || \
395 is_ia32_SwitchJmp(n)))
398 buf = xcalloc(1, SNPRINTF_BUF_LEN);
401 memset(buf, 0, SNPRINTF_BUF_LEN);
404 switch(get_ia32_op_type(n)) {
406 if (is_ia32_ImmConst(n)) {
407 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
409 else if (is_ia32_ImmSymConst(n)) {
410 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
413 const arch_register_t *in1 = get_in_reg(n, 2);
414 const arch_register_t *in2 = get_in_reg(n, 3);
415 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
416 const arch_register_t *in;
419 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
420 out = out ? out : in1;
421 in_name = arch_register_get_name(in);
423 if (is_ia32_emit_cl(n)) {
424 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
428 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
432 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
433 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
434 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
437 if (PRODUCES_RESULT(n)) {
438 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
441 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
446 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
447 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
448 ia32_emit_am(n, env),
449 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
450 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
453 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
454 ir_mode *mode = get_ia32_res_mode(n);
457 mode = mode ? mode : get_ia32_ls_mode(n);
458 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
460 if (is_ia32_emit_cl(n)) {
461 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
465 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
469 assert(0 && "unsupported op type");
472 #undef PRODUCES_RESULT
478 * Returns the xxx PTR string for a given mode
480 * @param mode the mode
481 * @param x87_insn if non-zero returns the string for a x87 instruction
482 * else for a SSE instruction
484 static const char *pointer_size(ir_mode *mode, int x87_insn)
487 switch (get_mode_size_bits(mode)) {
488 case 8: return "BYTE PTR";
489 case 16: return "WORD PTR";
490 case 32: return "DWORD PTR";
496 case 96: return "XWORD PTR";
497 default: return NULL;
504 * Emits registers and/or address mode of a binary operation.
506 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
507 static char *buf = NULL;
509 /* verify that this function is never called on non-AM supporting operations */
510 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
513 buf = xcalloc(1, SNPRINTF_BUF_LEN);
516 memset(buf, 0, SNPRINTF_BUF_LEN);
519 switch(get_ia32_op_type(n)) {
521 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
522 ir_mode *mode = get_ia32_ls_mode(n);
523 const char *p = pointer_size(mode, 1);
524 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
527 ia32_attr_t *attr = get_ia32_attr(n);
528 const arch_register_t *in1 = attr->x87[0];
529 const arch_register_t *in2 = attr->x87[1];
530 const arch_register_t *out = attr->x87[2];
531 const arch_register_t *in;
533 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
534 out = out ? out : in1;
536 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s",
537 arch_register_get_name(out), arch_register_get_name(in));
542 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
545 assert(0 && "unsupported op type");
552 * Emits registers and/or address mode of a unary operation.
554 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
555 static char *buf = NULL;
558 buf = xcalloc(1, SNPRINTF_BUF_LEN);
561 memset(buf, 0, SNPRINTF_BUF_LEN);
564 switch(get_ia32_op_type(n)) {
566 if (is_ia32_ImmConst(n)) {
567 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
569 else if (is_ia32_ImmSymConst(n)) {
570 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
573 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
574 /* MulS and Mulh implicitly multiply by EAX */
575 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
576 } else if(is_ia32_Push(n)) {
577 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
579 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
584 assert(!is_ia32_Push(n));
585 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
589 Mulh is emitted via emit_unop
590 imul [MEM] means EDX:EAX <- EAX * [MEM]
592 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
593 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
596 assert(0 && "unsupported op type");
603 * Emits address mode.
605 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
606 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
610 static struct obstack *obst = NULL;
611 ir_mode *mode = get_ia32_ls_mode(n);
613 /* just to be sure... */
614 assert(!is_ia32_use_frame(n) || get_ia32_frame_ent(n) != NULL);
616 if (! is_ia32_Lea(n))
617 assert(mode && "AM node must have ls_mode attribute set.");
620 obst = xcalloc(1, sizeof(*obst));
623 obstack_free(obst, NULL);
626 /* obstack_free with NULL results in an uninitialized obstack */
629 p = pointer_size(mode, ia32_has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
631 obstack_printf(obst, "%s ", p);
633 /* emit address mode symconst */
634 if (get_ia32_am_sc(n)) {
635 if (is_ia32_am_sc_sign(n))
636 obstack_printf(obst, "-");
637 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
640 if (am_flav & ia32_B) {
641 obstack_printf(obst, "[");
642 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
646 if (am_flav & ia32_I) {
648 obstack_printf(obst, "+");
651 obstack_printf(obst, "[");
654 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
656 if (am_flav & ia32_S) {
657 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
663 if (am_flav & ia32_O) {
664 int offs = get_ia32_am_offs_int(n);
667 /* omit explicit + if there was no base or index */
669 obstack_printf(obst, "[%d", offs);
671 obstack_printf(obst, "%+d", offs);
679 obstack_printf(obst, "] ");
681 obstack_1grow(obst, '\0');
682 s = obstack_finish(obst);
690 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
692 static char buf[SNPRINTF_BUF_LEN];
693 ir_mode *mode = get_ia32_ls_mode(irn);
694 const char *adr = get_ia32_cnst(irn);
695 const char *pref = pointer_size(mode, ia32_has_x87_register(irn));
697 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
702 * Formated print of commands and comments.
704 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
706 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
709 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
711 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
717 * Add a number to a prefix. This number will not be used a second time.
719 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
720 static unsigned long id = 0;
721 snprintf(buf, buflen, "%s%lu", prefix, ++id);
727 /*************************************************
730 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
731 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
732 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
733 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
735 *************************************************/
738 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
741 * coding of conditions
743 struct cmp2conditon_t {
749 * positive conditions for signed compares
751 static const struct cmp2conditon_t cmp2condition_s[] = {
752 { NULL, pn_Cmp_False }, /* always false */
753 { "e", pn_Cmp_Eq }, /* == */
754 { "l", pn_Cmp_Lt }, /* < */
755 { "le", pn_Cmp_Le }, /* <= */
756 { "g", pn_Cmp_Gt }, /* > */
757 { "ge", pn_Cmp_Ge }, /* >= */
758 { "ne", pn_Cmp_Lg }, /* != */
759 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
760 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
761 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
762 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
763 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
764 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
765 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
766 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
767 { NULL, pn_Cmp_True }, /* always true */
771 * positive conditions for unsigned compares
773 static const struct cmp2conditon_t cmp2condition_u[] = {
774 { NULL, pn_Cmp_False }, /* always false */
775 { "e", pn_Cmp_Eq }, /* == */
776 { "b", pn_Cmp_Lt }, /* < */
777 { "be", pn_Cmp_Le }, /* <= */
778 { "a", pn_Cmp_Gt }, /* > */
779 { "ae", pn_Cmp_Ge }, /* >= */
780 { "ne", pn_Cmp_Lg }, /* != */
781 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
782 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
783 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
784 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
785 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
786 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
787 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
788 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
789 { NULL, pn_Cmp_True }, /* always true */
793 * returns the condition code
795 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
797 assert(cmp2condition_s[cmp_code].num == cmp_code);
798 assert(cmp2condition_u[cmp_code].num == cmp_code);
800 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
804 * Returns the target block for a control flow node.
806 static ir_node *get_cfop_target_block(const ir_node *irn) {
807 return get_irn_link(irn);
811 * Returns the target label for a control flow node.
813 static char *get_cfop_target(const ir_node *irn, char *buf) {
814 ir_node *bl = get_cfop_target_block(irn);
816 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
820 /** Return the next block in Block schedule */
821 static ir_node *next_blk_sched(const ir_node *block) {
822 return get_irn_link(block);
826 * Returns the Proj with projection number proj and NOT mode_M
828 static ir_node *get_proj(const ir_node *irn, long proj) {
829 const ir_edge_t *edge;
832 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
834 foreach_out_edge(irn, edge) {
835 src = get_edge_src_irn(edge);
837 assert(is_Proj(src) && "Proj expected");
838 if (get_irn_mode(src) == mode_M)
841 if (get_Proj_proj(src) == proj)
848 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
850 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
851 const ir_node *proj_true;
852 const ir_node *proj_false;
853 const ir_node *block;
854 const ir_node *next_block;
855 char buf[SNPRINTF_BUF_LEN];
856 char cmd_buf[SNPRINTF_BUF_LEN];
857 char cmnt_buf[SNPRINTF_BUF_LEN];
862 /* get both Proj's */
863 proj_true = get_proj(irn, pn_Cond_true);
864 assert(proj_true && "CondJmp without true Proj");
866 proj_false = get_proj(irn, pn_Cond_false);
867 assert(proj_false && "CondJmp without false Proj");
869 pnc = get_ia32_pncode(irn);
871 /* for now, the code works for scheduled and non-schedules blocks */
872 block = get_nodes_block(irn);
874 /* we have a block schedule */
875 next_block = next_blk_sched(block);
877 if (get_cfop_target_block(proj_true) == next_block) {
878 /* exchange both proj's so the second one can be omitted */
879 const ir_node *t = proj_true;
881 proj_true = proj_false;
884 pnc = get_negated_pnc(pnc, mode);
887 /* the first Proj must always be created */
888 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
890 /* in case of unordered compare, check for parity */
891 if (pnc & pn_Cmp_Uo) {
892 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jp %s", get_cfop_target(proj_true, buf));
893 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* jump to false if result is unordered */");
897 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
898 get_cmp_suffix(pnc, is_unsigned),
899 get_cfop_target(proj_true, buf));
900 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
901 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
904 /* the second Proj might be a fallthrough */
905 if (get_cfop_target_block(proj_false) != next_block) {
906 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
907 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
911 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
917 * Emits code for conditional jump.
919 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
921 char cmd_buf[SNPRINTF_BUF_LEN];
922 char cmnt_buf[SNPRINTF_BUF_LEN];
924 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
925 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
927 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
931 * Emits code for conditional jump with two variables.
933 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
934 CondJmp_emitter(irn, env);
938 * Emits code for conditional test and jump.
940 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
942 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
945 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
946 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
947 char cmd_buf[SNPRINTF_BUF_LEN];
948 char cmnt_buf[SNPRINTF_BUF_LEN];
951 op2 = arch_register_get_name(get_in_reg(irn, 1));
953 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
954 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
957 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
963 * Emits code for conditional test and jump with two variables.
965 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
966 TestJmp_emitter(irn, env);
969 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
971 char cmd_buf[SNPRINTF_BUF_LEN];
972 char cmnt_buf[SNPRINTF_BUF_LEN];
974 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
975 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
977 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
980 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
982 char cmd_buf[SNPRINTF_BUF_LEN];
983 char cmnt_buf[SNPRINTF_BUF_LEN];
985 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
986 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
988 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
992 * Emits code for conditional SSE floating point jump with two variables.
994 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
996 char cmd_buf[SNPRINTF_BUF_LEN];
997 char cmnt_buf[SNPRINTF_BUF_LEN];
998 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1000 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
1001 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1004 finish_CondJmp(F, irn, mode_F);
1008 * Emits code for conditional x87 floating point jump with two variables.
1010 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
1012 char cmd_buf[SNPRINTF_BUF_LEN];
1013 char cmnt_buf[SNPRINTF_BUF_LEN];
1014 ia32_attr_t *attr = get_ia32_attr(irn);
1015 const char *reg = attr->x87[1]->name;
1016 const char *instr = "fcom";
1019 switch (get_ia32_irn_opcode(irn)) {
1020 case iro_ia32_fcomrJmp:
1022 case iro_ia32_fcomJmp:
1026 case iro_ia32_fcomrpJmp:
1028 case iro_ia32_fcompJmp:
1031 case iro_ia32_fcomrppJmp:
1033 case iro_ia32_fcomppJmp:
1040 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1042 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1043 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1045 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1046 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1048 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1049 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1052 /* the compare flags must be evaluated using carry , ie unsigned */
1053 finish_CondJmp(F, irn, mode_Iu);
1056 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1058 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1059 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1060 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1061 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1062 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1063 int idx_left = 2 - is_PsiCondCMov;
1064 int idx_right = 3 - is_PsiCondCMov;
1066 char cmd_buf[SNPRINTF_BUF_LEN];
1067 char cmnt_buf[SNPRINTF_BUF_LEN];
1068 const arch_register_t *in1, *in2, *out;
1070 out = arch_get_irn_register(env->arch_env, irn);
1071 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1072 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1074 /* we have to emit the cmp first, because the destination register */
1075 /* could be one of the compare registers */
1076 if (is_ia32_CmpCMov(irn)) {
1077 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1079 else if (is_ia32_xCmpCMov(irn)) {
1080 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1082 else if (is_PsiCondCMov) {
1083 /* omit compare because flags are already set by And/Or */
1084 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1087 assert(0 && "unsupported CMov");
1089 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1092 if (REGS_ARE_EQUAL(out, in2)) {
1093 /* best case: default in == out -> do nothing */
1095 else if (REGS_ARE_EQUAL(out, in1)) {
1096 /* true in == out -> need complement compare and exchange true and default in */
1097 ir_node *t = get_irn_n(irn, idx_left);
1098 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1099 set_irn_n(irn, idx_right, t);
1101 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1105 /* out is different from in: need copy default -> out */
1107 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1109 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1111 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1116 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1118 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1120 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1124 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1125 CMov_emitter(irn, env);
1128 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1129 CMov_emitter(irn, env);
1132 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1133 CMov_emitter(irn, env);
1136 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1138 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1139 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1140 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1141 const char *reg8bit;
1143 char cmd_buf[SNPRINTF_BUF_LEN];
1144 char cmnt_buf[SNPRINTF_BUF_LEN];
1145 const arch_register_t *out;
1147 out = arch_get_irn_register(env->arch_env, irn);
1148 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1150 if (is_ia32_CmpSet(irn)) {
1151 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1153 else if (is_ia32_xCmpSet(irn)) {
1154 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1156 else if (is_ia32_PsiCondSet(irn)) {
1157 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, 0", irn);
1160 assert(0 && "unsupported Set");
1162 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1165 /* use mov to clear target because it doesn't affect the eflags */
1166 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1167 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1170 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1171 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1175 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1176 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1179 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1180 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1183 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1184 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1187 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1189 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1191 long pnc = get_ia32_pncode(irn);
1192 long unord = pnc & pn_Cmp_Uo;
1193 char cmd_buf[SNPRINTF_BUF_LEN];
1194 char cmnt_buf[SNPRINTF_BUF_LEN];
1197 case pn_Cmp_Leg: /* odered */
1200 case pn_Cmp_Uo: /* unordered */
1204 case pn_Cmp_Eq: /* == */
1208 case pn_Cmp_Lt: /* < */
1212 case pn_Cmp_Le: /* <= */
1216 case pn_Cmp_Gt: /* > */
1220 case pn_Cmp_Ge: /* >= */
1224 case pn_Cmp_Lg: /* != */
1229 assert(sse_pnc >= 0 && "unsupported compare");
1231 if (unord && sse_pnc != 3) {
1233 We need a separate compare against unordered.
1234 Quick and Dirty solution:
1235 - get some memory on stack
1239 - and result and stored result
1242 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1243 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1245 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1246 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1248 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1249 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1253 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1254 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1257 if (unord && sse_pnc != 3) {
1258 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1259 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1261 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1262 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1267 /*********************************************************
1270 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1271 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1272 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1273 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1276 *********************************************************/
1278 /* jump table entry (target and corresponding number) */
1279 typedef struct _branch_t {
1284 /* jump table for switch generation */
1285 typedef struct _jmp_tbl_t {
1286 ir_node *defProj; /**< default target */
1287 int min_value; /**< smallest switch case */
1288 int max_value; /**< largest switch case */
1289 int num_branches; /**< number of jumps */
1290 char *label; /**< label of the jump table */
1291 branch_t *branches; /**< jump array */
1295 * Compare two variables of type branch_t. Used to sort all switch cases
1297 static int ia32_cmp_branch_t(const void *a, const void *b) {
1298 branch_t *b1 = (branch_t *)a;
1299 branch_t *b2 = (branch_t *)b;
1301 if (b1->value <= b2->value)
1308 * Emits code for a SwitchJmp (creates a jump table if
1309 * possible otherwise a cmp-jmp cascade). Port from
1312 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1313 unsigned long interval;
1314 char buf[SNPRINTF_BUF_LEN];
1315 int last_value, i, pn;
1318 const ir_edge_t *edge;
1319 const lc_arg_env_t *env = ia32_get_arg_env();
1320 FILE *F = emit_env->out;
1321 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1323 /* fill the table structure */
1324 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1325 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1327 tbl.num_branches = get_irn_n_edges(irn);
1328 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1329 tbl.min_value = INT_MAX;
1330 tbl.max_value = INT_MIN;
1333 /* go over all proj's and collect them */
1334 foreach_out_edge(irn, edge) {
1335 proj = get_edge_src_irn(edge);
1336 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1338 pn = get_Proj_proj(proj);
1340 /* create branch entry */
1341 tbl.branches[i].target = proj;
1342 tbl.branches[i].value = pn;
1344 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1345 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1347 /* check for default proj */
1348 if (pn == get_ia32_pncode(irn)) {
1349 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1356 /* sort the branches by their number */
1357 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1359 /* two-complement's magic make this work without overflow */
1360 interval = tbl.max_value - tbl.min_value;
1362 /* emit the table */
1363 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1364 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1367 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1368 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1371 if (tbl.num_branches > 1) {
1374 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1375 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1378 ia32_switch_section(F, SECTION_RODATA);
1379 fprintf(F, "\t.align 4\n");
1381 fprintf(F, "%s:\n", tbl.label);
1383 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1384 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1387 last_value = tbl.branches[0].value;
1388 for (i = 1; i < tbl.num_branches; ++i) {
1389 while (++last_value < tbl.branches[i].value) {
1390 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1391 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1394 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1395 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1398 ia32_switch_section(F, SECTION_TEXT);
1401 /* one jump is enough */
1402 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1403 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1414 * Emits code for a unconditional jump.
1416 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1417 ir_node *block, *next_bl;
1419 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1421 /* for now, the code works for scheduled and non-schedules blocks */
1422 block = get_nodes_block(irn);
1424 /* we have a block schedule */
1425 next_bl = next_blk_sched(block);
1426 if (get_cfop_target_block(irn) != next_bl) {
1427 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1428 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1432 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1437 /****************************
1440 * _ __ _ __ ___ _ ___
1441 * | '_ \| '__/ _ \| |/ __|
1442 * | |_) | | | (_) | |\__ \
1443 * | .__/|_| \___/| ||___/
1446 ****************************/
1449 * Emits code for a proj -> node
1451 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1452 ir_node *pred = get_Proj_pred(irn);
1454 if (get_irn_op(pred) == op_Start) {
1455 switch(get_Proj_proj(irn)) {
1456 case pn_Start_X_initial_exec:
1465 /**********************************
1468 * | | ___ _ __ _ _| |_) |
1469 * | | / _ \| '_ \| | | | _ <
1470 * | |___| (_) | |_) | |_| | |_) |
1471 * \_____\___/| .__/ \__, |____/
1474 **********************************/
1477 * Emit movsb/w instructions to make mov count divideable by 4
1479 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1480 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1482 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1484 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1485 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1490 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1491 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1495 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1496 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1500 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1501 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1503 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1504 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1512 * Emit rep movsd instruction for memcopy.
1514 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1515 FILE *F = emit_env->out;
1516 tarval *tv = get_ia32_Immop_tarval(irn);
1517 int rem = get_tarval_long(tv);
1518 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1520 emit_CopyB_prolog(F, irn, rem);
1522 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1523 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1528 * Emits unrolled memcopy.
1530 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1531 tarval *tv = get_ia32_Immop_tarval(irn);
1532 int size = get_tarval_long(tv);
1533 FILE *F = emit_env->out;
1534 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1536 emit_CopyB_prolog(F, irn, size & 0x3);
1540 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1541 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1548 /***************************
1552 * | | / _ \| '_ \ \ / /
1553 * | |___| (_) | | | \ V /
1554 * \_____\___/|_| |_|\_/
1556 ***************************/
1559 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1561 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1562 FILE *F = emit_env->out;
1563 const lc_arg_env_t *env = ia32_get_arg_env();
1564 ir_mode *src_mode = get_ia32_Conv_src_mode(irn);
1565 ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
1566 char *from, *to, buf[64];
1567 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1569 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1570 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1572 switch(get_ia32_op_type(irn)) {
1574 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1576 case ia32_AddrModeS:
1577 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1580 assert(0 && "unsupported op type for Conv");
1583 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1584 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1588 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1589 emit_ia32_Conv_with_FP(irn, emit_env);
1592 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1593 emit_ia32_Conv_with_FP(irn, emit_env);
1596 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1597 emit_ia32_Conv_with_FP(irn, emit_env);
1601 * Emits code for an Int conversion.
1603 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1604 FILE *F = emit_env->out;
1605 const lc_arg_env_t *env = ia32_get_arg_env();
1606 char *move_cmd = "movzx";
1607 char *conv_cmd = NULL;
1608 ir_mode *src_mode = get_ia32_Conv_src_mode(irn);
1609 ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
1611 int src_bits = get_mode_size_bits(src_mode);
1612 int tgt_bits = get_mode_size_bits(tgt_mode);
1613 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1614 const arch_register_t *in_reg, *out_reg;
1616 assert(mode_is_int(src_mode) && mode_is_int(tgt_mode));
1617 assert(src_bits == 8 || src_bits == 16 || src_bits == 32);
1618 assert(tgt_bits == 8 || tgt_bits == 16 || tgt_bits == 32);
1619 assert(src_bits != tgt_bits);
1621 signed_mode = mode_is_signed(src_bits < tgt_bits ? src_mode : tgt_mode);
1626 switch(get_ia32_op_type(irn)) {
1628 in_reg = get_in_reg(irn, 2);
1629 out_reg = get_out_reg(irn, 0);
1631 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1632 REGS_ARE_EQUAL(out_reg, in_reg) &&
1635 if (src_bits == 8 || tgt_bits == 8)
1637 else if (src_bits == 16 || tgt_bits == 16)
1640 /* argument and result are both in EAX and */
1641 /* signedness is ok: -> use converts */
1642 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1644 else if (REGS_ARE_EQUAL(out_reg, in_reg) && ! signed_mode)
1646 /* argument and result are in the same register */
1647 /* and signedness is ok: -> use and with mask */
1648 int mask = (1 << (src_bits < tgt_bits ? src_bits : tgt_bits)) - 1;
1649 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1652 /* use move w/o sign extension */
1653 ir_mode *smaller_mode = src_bits < tgt_bits ? src_mode : tgt_mode;
1654 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1656 ia32_get_reg_name_for_mode(emit_env, smaller_mode, in_reg));
1660 case ia32_AddrModeS:
1661 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1662 move_cmd, irn, ia32_emit_am(irn, emit_env));
1665 assert(0 && "unsupported op type for Conv");
1668 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1669 irn, src_bits, src_mode, tgt_bits, tgt_mode);
1675 * Emits code for an 8Bit Int conversion.
1677 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1678 emit_ia32_Conv_I2I(irn, emit_env);
1682 /*******************************************
1685 * | |__ ___ _ __ ___ __| | ___ ___
1686 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1687 * | |_) | __/ | | | (_) | (_| | __/\__ \
1688 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1690 *******************************************/
1693 * Emits a backend call
1695 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1696 FILE *F = emit_env->out;
1697 ir_entity *ent = be_Call_get_entity(irn);
1698 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1701 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1704 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1707 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1713 * Emits code to increase stack pointer.
1715 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1716 FILE *F = emit_env->out;
1717 int offs = be_get_IncSP_offset(irn);
1718 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1722 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1724 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1725 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1728 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1729 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1736 * Emits code to set stack pointer.
1738 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1739 FILE *F = emit_env->out;
1740 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1742 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1743 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1748 * Emits code for Copy/CopyKeep.
1750 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1751 FILE *F = emit_env->out;
1752 const arch_env_t *aenv = emit_env->arch_env;
1753 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1755 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1756 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1759 if (mode_is_float(get_irn_mode(irn)))
1760 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1762 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1763 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1767 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1768 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1771 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1772 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1776 * Emits code for exchange.
1778 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1779 FILE *F = emit_env->out;
1780 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1781 const arch_register_t *in1, *in2;
1782 const arch_register_class_t *cls1, *cls2;
1784 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1785 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1787 cls1 = arch_register_get_class(in1);
1788 cls2 = arch_register_get_class(in2);
1790 assert(cls1 == cls2 && "Register class mismatch at Perm");
1792 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1794 if(emit_env->isa->opt_arch == arch_athlon) {
1795 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1796 // it is often beneficial to use the 3 xor trick instead of an xchg
1798 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1800 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1802 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1805 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1810 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1811 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1812 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1814 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1818 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1823 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1828 * Emits code for Constant loading.
1830 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1832 char cmd_buf[256], cmnt_buf[256];
1833 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1834 ir_mode *mode = get_irn_mode(n);
1835 tarval *tv = get_ia32_Immop_tarval(n);
1837 if (get_ia32_op_type(n) == ia32_SymConst) {
1838 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1839 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1841 assert(mode == get_tarval_mode(tv) || (mode_is_reference(get_tarval_mode(tv)) && mode == mode_Iu));
1842 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1843 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1844 const char *instr = "xor";
1845 if (env->isa->opt_arch == arch_pentium_4) {
1846 /* P4 prefers sub r, r, others xor r, r */
1849 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1850 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1852 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1853 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1856 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1860 * Emits code to increase stack pointer.
1862 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1863 FILE *F = emit_env->out;
1864 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1866 if (is_ia32_ImmConst(irn)) {
1867 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1869 else if (is_ia32_ImmSymConst(irn)) {
1870 if (get_ia32_op_type(irn) == ia32_Normal)
1871 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1872 else /* source address mode */
1873 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1876 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1878 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1884 * Emits code to increase stack pointer.
1886 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1887 FILE *F = emit_env->out;
1888 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1890 if (is_ia32_ImmConst(irn)) {
1891 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1893 else if (is_ia32_ImmSymConst(irn)) {
1894 if (get_ia32_op_type(irn) == ia32_Normal)
1895 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1896 else /* source address mode */
1897 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1900 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1902 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1908 * Emits code to load the TLS base
1910 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1911 FILE *F = emit_env->out;
1912 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1914 switch (asm_flavour) {
1916 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1919 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1922 assert(0 && "unsupported TLS");
1925 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1930 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1932 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1934 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1937 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1940 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1944 /***********************************************************************************
1947 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1948 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1949 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1950 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1952 ***********************************************************************************/
1955 * Enters the emitter functions for handled nodes into the generic
1956 * pointer of an opcode.
1958 static void ia32_register_emitters(void) {
1960 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1961 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1962 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1963 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1964 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1965 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1967 /* first clear the generic function pointer for all ops */
1968 clear_irp_opcodes_generic_func();
1970 /* register all emitter functions defined in spec */
1971 ia32_register_spec_emitters();
1973 /* other ia32 emitter functions */
1979 IA32_EMIT(PsiCondCMov);
1981 IA32_EMIT(PsiCondSet);
1982 IA32_EMIT(SwitchJmp);
1985 IA32_EMIT(Conv_I2FP);
1986 IA32_EMIT(Conv_FP2I);
1987 IA32_EMIT(Conv_FP2FP);
1988 IA32_EMIT(Conv_I2I);
1989 IA32_EMIT(Conv_I2I8Bit);
1996 IA32_EMIT(xCmpCMov);
1997 IA32_EMIT(xCondJmp);
1998 IA32_EMIT2(fcomJmp, x87CondJmp);
1999 IA32_EMIT2(fcompJmp, x87CondJmp);
2000 IA32_EMIT2(fcomppJmp, x87CondJmp);
2001 IA32_EMIT2(fcomrJmp, x87CondJmp);
2002 IA32_EMIT2(fcomrpJmp, x87CondJmp);
2003 IA32_EMIT2(fcomrppJmp, x87CondJmp);
2005 /* benode emitter */
2031 static const char *last_name = NULL;
2032 static unsigned last_line = -1;
2033 static unsigned num = -1;
2036 * Emit the debug support for node irn.
2038 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2039 dbg_info *db = get_irn_dbg_info(irn);
2041 const char *fname = be_retrieve_dbg_info(db, &lineno);
2043 if (! env->cg->birg->main_env->options->stabs_debug_support)
2047 if (last_name != fname) {
2049 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2052 if (last_line != lineno) {
2056 snprintf(name, sizeof(name), ".LM%u", ++num);
2058 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2059 fprintf(F, "%s:\n", name);
2065 * Emits code for a node.
2067 static void ia32_emit_node(const ir_node *irn, void *env) {
2068 ia32_emit_env_t *emit_env = env;
2069 ir_op *op = get_irn_op(irn);
2070 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2072 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2074 if (op->ops.generic) {
2075 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2076 ia32_emit_dbg(irn, emit_env);
2080 emit_Nothing(irn, env);
2081 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2086 * Emits gas alignment directives
2088 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2089 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2093 * Emits gas alignment directives for Functions depended on cpu architecture.
2095 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2097 unsigned maximum_skip;
2112 maximum_skip = (1 << align) - 1;
2113 ia32_emit_alignment(F, align, maximum_skip);
2117 * Emits gas alignment directives for Labels depended on cpu architecture.
2119 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2120 unsigned align; unsigned maximum_skip;
2135 maximum_skip = (1 << align) - 1;
2136 ia32_emit_alignment(F, align, maximum_skip);
2139 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2140 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2141 double block_freq, prev_freq;
2142 static const double DELTA = .0001;
2143 cpu_support cpu = env->isa->opt_arch;
2145 if(exec_freq == NULL)
2147 if(cpu == arch_i386 || cpu == arch_i486)
2150 block_freq = get_block_execfreq(exec_freq, block);
2151 prev_freq = get_block_execfreq(exec_freq, prev_block);
2153 if(block_freq < DELTA || prev_freq < DELTA)
2156 block_freq /= prev_freq;
2160 case arch_athlon_64:
2162 return block_freq > 3;
2167 return block_freq > 2;
2171 * Walks over the nodes in a block connected by scheduling edges
2172 * and emits code for each node.
2174 static void ia32_gen_block(ir_node *block, ir_node *last_block, ia32_emit_env_t *env) {
2175 ir_graph *irg = get_irn_irg(block);
2176 ir_node *start_block = get_irg_start_block(irg);
2182 assert(is_Block(block));
2184 if (block == start_block)
2187 if (need_label && get_irn_arity(block) == 1) {
2188 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2190 if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2194 /* special case: if one of our cfg preds is a switch-jmp we need a label, */
2195 /* otherwise there might be jump table entries jumping to */
2196 /* non-existent (omitted) labels */
2197 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2198 ir_node *pred = get_Block_cfgpred(block, i);
2200 if (is_Proj(pred)) {
2201 assert(get_irn_mode(pred) == mode_X);
2202 if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
2209 /* special case because the start block contains no jump instruction */
2210 if (last_block == start_block) {
2211 const ir_edge_t *edge;
2212 ir_node *startsucc = NULL;
2214 foreach_block_succ(start_block, edge) {
2215 startsucc = get_edge_src_irn(edge);
2216 if (startsucc != start_block)
2219 assert(startsucc != NULL);
2221 /* if the last block was the start block and we are not inside the */
2222 /* start successor, emit a jump to the start successor */
2223 if (startsucc != block) {
2224 char buf[SNPRINTF_BUF_LEN];
2225 ir_snprintf(buf, sizeof(buf), BLOCK_PREFIX("%d"),
2226 get_irn_node_nr(startsucc));
2227 ir_fprintf(F, "\tjmp %s\n", buf);
2232 char cmd_buf[SNPRINTF_BUF_LEN];
2235 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2237 /* align the loop headers */
2238 if (! is_first_loop_block(block, last_block, env)) {
2239 /* align blocks where the previous block has no fallthrough */
2240 arity = get_irn_arity(block);
2242 for (i = 0; i < arity; ++i) {
2243 ir_node *predblock = get_Block_cfgpred_block(block, i);
2245 if (predblock == last_block) {
2253 ia32_emit_align_label(env->out, env->isa->opt_arch);
2255 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2256 get_irn_node_nr(block));
2257 fprintf(F, "%-43s ", cmd_buf);
2259 /* emit list of pred blocks in comment */
2260 fprintf(F, "/* preds:");
2262 arity = get_irn_arity(block);
2263 for (i = 0; i < arity; ++i) {
2264 ir_node *predblock = get_Block_cfgpred_block(block, i);
2265 fprintf(F, " %ld", get_irn_node_nr(predblock));
2268 if (exec_freq != NULL) {
2269 fprintf(F, " freq: %f", get_block_execfreq(exec_freq, block));
2272 fprintf(F, " */\n");
2275 /* emit the contents of the block */
2276 ia32_emit_dbg(block, env);
2277 sched_foreach(block, irn) {
2278 ia32_emit_node(irn, env);
2283 * Emits code for function start.
2285 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2286 ir_entity *irg_ent = get_irg_entity(irg);
2287 const char *irg_name = get_entity_ld_name(irg_ent);
2288 cpu_support cpu = emit_env->isa->opt_arch;
2289 const be_irg_t *birg = emit_env->cg->birg;
2292 ia32_switch_section(F, SECTION_TEXT);
2293 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2294 ia32_emit_align_func(F, cpu);
2295 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2296 fprintf(F, ".globl %s\n", irg_name);
2298 ia32_dump_function_object(F, irg_name);
2299 fprintf(F, "%s:\n", irg_name);
2303 * Emits code for function end
2305 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2306 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2307 const be_irg_t *birg = emit_env->cg->birg;
2309 ia32_dump_function_size(F, irg_name);
2310 be_dbg_method_end(birg->main_env->db_handle);
2316 * Sets labels for control flow nodes (jump target)
2317 * TODO: Jump optimization
2319 static void ia32_gen_labels(ir_node *block, void *env) {
2321 int n = get_Block_n_cfgpreds(block);
2323 for (n--; n >= 0; n--) {
2324 pred = get_Block_cfgpred(block, n);
2325 set_irn_link(pred, block);
2330 * Main driver. Emits the code for one routine.
2332 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2333 ia32_emit_env_t emit_env;
2335 ir_node *last_block = NULL;
2338 emit_env.arch_env = cg->arch_env;
2340 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2341 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2343 /* set the global arch_env (needed by print hooks) */
2344 arch_env = cg->arch_env;
2346 ia32_register_emitters();
2348 ia32_emit_func_prolog(F, irg, &emit_env);
2349 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2351 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2352 int i, n = ARR_LEN(cg->blk_sched);
2354 for (i = 0; i < n;) {
2357 block = cg->blk_sched[i];
2359 next_bl = i < n ? cg->blk_sched[i] : NULL;
2361 /* set here the link. the emitter expects to find the next block here */
2362 set_irn_link(block, next_bl);
2363 ia32_gen_block(block, last_block, &emit_env);
2368 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2369 in the block schedule. As this number should NEVER be equal the next block,
2370 we does not need a clear block link here. */
2372 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2376 ia32_emit_func_epilog(F, irg, &emit_env);