2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 #define SNPRINTF_BUF_LEN 128
86 static const ia32_isa_t *isa;
87 static char pic_base_label[128];
88 static ir_label_t exc_label_id;
89 static int mark_spill_reload = 0;
92 /** Return the next block in Block schedule */
93 static ir_node *get_prev_block_sched(const ir_node *block)
95 return (ir_node*)get_irn_link(block);
98 /** Checks if the current block is a fall-through target. */
99 static int is_fallthrough(const ir_node *cfgpred)
103 if (!is_Proj(cfgpred))
105 pred = get_Proj_pred(cfgpred);
106 if (is_ia32_SwitchJmp(pred))
113 * returns non-zero if the given block needs a label
114 * because of being a jump-target (and not a fall-through)
116 static int block_needs_label(const ir_node *block)
119 int n_cfgpreds = get_Block_n_cfgpreds(block);
121 if (get_Block_entity(block) != NULL)
124 if (n_cfgpreds == 0) {
126 } else if (n_cfgpreds == 1) {
127 ir_node *cfgpred = get_Block_cfgpred(block, 0);
128 ir_node *cfgpred_block = get_nodes_block(cfgpred);
130 if (get_prev_block_sched(block) == cfgpred_block
131 && is_fallthrough(cfgpred)) {
140 * Add a number to a prefix. This number will not be used a second time.
142 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
144 static unsigned long id = 0;
145 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
150 * Emit the name of the 8bit low register
152 static void emit_8bit_register(const arch_register_t *reg)
154 const char *reg_name = arch_register_get_name(reg);
155 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
156 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
159 be_emit_char(reg_name[1]); /* get the basic name of the register */
164 * Emit the name of the 8bit high register
166 static void emit_8bit_register_high(const arch_register_t *reg)
168 const char *reg_name = arch_register_get_name(reg);
169 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
170 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
173 be_emit_char(reg_name[1]); /* get the basic name of the register */
177 static void emit_16bit_register(const arch_register_t *reg)
179 const char *reg_name = arch_register_get_name(reg);
182 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
186 * emit a register, possible shortened by a mode
188 * @param reg the register
189 * @param mode the mode of the register or NULL for full register
191 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
193 const char *reg_name;
196 int size = get_mode_size_bits(mode);
198 case 8: emit_8bit_register(reg); return;
199 case 16: emit_16bit_register(reg); return;
201 assert(mode_is_float(mode) || size == 32);
204 reg_name = arch_register_get_name(reg);
207 be_emit_string(reg_name);
210 void ia32_emit_source_register(const ir_node *node, int pos)
212 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
214 emit_register(reg, NULL);
217 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
219 be_gas_emit_entity(entity);
221 if (get_entity_owner(entity) == get_tls_type()) {
222 if (get_entity_visibility(entity) == ir_visibility_external) {
223 be_emit_cstring("@INDNTPOFF");
225 be_emit_cstring("@NTPOFF");
229 if (do_pic && !no_pic_adjust) {
231 be_emit_string(pic_base_label);
235 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
237 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
239 if (attr->symconst != NULL) {
242 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
244 if (attr->symconst == NULL || attr->offset != 0) {
245 if (attr->symconst != NULL) {
246 be_emit_irprintf("%+d", attr->offset);
248 be_emit_irprintf("0x%X", attr->offset);
253 static void emit_ia32_Immediate(const ir_node *node)
256 emit_ia32_Immediate_no_prefix(node);
259 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
261 const arch_register_t *reg;
262 const ir_node *in = get_irn_n(node, pos);
263 if (is_ia32_Immediate(in)) {
264 emit_ia32_Immediate(in);
268 reg = arch_get_irn_register_in(node, pos);
269 emit_8bit_register(reg);
272 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
274 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
275 emit_8bit_register_high(reg);
278 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
280 const arch_register_t *reg;
281 const ir_node *in = get_irn_n(node, pos);
282 if (is_ia32_Immediate(in)) {
283 emit_ia32_Immediate(in);
287 reg = arch_get_irn_register_in(node, pos);
288 emit_16bit_register(reg);
291 void ia32_emit_dest_register(const ir_node *node, int pos)
293 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
295 emit_register(reg, NULL);
298 void ia32_emit_dest_register_size(const ir_node *node, int pos)
300 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
302 emit_register(reg, get_ia32_ls_mode(node));
305 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
307 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
309 emit_register(reg, mode_Bu);
312 void ia32_emit_x87_register(const ir_node *node, int pos)
314 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
318 be_emit_string(attr->x87[pos]->name);
321 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
323 assert(mode_is_int(mode) || mode_is_reference(mode));
324 switch (get_mode_size_bits(mode)) {
325 case 8: be_emit_char('b'); return;
326 case 16: be_emit_char('w'); return;
327 case 32: be_emit_char('l'); return;
328 /* gas docu says q is the suffix but gcc, objdump and icc use ll
330 case 64: be_emit_cstring("ll"); return;
332 panic("Can't output mode_suffix for %+F", mode);
335 void ia32_emit_mode_suffix(const ir_node *node)
337 ir_mode *mode = get_ia32_ls_mode(node);
341 ia32_emit_mode_suffix_mode(mode);
344 void ia32_emit_x87_mode_suffix(const ir_node *node)
348 /* we only need to emit the mode on address mode */
349 if (get_ia32_op_type(node) == ia32_Normal)
352 mode = get_ia32_ls_mode(node);
353 assert(mode != NULL);
355 if (mode_is_float(mode)) {
356 switch (get_mode_size_bits(mode)) {
357 case 32: be_emit_char('s'); return;
358 case 64: be_emit_char('l'); return;
359 /* long doubles have different sizes due to alignment on different
363 case 128: be_emit_char('t'); return;
366 assert(mode_is_int(mode) || mode_is_reference(mode));
367 switch (get_mode_size_bits(mode)) {
368 case 16: be_emit_char('s'); return;
369 case 32: be_emit_char('l'); return;
370 /* gas docu says q is the suffix but gcc, objdump and icc use ll
372 case 64: be_emit_cstring("ll"); return;
375 panic("Can't output mode_suffix for %+F", mode);
378 static char get_xmm_mode_suffix(ir_mode *mode)
380 assert(mode_is_float(mode));
381 switch (get_mode_size_bits(mode)) {
384 default: panic("Invalid XMM mode");
388 void ia32_emit_xmm_mode_suffix(const ir_node *node)
390 ir_mode *mode = get_ia32_ls_mode(node);
391 assert(mode != NULL);
393 be_emit_char(get_xmm_mode_suffix(mode));
396 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
398 ir_mode *mode = get_ia32_ls_mode(node);
399 assert(mode != NULL);
400 be_emit_char(get_xmm_mode_suffix(mode));
403 void ia32_emit_extend_suffix(const ir_node *node)
405 ir_mode *mode = get_ia32_ls_mode(node);
406 if (get_mode_size_bits(mode) == 32)
408 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
409 ia32_emit_mode_suffix_mode(mode);
412 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
414 ir_node *in = get_irn_n(node, pos);
415 if (is_ia32_Immediate(in)) {
416 emit_ia32_Immediate(in);
418 const ir_mode *mode = get_ia32_ls_mode(node);
419 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
420 emit_register(reg, mode);
425 * Returns the target block for a control flow node.
427 static ir_node *get_cfop_target_block(const ir_node *irn)
429 assert(get_irn_mode(irn) == mode_X);
430 return (ir_node*)get_irn_link(irn);
434 * Emits the target label for a control flow node.
436 static void ia32_emit_cfop_target(const ir_node *node)
438 ir_node *block = get_cfop_target_block(node);
439 be_gas_emit_block_name(block);
443 * Emit the suffix for a compare instruction.
445 static void ia32_emit_condition_code(ia32_condition_code_t cc)
448 case ia32_cc_overflow: be_emit_cstring("o"); return;
449 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
450 case ia32_cc_float_below:
451 case ia32_cc_float_unordered_below:
452 case ia32_cc_below: be_emit_cstring("b"); return;
453 case ia32_cc_float_above_equal:
454 case ia32_cc_float_unordered_above_equal:
455 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
456 case ia32_cc_float_equal:
457 case ia32_cc_equal: be_emit_cstring("e"); return;
458 case ia32_cc_float_not_equal:
459 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
460 case ia32_cc_float_below_equal:
461 case ia32_cc_float_unordered_below_equal:
462 case ia32_cc_below_equal: be_emit_cstring("be"); return;
463 case ia32_cc_float_above:
464 case ia32_cc_float_unordered_above:
465 case ia32_cc_above: be_emit_cstring("a"); return;
466 case ia32_cc_sign: be_emit_cstring("s"); return;
467 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
468 case ia32_cc_parity: be_emit_cstring("p"); return;
469 case ia32_cc_not_parity: be_emit_cstring("np"); return;
470 case ia32_cc_less: be_emit_cstring("l"); return;
471 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
472 case ia32_cc_less_equal: be_emit_cstring("le"); return;
473 case ia32_cc_greater: be_emit_cstring("g"); return;
474 case ia32_cc_float_parity_cases:
475 case ia32_cc_additional_float_cases:
478 panic("Invalid ia32 condition code");
481 typedef enum ia32_emit_mod_t {
483 EMIT_RESPECT_LS = 1U << 0,
484 EMIT_ALTERNATE_AM = 1U << 1,
486 EMIT_HIGH_REG = 1U << 3,
487 EMIT_LOW_REG = 1U << 4
489 ENUM_BITSET(ia32_emit_mod_t)
492 * Emits address mode.
494 void ia32_emit_am(const ir_node *node)
496 ir_entity *ent = get_ia32_am_sc(node);
497 int offs = get_ia32_am_offs_int(node);
498 ir_node *base = get_irn_n(node, n_ia32_base);
499 int has_base = !is_ia32_NoReg_GP(base);
500 ir_node *idx = get_irn_n(node, n_ia32_index);
501 int has_index = !is_ia32_NoReg_GP(idx);
503 /* just to be sure... */
504 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
506 if (get_ia32_am_tls_segment(node))
507 be_emit_cstring("%gs:");
511 const ia32_attr_t *attr = get_ia32_attr_const(node);
512 if (is_ia32_am_sc_sign(node))
514 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
517 /* also handle special case if nothing is set */
518 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
520 be_emit_irprintf("%+d", offs);
522 be_emit_irprintf("%d", offs);
526 if (has_base || has_index) {
531 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
532 emit_register(reg, NULL);
535 /* emit index + scale */
537 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
540 emit_register(reg, NULL);
542 scale = get_ia32_am_scale(node);
544 be_emit_irprintf(",%d", 1 << scale);
552 * fmt parameter output
553 * ---- ---------------------- ---------------------------------------------
555 * %AM <node> address mode of the node
556 * %AR const arch_register_t* address mode of the node or register
557 * %ASx <node> address mode of the node or source register x
558 * %Dx <node> destination register x
559 * %I <node> immediate of the node
560 * %L <node> control flow target of the node
561 * %M <node> mode suffix of the node
562 * %P int condition code
563 * %R const arch_register_t* register
564 * %Sx <node> source register x
565 * %s const char* string
566 * %u unsigned int unsigned int
567 * %d signed int signed int
570 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
571 * * modifier does not prefix immediates with $, but AM with *
572 * l modifier for %lu and %ld
573 * > modifier to output high 8bit register (ah, bh)
574 * < modifier to output low 8bit register (al, bl)
576 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
582 const char *start = fmt;
583 ia32_emit_mod_t mod = EMIT_NONE;
585 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
588 be_emit_string_len(start, fmt - start);
592 be_emit_finish_line_gas(node);
605 case '*': mod |= EMIT_ALTERNATE_AM; break;
606 case '#': mod |= EMIT_RESPECT_LS; break;
607 case 'l': mod |= EMIT_LONG; break;
608 case '>': mod |= EMIT_HIGH_REG; break;
609 case '<': mod |= EMIT_LOW_REG; break;
618 arch_register_t const *reg;
629 if (mod & EMIT_ALTERNATE_AM)
635 reg = va_arg(ap, const arch_register_t*);
636 if (get_ia32_op_type(node) == ia32_AddrModeS) {
643 if (get_ia32_op_type(node) == ia32_AddrModeS) {
647 assert(get_ia32_op_type(node) == ia32_Normal);
651 default: goto unknown;
657 if (*fmt < '0' || '9' <= *fmt)
659 reg = arch_get_irn_register_out(node, *fmt++ - '0');
665 if (!(mod & EMIT_ALTERNATE_AM))
667 emit_ia32_Immediate_no_prefix(imm);
671 ia32_emit_cfop_target(node);
675 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
679 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
680 ia32_emit_condition_code(cc);
685 reg = va_arg(ap, const arch_register_t*);
687 if (mod & EMIT_ALTERNATE_AM)
689 if (mod & EMIT_HIGH_REG) {
690 emit_8bit_register_high(reg);
691 } else if (mod & EMIT_LOW_REG) {
692 emit_8bit_register(reg);
694 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
702 if (*fmt < '0' || '9' <= *fmt)
706 imm = get_irn_n(node, pos);
707 if (is_ia32_Immediate(imm)) {
710 reg = arch_get_irn_register_in(node, pos);
716 const char *str = va_arg(ap, const char*);
722 if (mod & EMIT_LONG) {
723 unsigned long num = va_arg(ap, unsigned long);
724 be_emit_irprintf("%lu", num);
726 unsigned num = va_arg(ap, unsigned);
727 be_emit_irprintf("%u", num);
732 if (mod & EMIT_LONG) {
733 long num = va_arg(ap, long);
734 be_emit_irprintf("%ld", num);
736 int num = va_arg(ap, int);
737 be_emit_irprintf("%d", num);
743 panic("unknown format conversion in ia32_emitf()");
751 * Emits registers and/or address mode of a binary operation.
753 void ia32_emit_binop(const ir_node *node)
755 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
756 ia32_emitf(node, "%#S4, %#AS3");
758 ia32_emitf(node, "%#AS4, %#S3");
763 * Emits registers and/or address mode of a binary operation.
765 void ia32_emit_x87_binop(const ir_node *node)
767 switch (get_ia32_op_type(node)) {
770 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
771 const arch_register_t *in1 = x87_attr->x87[0];
772 const arch_register_t *in = x87_attr->x87[1];
773 const arch_register_t *out = x87_attr->x87[2];
777 } else if (out == in) {
782 be_emit_string(arch_register_get_name(in));
783 be_emit_cstring(", %");
784 be_emit_string(arch_register_get_name(out));
792 assert(0 && "unsupported op type");
797 * Emits registers and/or address mode of a unary operation.
799 void ia32_emit_unop(const ir_node *node, int pos)
803 ia32_emitf(node, fmt);
806 static void emit_ia32_IMul(const ir_node *node)
808 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
809 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
811 /* do we need the 3-address form? */
812 if (is_ia32_NoReg_GP(left) ||
813 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
814 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
816 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
821 * walks up a tree of copies/perms/spills/reloads to find the original value
822 * that is moved around
824 static ir_node *find_original_value(ir_node *node)
826 if (irn_visited(node))
829 mark_irn_visited(node);
830 if (be_is_Copy(node)) {
831 return find_original_value(be_get_Copy_op(node));
832 } else if (be_is_CopyKeep(node)) {
833 return find_original_value(be_get_CopyKeep_op(node));
834 } else if (is_Proj(node)) {
835 ir_node *pred = get_Proj_pred(node);
836 if (be_is_Perm(pred)) {
837 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
838 } else if (be_is_MemPerm(pred)) {
839 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
840 } else if (is_ia32_Load(pred)) {
841 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
842 } else if (is_ia32_Store(pred)) {
843 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
847 } else if (is_Phi(node)) {
849 arity = get_irn_arity(node);
850 for (i = 0; i < arity; ++i) {
851 ir_node *in = get_irn_n(node, i);
852 ir_node *res = find_original_value(in);
863 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
865 ir_node *flags = get_irn_n(node, flags_pos);
866 const ia32_attr_t *flags_attr;
867 flags = skip_Proj(flags);
869 if (is_ia32_Sahf(flags)) {
870 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
871 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
872 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
873 inc_irg_visited(current_ir_graph);
874 cmp = find_original_value(cmp);
876 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
877 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
880 flags_attr = get_ia32_attr_const(cmp);
882 flags_attr = get_ia32_attr_const(flags);
885 if (flags_attr->data.ins_permuted)
886 cc = ia32_invert_condition_code(cc);
890 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
892 ia32_condition_code_t cc = get_ia32_condcode(node);
893 cc = determine_final_cc(node, flags_pos, cc);
895 ia32_emit_condition_code(cc);
899 * Emits an exception label for a given node.
901 static void ia32_emit_exc_label(const ir_node *node)
903 be_emit_string(be_gas_insn_label_prefix());
904 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
908 * Returns the Proj with projection number proj and NOT mode_M
910 static ir_node *get_proj(const ir_node *node, long proj)
912 const ir_edge_t *edge;
915 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
917 foreach_out_edge(node, edge) {
918 src = get_edge_src_irn(edge);
920 assert(is_Proj(src) && "Proj expected");
921 if (get_irn_mode(src) == mode_M)
924 if (get_Proj_proj(src) == proj)
930 static int can_be_fallthrough(const ir_node *node)
932 ir_node *target_block = get_cfop_target_block(node);
933 ir_node *block = get_nodes_block(node);
934 return get_prev_block_sched(target_block) == block;
938 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
940 static void emit_ia32_Jcc(const ir_node *node)
942 int need_parity_label = 0;
943 ia32_condition_code_t cc = get_ia32_condcode(node);
944 const ir_node *proj_true;
945 const ir_node *proj_false;
947 cc = determine_final_cc(node, 0, cc);
950 proj_true = get_proj(node, pn_ia32_Jcc_true);
951 assert(proj_true && "Jcc without true Proj");
953 proj_false = get_proj(node, pn_ia32_Jcc_false);
954 assert(proj_false && "Jcc without false Proj");
956 if (can_be_fallthrough(proj_true)) {
957 /* exchange both proj's so the second one can be omitted */
958 const ir_node *t = proj_true;
960 proj_true = proj_false;
962 cc = ia32_negate_condition_code(cc);
965 if (cc & ia32_cc_float_parity_cases) {
966 /* Some floating point comparisons require a test of the parity flag,
967 * which indicates that the result is unordered */
968 if (cc & ia32_cc_negated) {
969 ia32_emitf(proj_true, "\tjp %L\n");
971 /* we need a local label if the false proj is a fallthrough
972 * as the falseblock might have no label emitted then */
973 if (can_be_fallthrough(proj_false)) {
974 need_parity_label = 1;
975 ia32_emitf(proj_false, "\tjp 1f\n");
977 ia32_emitf(proj_false, "\tjp %L\n");
981 ia32_emitf(proj_true, "\tj%P %L\n", cc);
982 if (need_parity_label) {
983 ia32_emitf(NULL, "1:\n");
986 /* the second Proj might be a fallthrough */
987 if (can_be_fallthrough(proj_false)) {
988 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
990 ia32_emitf(proj_false, "\tjmp %L\n");
995 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
998 static void emit_ia32_Setcc(const ir_node *node)
1000 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
1002 ia32_condition_code_t cc = get_ia32_condcode(node);
1003 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1004 if (cc & ia32_cc_float_parity_cases) {
1005 if (cc & ia32_cc_negated) {
1006 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1007 ia32_emitf(node, "\tsetp %>R\n", dreg);
1008 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1010 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1011 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1012 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1015 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1019 static void emit_ia32_CMovcc(const ir_node *node)
1021 const ia32_attr_t *attr = get_ia32_attr_const(node);
1022 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
1023 ia32_condition_code_t cc = get_ia32_condcode(node);
1024 const arch_register_t *in_true;
1025 const arch_register_t *in_false;
1027 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1028 /* although you can't set ins_permuted in the constructor it might still
1029 * be set by memory operand folding
1030 * Permuting inputs of a cmov means the condition is negated!
1032 if (attr->data.ins_permuted)
1033 cc = ia32_negate_condition_code(cc);
1035 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1036 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1038 /* should be same constraint fullfilled? */
1039 if (out == in_false) {
1040 /* yes -> nothing to do */
1041 } else if (out == in_true) {
1042 const arch_register_t *tmp;
1044 assert(get_ia32_op_type(node) == ia32_Normal);
1046 cc = ia32_negate_condition_code(cc);
1053 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1056 if (cc & ia32_cc_float_parity_cases) {
1057 panic("CMov with floatingpoint compare/parity not supported yet");
1060 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1064 * Emits code for a SwitchJmp
1066 static void emit_ia32_SwitchJmp(const ir_node *node)
1068 ir_entity *jump_table = get_ia32_am_sc(node);
1069 const ir_switch_table *table = get_ia32_switch_table(node);
1071 ia32_emitf(node, "\tjmp %*AM\n");
1072 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
1076 * Emits code for a unconditional jump.
1078 static void emit_ia32_Jmp(const ir_node *node)
1080 /* we have a block schedule */
1081 if (can_be_fallthrough(node)) {
1082 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1084 ia32_emitf(node, "\tjmp %L\n");
1089 * Emit an inline assembler operand.
1091 * @param node the ia32_ASM node
1092 * @param s points to the operand (a %c)
1094 * @return pointer to the first char in s NOT in the current operand
1096 static const char* emit_asm_operand(const ir_node *node, const char *s)
1098 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1099 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1101 const arch_register_t *reg;
1102 const ia32_asm_reg_t *asm_regs = attr->register_map;
1103 const ia32_asm_reg_t *asm_reg;
1112 /* parse modifiers */
1115 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1140 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1147 if (sscanf(s, "%d%n", &num, &p) != 1) {
1148 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1155 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1157 "Error: Custom assembler references invalid input/output (%+F)\n",
1161 asm_reg = & asm_regs[num];
1162 assert(asm_reg->valid);
1165 if (asm_reg->use_input == 0) {
1166 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1168 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1170 /* might be an immediate value */
1171 if (is_ia32_Immediate(pred)) {
1172 emit_ia32_Immediate(pred);
1175 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1179 "Warning: no register assigned for %d asm op (%+F)\n",
1184 if (asm_reg->memory) {
1189 if (modifier != 0) {
1192 emit_8bit_register(reg);
1195 emit_8bit_register_high(reg);
1198 emit_16bit_register(reg);
1201 panic("Invalid asm op modifier");
1204 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1207 if (asm_reg->memory) {
1215 * Emits code for an ASM pseudo op.
1217 static void emit_ia32_Asm(const ir_node *node)
1219 const void *gen_attr = get_irn_generic_attr_const(node);
1220 const ia32_asm_attr_t *attr
1221 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1222 ident *asm_text = attr->asm_text;
1223 const char *s = get_id_str(asm_text);
1225 ia32_emitf(node, "#APP\t\n");
1232 s = emit_asm_operand(node, s);
1238 ia32_emitf(NULL, "\n#NO_APP\n");
1243 * Emit movsb/w instructions to make mov count divideable by 4
1245 static void emit_CopyB_prolog(unsigned size)
1248 ia32_emitf(NULL, "\tmovsb\n");
1250 ia32_emitf(NULL, "\tmovsw\n");
1254 * Emit rep movsd instruction for memcopy.
1256 static void emit_ia32_CopyB(const ir_node *node)
1258 unsigned size = get_ia32_copyb_size(node);
1260 emit_CopyB_prolog(size);
1261 ia32_emitf(node, "\trep movsd\n");
1265 * Emits unrolled memcopy.
1267 static void emit_ia32_CopyB_i(const ir_node *node)
1269 unsigned size = get_ia32_copyb_size(node);
1271 emit_CopyB_prolog(size);
1275 ia32_emitf(NULL, "\tmovsd\n");
1281 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1283 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1286 ir_mode *ls_mode = get_ia32_ls_mode(node);
1287 int ls_bits = get_mode_size_bits(ls_mode);
1288 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1290 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1293 static void emit_ia32_Conv_I2FP(const ir_node *node)
1295 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1298 static void emit_ia32_Conv_FP2I(const ir_node *node)
1300 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1303 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1305 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1309 * Emits code for an Int conversion.
1311 static void emit_ia32_Conv_I2I(const ir_node *node)
1313 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1314 int signed_mode = mode_is_signed(smaller_mode);
1315 const char *sign_suffix;
1317 assert(!mode_is_float(smaller_mode));
1319 sign_suffix = signed_mode ? "s" : "z";
1320 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1326 static void emit_ia32_Call(const ir_node *node)
1328 /* Special case: Call must not have its immediates prefixed by $, instead
1329 * address mode is prefixed by *. */
1330 ia32_emitf(node, "\tcall %*AS3\n");
1335 * Emits code to increase stack pointer.
1337 static void emit_be_IncSP(const ir_node *node)
1339 int offs = be_get_IncSP_offset(node);
1345 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1347 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1352 * Emits code for Copy/CopyKeep.
1354 static void Copy_emitter(const ir_node *node, const ir_node *op)
1356 const arch_register_t *in = arch_get_irn_register(op);
1357 const arch_register_t *out = arch_get_irn_register(node);
1362 /* copies of vf nodes aren't real... */
1363 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1366 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1369 static void emit_be_Copy(const ir_node *node)
1371 Copy_emitter(node, be_get_Copy_op(node));
1374 static void emit_be_CopyKeep(const ir_node *node)
1376 Copy_emitter(node, be_get_CopyKeep_op(node));
1380 * Emits code for exchange.
1382 static void emit_be_Perm(const ir_node *node)
1384 const arch_register_t *in0, *in1;
1385 const arch_register_class_t *cls0, *cls1;
1387 in0 = arch_get_irn_register(get_irn_n(node, 0));
1388 in1 = arch_get_irn_register(get_irn_n(node, 1));
1390 cls0 = arch_register_get_class(in0);
1391 cls1 = arch_register_get_class(in1);
1393 assert(cls0 == cls1 && "Register class mismatch at Perm");
1395 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1396 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1397 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1398 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1399 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1400 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1401 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1403 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1406 panic("unexpected register class in be_Perm (%+F)", node);
1411 * Emits code for Constant loading.
1413 static void emit_ia32_Const(const ir_node *node)
1415 ia32_emitf(node, "\tmovl %I, %D0\n");
1418 /* helper function for emit_ia32_Minus64Bit */
1419 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1421 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1424 /* helper function for emit_ia32_Minus64Bit */
1425 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1427 ia32_emitf(node, "\tnegl %R\n", reg);
1430 /* helper function for emit_ia32_Minus64Bit */
1431 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1433 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1436 /* helper function for emit_ia32_Minus64Bit */
1437 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1439 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1442 /* helper function for emit_ia32_Minus64Bit */
1443 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1445 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1448 /* helper function for emit_ia32_Minus64Bit */
1449 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1451 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1454 static void emit_ia32_Minus64Bit(const ir_node *node)
1456 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1457 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1458 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1459 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1461 if (out_lo == in_lo) {
1462 if (out_hi != in_hi) {
1463 /* a -> a, b -> d */
1466 /* a -> a, b -> b */
1469 } else if (out_lo == in_hi) {
1470 if (out_hi == in_lo) {
1471 /* a -> b, b -> a */
1472 emit_xchg(node, in_lo, in_hi);
1475 /* a -> b, b -> d */
1476 emit_mov(node, in_hi, out_hi);
1477 emit_mov(node, in_lo, out_lo);
1481 if (out_hi == in_lo) {
1482 /* a -> c, b -> a */
1483 emit_mov(node, in_lo, out_lo);
1485 } else if (out_hi == in_hi) {
1486 /* a -> c, b -> b */
1487 emit_mov(node, in_lo, out_lo);
1490 /* a -> c, b -> d */
1491 emit_mov(node, in_lo, out_lo);
1497 emit_neg( node, out_hi);
1498 emit_neg( node, out_lo);
1499 emit_sbb0(node, out_hi);
1503 emit_zero(node, out_hi);
1504 emit_neg( node, out_lo);
1505 emit_sbb( node, in_hi, out_hi);
1508 static void emit_ia32_GetEIP(const ir_node *node)
1510 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1511 ia32_emitf(NULL, "%s:\n", pic_base_label);
1512 ia32_emitf(node, "\tpopl %D0\n");
1515 static void emit_ia32_ClimbFrame(const ir_node *node)
1517 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1519 ia32_emitf(node, "\tmovl %S0, %D0\n");
1520 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1521 be_gas_emit_block_name(node);
1522 be_emit_cstring(":\n");
1523 be_emit_write_line();
1524 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1525 ia32_emitf(node, "\tdec %S1\n");
1526 be_emit_cstring("\tjnz ");
1527 be_gas_emit_block_name(node);
1528 be_emit_finish_line_gas(node);
1531 static void emit_be_Return(const ir_node *node)
1533 unsigned pop = be_Return_get_pop(node);
1535 if (pop > 0 || be_Return_get_emit_pop(node)) {
1536 ia32_emitf(node, "\tret $%u\n", pop);
1538 ia32_emitf(node, "\tret\n");
1542 static void emit_Nothing(const ir_node *node)
1549 * Enters the emitter functions for handled nodes into the generic
1550 * pointer of an opcode.
1552 static void ia32_register_emitters(void)
1554 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1555 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1556 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1557 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1558 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1559 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1561 /* first clear the generic function pointer for all ops */
1562 ir_clear_opcodes_generic_func();
1564 /* register all emitter functions defined in spec */
1565 ia32_register_spec_emitters();
1567 /* other ia32 emitter functions */
1568 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1573 IA32_EMIT(Conv_FP2FP);
1574 IA32_EMIT(Conv_FP2I);
1575 IA32_EMIT(Conv_I2FP);
1576 IA32_EMIT(Conv_I2I);
1583 IA32_EMIT(Minus64Bit);
1584 IA32_EMIT(SwitchJmp);
1585 IA32_EMIT(ClimbFrame);
1588 /* benode emitter */
1608 typedef void (*emit_func_ptr) (const ir_node *);
1611 * Assign and emit an exception label if the current instruction can fail.
1613 static void ia32_assign_exc_label(ir_node *node)
1615 /* assign a new ID to the instruction */
1616 set_ia32_exc_label_id(node, ++exc_label_id);
1618 ia32_emit_exc_label(node);
1620 be_emit_pad_comment();
1621 be_emit_cstring("/* exception to Block ");
1622 ia32_emit_cfop_target(node);
1623 be_emit_cstring(" */\n");
1624 be_emit_write_line();
1628 * Emits code for a node.
1630 static void ia32_emit_node(ir_node *node)
1632 ir_op *op = get_irn_op(node);
1634 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1636 if (is_ia32_irn(node)) {
1637 if (get_ia32_exc_label(node)) {
1638 /* emit the exception label of this instruction */
1639 ia32_assign_exc_label(node);
1641 if (mark_spill_reload) {
1642 if (is_ia32_is_spill(node)) {
1643 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1645 if (is_ia32_is_reload(node)) {
1646 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1648 if (is_ia32_is_remat(node)) {
1649 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1653 if (op->ops.generic) {
1654 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1656 be_dwarf_location(get_irn_dbg_info(node));
1661 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1667 * Emits gas alignment directives
1669 static void ia32_emit_alignment(unsigned align, unsigned skip)
1671 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1675 * Emits gas alignment directives for Labels depended on cpu architecture.
1677 static void ia32_emit_align_label(void)
1679 unsigned align = ia32_cg_config.label_alignment;
1680 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1681 ia32_emit_alignment(align, maximum_skip);
1685 * Test whether a block should be aligned.
1686 * For cpus in the P4/Athlon class it is useful to align jump labels to
1687 * 16 bytes. However we should only do that if the alignment nops before the
1688 * label aren't executed more often than we have jumps to the label.
1690 static int should_align_block(const ir_node *block)
1692 static const double DELTA = .0001;
1693 ir_graph *irg = get_irn_irg(block);
1694 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1695 ir_node *prev = get_prev_block_sched(block);
1697 double prev_freq = 0; /**< execfreq of the fallthrough block */
1698 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1701 if (exec_freq == NULL)
1703 if (ia32_cg_config.label_alignment_factor <= 0)
1706 block_freq = get_block_execfreq(exec_freq, block);
1707 if (block_freq < DELTA)
1710 n_cfgpreds = get_Block_n_cfgpreds(block);
1711 for (i = 0; i < n_cfgpreds; ++i) {
1712 const ir_node *pred = get_Block_cfgpred_block(block, i);
1713 double pred_freq = get_block_execfreq(exec_freq, pred);
1716 prev_freq += pred_freq;
1718 jmp_freq += pred_freq;
1722 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1725 jmp_freq /= prev_freq;
1727 return jmp_freq > ia32_cg_config.label_alignment_factor;
1731 * Emit the block header for a block.
1733 * @param block the block
1734 * @param prev_block the previous block
1736 static void ia32_emit_block_header(ir_node *block)
1738 ir_graph *irg = current_ir_graph;
1739 int need_label = block_needs_label(block);
1740 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1743 if (block == get_irg_end_block(irg))
1746 if (ia32_cg_config.label_alignment > 0) {
1747 /* align the current block if:
1748 * a) if should be aligned due to its execution frequency
1749 * b) there is no fall-through here
1751 if (should_align_block(block)) {
1752 ia32_emit_align_label();
1754 /* if the predecessor block has no fall-through,
1755 we can always align the label. */
1757 int has_fallthrough = 0;
1759 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1760 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1761 if (can_be_fallthrough(cfg_pred)) {
1762 has_fallthrough = 1;
1767 if (!has_fallthrough)
1768 ia32_emit_align_label();
1773 be_gas_emit_block_name(block);
1776 be_emit_pad_comment();
1777 be_emit_cstring(" /* ");
1779 be_emit_cstring("\t/* ");
1780 be_gas_emit_block_name(block);
1781 be_emit_cstring(": ");
1784 be_emit_cstring("preds:");
1786 /* emit list of pred blocks in comment */
1787 arity = get_irn_arity(block);
1789 be_emit_cstring(" none");
1792 for (i = 0; i < arity; ++i) {
1793 ir_node *predblock = get_Block_cfgpred_block(block, i);
1794 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1797 if (exec_freq != NULL) {
1798 be_emit_irprintf(", freq: %f",
1799 get_block_execfreq(exec_freq, block));
1801 be_emit_cstring(" */\n");
1802 be_emit_write_line();
1806 * Walks over the nodes in a block connected by scheduling edges
1807 * and emits code for each node.
1809 static void ia32_gen_block(ir_node *block)
1813 ia32_emit_block_header(block);
1815 /* emit the contents of the block */
1816 be_dwarf_location(get_irn_dbg_info(block));
1817 sched_foreach(block, node) {
1818 ia32_emit_node(node);
1822 typedef struct exc_entry {
1823 ir_node *exc_instr; /** The instruction that can issue an exception. */
1824 ir_node *block; /** The block to call then. */
1829 * Sets labels for control flow nodes (jump target).
1830 * Links control predecessors to there destination blocks.
1832 static void ia32_gen_labels(ir_node *block, void *data)
1834 exc_entry **exc_list = (exc_entry**)data;
1838 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1839 pred = get_Block_cfgpred(block, n);
1840 set_irn_link(pred, block);
1842 pred = skip_Proj(pred);
1843 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1848 ARR_APP1(exc_entry, *exc_list, e);
1849 set_irn_link(pred, block);
1855 * Compare two exception_entries.
1857 static int cmp_exc_entry(const void *a, const void *b)
1859 const exc_entry *ea = (const exc_entry*)a;
1860 const exc_entry *eb = (const exc_entry*)b;
1862 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1868 * Main driver. Emits the code for one routine.
1870 void ia32_gen_routine(ir_graph *irg)
1872 ir_entity *entity = get_irg_entity(irg);
1873 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1874 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1875 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1876 ir_node **blk_sched = irg_data->blk_sched;
1879 isa = (ia32_isa_t*) arch_env;
1880 do_pic = be_get_irg_options(irg)->pic;
1882 be_gas_elf_type_char = '@';
1884 ia32_register_emitters();
1886 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1888 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
1890 /* we use links to point to target blocks */
1891 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1892 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1894 /* initialize next block links */
1895 n = ARR_LEN(blk_sched);
1896 for (i = 0; i < n; ++i) {
1897 ir_node *block = blk_sched[i];
1898 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1900 set_irn_link(block, prev);
1903 for (i = 0; i < n; ++i) {
1904 ir_node *block = blk_sched[i];
1906 ia32_gen_block(block);
1909 be_gas_emit_function_epilog(entity);
1911 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1913 /* Sort the exception table using the exception label id's.
1914 Those are ascending with ascending addresses. */
1915 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1919 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1920 be_emit_cstring("\t.long ");
1921 ia32_emit_exc_label(exc_list[e].exc_instr);
1923 be_emit_cstring("\t.long ");
1924 be_gas_emit_block_name(exc_list[e].block);
1928 DEL_ARR_F(exc_list);
1931 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1932 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1936 /* ==== Experimental binary emitter ==== */
1938 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1939 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1940 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1942 static void build_reg_map(void)
1944 reg_gp_map[REG_GP_EAX] = 0x0;
1945 reg_gp_map[REG_GP_ECX] = 0x1;
1946 reg_gp_map[REG_GP_EDX] = 0x2;
1947 reg_gp_map[REG_GP_EBX] = 0x3;
1948 reg_gp_map[REG_GP_ESP] = 0x4;
1949 reg_gp_map[REG_GP_EBP] = 0x5;
1950 reg_gp_map[REG_GP_ESI] = 0x6;
1951 reg_gp_map[REG_GP_EDI] = 0x7;
1954 /** Returns the encoding for a pnc field. */
1955 static unsigned char pnc2cc(ia32_condition_code_t cc)
1960 /** Sign extension bit values for binops */
1962 UNSIGNED_IMM = 0, /**< unsigned immediate */
1963 SIGNEXT_IMM = 2, /**< sign extended immediate */
1966 /** The mod encoding of the ModR/M */
1968 MOD_IND = 0x00, /**< [reg1] */
1969 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1970 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1971 MOD_REG = 0xC0 /**< reg1 */
1974 /** create R/M encoding for ModR/M */
1975 #define ENC_RM(x) (x)
1976 /** create REG encoding for ModR/M */
1977 #define ENC_REG(x) ((x) << 3)
1979 /** create encoding for a SIB byte */
1980 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1982 /* Node: The following routines are supposed to append bytes, words, dwords
1983 to the output stream.
1984 Currently the implementation is stupid in that it still creates output
1985 for an "assembler" in the form of .byte, .long
1986 We will change this when enough infrastructure is there to create complete
1987 machine code in memory/object files */
1989 static void bemit8(const unsigned char byte)
1991 be_emit_irprintf("\t.byte 0x%x\n", byte);
1992 be_emit_write_line();
1995 static void bemit16(const unsigned short u16)
1997 be_emit_irprintf("\t.word 0x%x\n", u16);
1998 be_emit_write_line();
2001 static void bemit32(const unsigned u32)
2003 be_emit_irprintf("\t.long 0x%x\n", u32);
2004 be_emit_write_line();
2008 * Emit address of an entity. If @p is_relative is true then a relative
2009 * offset from behind the address to the entity is created.
2011 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2014 if (entity == NULL) {
2019 /* the final version should remember the position in the bytestream
2020 and patch it with the correct address at linktime... */
2021 be_emit_cstring("\t.long ");
2024 be_gas_emit_entity(entity);
2026 if (get_entity_owner(entity) == get_tls_type()) {
2027 if (get_entity_visibility(entity) == ir_visibility_external) {
2028 be_emit_cstring("@INDNTPOFF");
2030 be_emit_cstring("@NTPOFF");
2035 be_emit_cstring("-.");
2040 be_emit_irprintf("%+d", offset);
2043 be_emit_write_line();
2046 static void bemit_jmp_destination(const ir_node *dest_block)
2048 be_emit_cstring("\t.long ");
2049 be_gas_emit_block_name(dest_block);
2050 be_emit_cstring(" - . - 4\n");
2051 be_emit_write_line();
2054 /* end emit routines, all emitters following here should only use the functions
2057 typedef enum reg_modifier {
2062 /** Create a ModR/M byte for src1,src2 registers */
2063 static void bemit_modrr(const arch_register_t *src1,
2064 const arch_register_t *src2)
2066 unsigned char modrm = MOD_REG;
2067 modrm |= ENC_RM(reg_gp_map[src1->index]);
2068 modrm |= ENC_REG(reg_gp_map[src2->index]);
2072 /** Create a ModR/M8 byte for src1,src2 registers */
2073 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2074 reg_modifier_t high_part2, const arch_register_t *src2)
2076 unsigned char modrm = MOD_REG;
2077 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2078 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2082 /** Create a ModR/M byte for one register and extension */
2083 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2085 unsigned char modrm = MOD_REG;
2087 modrm |= ENC_RM(reg_gp_map[reg->index]);
2088 modrm |= ENC_REG(ext);
2092 /** Create a ModR/M8 byte for one register */
2093 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2095 unsigned char modrm = MOD_REG;
2096 assert(reg_gp_map[reg->index] < 4);
2097 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2103 * Calculate the size of an signed immediate in bytes.
2105 * @param offset an offset
2107 static unsigned get_signed_imm_size(int offset)
2109 if (-128 <= offset && offset < 128) {
2111 } else if (-32768 <= offset && offset < 32768) {
2119 * Emit an address mode.
2121 * @param reg content of the reg field: either a register index or an opcode extension
2122 * @param node the node
2124 static void bemit_mod_am(unsigned reg, const ir_node *node)
2126 ir_entity *ent = get_ia32_am_sc(node);
2127 int offs = get_ia32_am_offs_int(node);
2128 ir_node *base = get_irn_n(node, n_ia32_base);
2129 int has_base = !is_ia32_NoReg_GP(base);
2130 ir_node *idx = get_irn_n(node, n_ia32_index);
2131 int has_index = !is_ia32_NoReg_GP(idx);
2134 unsigned emitoffs = 0;
2135 bool emitsib = false;
2138 /* set the mod part depending on displacement */
2140 modrm |= MOD_IND_WORD_OFS;
2142 } else if (offs == 0) {
2145 } else if (-128 <= offs && offs < 128) {
2146 modrm |= MOD_IND_BYTE_OFS;
2149 modrm |= MOD_IND_WORD_OFS;
2154 const arch_register_t *base_reg = arch_get_irn_register(base);
2155 base_enc = reg_gp_map[base_reg->index];
2157 /* Use the EBP encoding + MOD_IND if NO base register. There is
2158 * always a 32bit offset present in this case. */
2164 /* Determine if we need a SIB byte. */
2166 const arch_register_t *reg_index = arch_get_irn_register(idx);
2167 int scale = get_ia32_am_scale(node);
2169 /* R/M set to ESP means SIB in 32bit mode. */
2170 modrm |= ENC_RM(0x04);
2171 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2173 } else if (base_enc == 0x04) {
2174 /* for the above reason we are forced to emit a SIB when base is ESP.
2175 * Only the base is used, index must be ESP too, which means no index.
2177 modrm |= ENC_RM(0x04);
2178 sib = ENC_SIB(0, 0x04, 0x04);
2181 modrm |= ENC_RM(base_enc);
2184 /* We are forced to emit an 8bit offset as EBP base without offset is a
2185 * special case for SIB without base register. */
2186 if (base_enc == 0x05 && emitoffs == 0) {
2187 modrm |= MOD_IND_BYTE_OFS;
2191 modrm |= ENC_REG(reg);
2197 /* emit displacement */
2198 if (emitoffs == 8) {
2199 bemit8((unsigned) offs);
2200 } else if (emitoffs == 32) {
2201 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2206 * Emit a binop with a immediate operand.
2208 * @param node the node to emit
2209 * @param opcode_eax the opcode for the op eax, imm variant
2210 * @param opcode the opcode for the reg, imm variant
2211 * @param ruval the opcode extension for opcode
2213 static void bemit_binop_with_imm(
2214 const ir_node *node,
2215 unsigned char opcode_ax,
2216 unsigned char opcode, unsigned char ruval)
2218 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2219 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2220 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2223 /* Some instructions (test) have no short form with 32bit value + 8bit
2225 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2228 /* check for sign extension */
2229 size = get_signed_imm_size(attr->offset);
2234 bemit8(opcode | SIGNEXT_IMM);
2235 /* cmp has this special mode */
2236 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2237 bemit_mod_am(ruval, node);
2239 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2240 bemit_modru(reg, ruval);
2242 bemit8((unsigned char)attr->offset);
2246 /* check for eax variant: this variant is shorter for 32bit immediates only */
2247 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2249 bemit_mod_am(ruval, node);
2251 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2252 if (reg->index == REG_GP_EAX) {
2256 bemit_modru(reg, ruval);
2259 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2262 panic("invalid imm size?!?");
2268 static void bemit_binop_2(const ir_node *node, unsigned code)
2270 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2272 if (get_ia32_op_type(node) == ia32_Normal) {
2273 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2274 bemit_modrr(op2, out);
2276 bemit_mod_am(reg_gp_map[out->index], node);
2283 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2285 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2286 if (is_ia32_Immediate(right)) {
2287 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2289 bemit_binop_2(node, opcodes[0]);
2296 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2299 if (get_ia32_op_type(node) == ia32_Normal) {
2300 const arch_register_t *in = arch_get_irn_register_in(node, input);
2301 bemit_modru(in, ext);
2303 bemit_mod_am(ext, node);
2307 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2309 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2310 bemit_unop(node, code, reg_gp_map[out->index], input);
2313 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2315 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2318 bemit8(size == 8 ? code : code + 1);
2319 bemit_mod_am(ext, node);
2322 static void bemit_immediate(const ir_node *node, bool relative)
2324 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2325 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2328 static void bemit_copy(const ir_node *copy)
2330 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2331 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2335 /* copies of vf nodes aren't real... */
2336 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2339 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2341 bemit_modrr(in, out);
2344 static void bemit_perm(const ir_node *node)
2346 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2347 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2348 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2350 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2352 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2353 if (in0->index == REG_GP_EAX) {
2354 bemit8(0x90 + reg_gp_map[in1->index]);
2355 } else if (in1->index == REG_GP_EAX) {
2356 bemit8(0x90 + reg_gp_map[in0->index]);
2359 bemit_modrr(in0, in1);
2361 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2362 panic("unimplemented"); // TODO implement
2363 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2364 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2365 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2366 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2368 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2371 panic("unexpected register class in be_Perm (%+F)", node);
2375 static void bemit_xor0(const ir_node *node)
2377 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2379 bemit_modrr(out, out);
2382 static void bemit_mov_const(const ir_node *node)
2384 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2385 bemit8(0xB8 + reg_gp_map[out->index]);
2386 bemit_immediate(node, false);
2390 * Creates a function for a Binop with 3 possible encodings.
2392 #define BINOP(op, op0, op1, op2, op2_ext) \
2393 static void bemit_ ## op(const ir_node *node) { \
2394 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2395 bemit_binop(node, op ## _codes); \
2398 /* insn def eax,imm imm */
2399 BINOP(add, 0x03, 0x05, 0x81, 0)
2400 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2401 BINOP(adc, 0x13, 0x15, 0x81, 2)
2402 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2403 BINOP(and, 0x23, 0x25, 0x81, 4)
2404 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2405 BINOP(xor, 0x33, 0x35, 0x81, 6)
2406 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2408 #define BINOPMEM(op, ext) \
2409 static void bemit_##op(const ir_node *node) \
2412 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2415 val = get_irn_n(node, n_ia32_unary_op); \
2416 if (is_ia32_Immediate(val)) { \
2417 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2418 int offset = attr->offset; \
2419 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2421 bemit_mod_am(ext, node); \
2425 bemit_mod_am(ext, node); \
2429 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2433 bemit8(ext << 3 | 1); \
2434 bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
2438 static void bemit_##op##8bit(const ir_node *node) \
2440 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2441 if (is_ia32_Immediate(val)) { \
2443 bemit_mod_am(ext, node); \
2444 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2447 bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
2459 * Creates a function for an Unop with code /ext encoding.
2461 #define UNOP(op, code, ext, input) \
2462 static void bemit_ ## op(const ir_node *node) { \
2463 bemit_unop(node, code, ext, input); \
2466 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2467 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2468 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2469 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2470 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2471 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2473 /* TODO: am support for IJmp */
2474 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2476 #define SHIFT(op, ext) \
2477 static void bemit_##op(const ir_node *node) \
2479 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2480 ir_node *count = get_irn_n(node, 1); \
2481 if (is_ia32_Immediate(count)) { \
2482 int offset = get_ia32_immediate_attr_const(count)->offset; \
2483 if (offset == 1) { \
2485 bemit_modru(out, ext); \
2488 bemit_modru(out, ext); \
2493 bemit_modru(out, ext); \
2497 static void bemit_##op##mem(const ir_node *node) \
2500 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2503 count = get_irn_n(node, 1); \
2504 if (is_ia32_Immediate(count)) { \
2505 int offset = get_ia32_immediate_attr_const(count)->offset; \
2506 if (offset == 1) { \
2507 bemit8(size == 8 ? 0xD0 : 0xD1); \
2508 bemit_mod_am(ext, node); \
2510 bemit8(size == 8 ? 0xC0 : 0xC1); \
2511 bemit_mod_am(ext, node); \
2515 bemit8(size == 8 ? 0xD2 : 0xD3); \
2516 bemit_mod_am(ext, node); \
2526 static void bemit_shld(const ir_node *node)
2528 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2529 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2530 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2532 if (is_ia32_Immediate(count)) {
2534 bemit_modrr(out, in);
2535 bemit8(get_ia32_immediate_attr_const(count)->offset);
2538 bemit_modrr(out, in);
2542 static void bemit_shrd(const ir_node *node)
2544 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2545 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2546 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2548 if (is_ia32_Immediate(count)) {
2550 bemit_modrr(out, in);
2551 bemit8(get_ia32_immediate_attr_const(count)->offset);
2554 bemit_modrr(out, in);
2559 * binary emitter for setcc.
2561 static void bemit_setcc(const ir_node *node)
2563 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2565 ia32_condition_code_t cc = get_ia32_condcode(node);
2566 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2567 if (cc & ia32_cc_float_parity_cases) {
2568 if (cc & ia32_cc_negated) {
2571 bemit8(0x90 | pnc2cc(cc));
2572 bemit_modrm8(REG_LOW, dreg);
2577 bemit_modrm8(REG_HIGH, dreg);
2579 /* orb %>dreg, %<dreg */
2581 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2585 bemit8(0x90 | pnc2cc(cc));
2586 bemit_modrm8(REG_LOW, dreg);
2591 bemit_modrm8(REG_HIGH, dreg);
2593 /* andb %>dreg, %<dreg */
2595 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2600 bemit8(0x90 | pnc2cc(cc));
2601 bemit_modrm8(REG_LOW, dreg);
2605 static void bemit_cmovcc(const ir_node *node)
2607 const ia32_attr_t *attr = get_ia32_attr_const(node);
2608 int ins_permuted = attr->data.ins_permuted;
2609 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2610 ia32_condition_code_t cc = get_ia32_condcode(node);
2611 const arch_register_t *in_true;
2612 const arch_register_t *in_false;
2614 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2616 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2617 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2619 /* should be same constraint fullfilled? */
2620 if (out == in_false) {
2621 /* yes -> nothing to do */
2622 } else if (out == in_true) {
2623 assert(get_ia32_op_type(node) == ia32_Normal);
2624 ins_permuted = !ins_permuted;
2628 bemit8(0x8B); // mov %in_false, %out
2629 bemit_modrr(in_false, out);
2633 cc = ia32_negate_condition_code(cc);
2635 if (cc & ia32_cc_float_parity_cases)
2636 panic("cmov can't handle parity float cases");
2639 bemit8(0x40 | pnc2cc(cc));
2640 if (get_ia32_op_type(node) == ia32_Normal) {
2641 bemit_modrr(in_true, out);
2643 bemit_mod_am(reg_gp_map[out->index], node);
2647 static void bemit_cmp(const ir_node *node)
2649 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2655 right = get_irn_n(node, n_ia32_binary_right);
2656 if (is_ia32_Immediate(right)) {
2657 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2658 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2659 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2662 if (attr->symconst != NULL) {
2665 /* check for sign extension */
2666 size = get_signed_imm_size(attr->offset);
2671 bemit8(0x81 | SIGNEXT_IMM);
2672 /* cmp has this special mode */
2673 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2674 bemit_mod_am(7, node);
2676 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2677 bemit_modru(reg, 7);
2679 bemit8((unsigned char)attr->offset);
2683 /* check for eax variant: this variant is shorter for 32bit immediates only */
2684 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2686 bemit_mod_am(7, node);
2688 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2689 if (reg->index == REG_GP_EAX) {
2693 bemit_modru(reg, 7);
2696 if (ls_size == 16) {
2697 bemit16(attr->offset);
2699 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2703 panic("invalid imm size?!?");
2705 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2707 if (get_ia32_op_type(node) == ia32_Normal) {
2708 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2709 bemit_modrr(op2, out);
2711 bemit_mod_am(reg_gp_map[out->index], node);
2716 static void bemit_cmp8bit(const ir_node *node)
2718 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2719 if (is_ia32_Immediate(right)) {
2720 if (get_ia32_op_type(node) == ia32_Normal) {
2721 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2722 if (out->index == REG_GP_EAX) {
2726 bemit_modru(out, 7);
2730 bemit_mod_am(7, node);
2732 bemit8(get_ia32_immediate_attr_const(right)->offset);
2734 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2736 if (get_ia32_op_type(node) == ia32_Normal) {
2737 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2738 bemit_modrr(out, in);
2740 bemit_mod_am(reg_gp_map[out->index], node);
2745 static void bemit_test8bit(const ir_node *node)
2747 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2748 if (is_ia32_Immediate(right)) {
2749 if (get_ia32_op_type(node) == ia32_Normal) {
2750 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2751 if (out->index == REG_GP_EAX) {
2755 bemit_modru(out, 0);
2759 bemit_mod_am(0, node);
2761 bemit8(get_ia32_immediate_attr_const(right)->offset);
2763 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2765 if (get_ia32_op_type(node) == ia32_Normal) {
2766 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2767 bemit_modrr(out, in);
2769 bemit_mod_am(reg_gp_map[out->index], node);
2774 static void bemit_imul(const ir_node *node)
2776 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2777 /* Do we need the immediate form? */
2778 if (is_ia32_Immediate(right)) {
2779 int imm = get_ia32_immediate_attr_const(right)->offset;
2780 if (get_signed_imm_size(imm) == 1) {
2781 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2784 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2789 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2793 static void bemit_dec(const ir_node *node)
2795 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2796 bemit8(0x48 + reg_gp_map[out->index]);
2799 static void bemit_inc(const ir_node *node)
2801 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2802 bemit8(0x40 + reg_gp_map[out->index]);
2805 #define UNOPMEM(op, code, ext) \
2806 static void bemit_##op(const ir_node *node) \
2808 bemit_unop_mem(node, code, ext); \
2811 UNOPMEM(notmem, 0xF6, 2)
2812 UNOPMEM(negmem, 0xF6, 3)
2813 UNOPMEM(incmem, 0xFE, 0)
2814 UNOPMEM(decmem, 0xFE, 1)
2816 static void bemit_ldtls(const ir_node *node)
2818 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2820 bemit8(0x65); // gs:
2821 if (out->index == REG_GP_EAX) {
2822 bemit8(0xA1); // movl 0, %eax
2824 bemit8(0x8B); // movl 0, %reg
2825 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2833 static void bemit_lea(const ir_node *node)
2835 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2837 bemit_mod_am(reg_gp_map[out->index], node);
2840 /* helper function for bemit_minus64bit */
2841 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2843 bemit8(0x8B); // movl %src, %dst
2844 bemit_modrr(src, dst);
2847 /* helper function for bemit_minus64bit */
2848 static void bemit_helper_neg(const arch_register_t *reg)
2850 bemit8(0xF7); // negl %reg
2851 bemit_modru(reg, 3);
2854 /* helper function for bemit_minus64bit */
2855 static void bemit_helper_sbb0(const arch_register_t *reg)
2857 bemit8(0x83); // sbbl $0, %reg
2858 bemit_modru(reg, 3);
2862 /* helper function for bemit_minus64bit */
2863 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2865 bemit8(0x1B); // sbbl %src, %dst
2866 bemit_modrr(src, dst);
2869 /* helper function for bemit_minus64bit */
2870 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2872 if (src->index == REG_GP_EAX) {
2873 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2874 } else if (dst->index == REG_GP_EAX) {
2875 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2877 bemit8(0x87); // xchgl %src, %dst
2878 bemit_modrr(src, dst);
2882 /* helper function for bemit_minus64bit */
2883 static void bemit_helper_zero(const arch_register_t *reg)
2885 bemit8(0x33); // xorl %reg, %reg
2886 bemit_modrr(reg, reg);
2889 static void bemit_minus64bit(const ir_node *node)
2891 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2892 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2893 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2894 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2896 if (out_lo == in_lo) {
2897 if (out_hi != in_hi) {
2898 /* a -> a, b -> d */
2901 /* a -> a, b -> b */
2904 } else if (out_lo == in_hi) {
2905 if (out_hi == in_lo) {
2906 /* a -> b, b -> a */
2907 bemit_helper_xchg(in_lo, in_hi);
2910 /* a -> b, b -> d */
2911 bemit_helper_mov(in_hi, out_hi);
2912 bemit_helper_mov(in_lo, out_lo);
2916 if (out_hi == in_lo) {
2917 /* a -> c, b -> a */
2918 bemit_helper_mov(in_lo, out_lo);
2920 } else if (out_hi == in_hi) {
2921 /* a -> c, b -> b */
2922 bemit_helper_mov(in_lo, out_lo);
2925 /* a -> c, b -> d */
2926 bemit_helper_mov(in_lo, out_lo);
2932 bemit_helper_neg( out_hi);
2933 bemit_helper_neg( out_lo);
2934 bemit_helper_sbb0(out_hi);
2938 bemit_helper_zero(out_hi);
2939 bemit_helper_neg( out_lo);
2940 bemit_helper_sbb( in_hi, out_hi);
2944 * Emit a single opcode.
2946 #define EMIT_SINGLEOP(op, code) \
2947 static void bemit_ ## op(const ir_node *node) { \
2952 //EMIT_SINGLEOP(daa, 0x27)
2953 //EMIT_SINGLEOP(das, 0x2F)
2954 //EMIT_SINGLEOP(aaa, 0x37)
2955 //EMIT_SINGLEOP(aas, 0x3F)
2956 //EMIT_SINGLEOP(nop, 0x90)
2957 EMIT_SINGLEOP(cwtl, 0x98)
2958 EMIT_SINGLEOP(cltd, 0x99)
2959 //EMIT_SINGLEOP(fwait, 0x9B)
2960 EMIT_SINGLEOP(sahf, 0x9E)
2961 //EMIT_SINGLEOP(popf, 0x9D)
2962 EMIT_SINGLEOP(leave, 0xC9)
2963 EMIT_SINGLEOP(int3, 0xCC)
2964 //EMIT_SINGLEOP(iret, 0xCF)
2965 //EMIT_SINGLEOP(xlat, 0xD7)
2966 //EMIT_SINGLEOP(lock, 0xF0)
2967 EMIT_SINGLEOP(rep, 0xF3)
2968 //EMIT_SINGLEOP(halt, 0xF4)
2969 EMIT_SINGLEOP(cmc, 0xF5)
2970 EMIT_SINGLEOP(stc, 0xF9)
2971 //EMIT_SINGLEOP(cli, 0xFA)
2972 //EMIT_SINGLEOP(sti, 0xFB)
2973 //EMIT_SINGLEOP(std, 0xFD)
2976 * Emits a MOV out, [MEM].
2978 static void bemit_load(const ir_node *node)
2980 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2982 if (out->index == REG_GP_EAX) {
2983 ir_node *base = get_irn_n(node, n_ia32_base);
2984 int has_base = !is_ia32_NoReg_GP(base);
2985 ir_node *idx = get_irn_n(node, n_ia32_index);
2986 int has_index = !is_ia32_NoReg_GP(idx);
2987 if (!has_base && !has_index) {
2988 ir_entity *ent = get_ia32_am_sc(node);
2989 int offs = get_ia32_am_offs_int(node);
2990 /* load from constant address to EAX can be encoded
2993 bemit_entity(ent, 0, offs, false);
2998 bemit_mod_am(reg_gp_map[out->index], node);
3002 * Emits a MOV [mem], in.
3004 static void bemit_store(const ir_node *node)
3006 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3007 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3009 if (is_ia32_Immediate(value)) {
3012 bemit_mod_am(0, node);
3013 bemit8(get_ia32_immediate_attr_const(value)->offset);
3014 } else if (size == 16) {
3017 bemit_mod_am(0, node);
3018 bemit16(get_ia32_immediate_attr_const(value)->offset);
3021 bemit_mod_am(0, node);
3022 bemit_immediate(value, false);
3025 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
3027 if (in->index == REG_GP_EAX) {
3028 ir_node *base = get_irn_n(node, n_ia32_base);
3029 int has_base = !is_ia32_NoReg_GP(base);
3030 ir_node *idx = get_irn_n(node, n_ia32_index);
3031 int has_index = !is_ia32_NoReg_GP(idx);
3032 if (!has_base && !has_index) {
3033 ir_entity *ent = get_ia32_am_sc(node);
3034 int offs = get_ia32_am_offs_int(node);
3035 /* store to constant address from EAX can be encoded as
3036 * 0xA2/0xA3 [offset]*/
3044 bemit_entity(ent, 0, offs, false);
3056 bemit_mod_am(reg_gp_map[in->index], node);
3060 static void bemit_conv_i2i(const ir_node *node)
3062 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3071 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3072 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3073 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3079 static void bemit_push(const ir_node *node)
3081 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3083 if (is_ia32_Immediate(value)) {
3084 const ia32_immediate_attr_t *attr
3085 = get_ia32_immediate_attr_const(value);
3086 unsigned size = get_signed_imm_size(attr->offset);
3092 bemit8((unsigned char)attr->offset);
3097 bemit_immediate(value, false);
3100 } else if (is_ia32_NoReg_GP(value)) {
3102 bemit_mod_am(6, node);
3104 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3105 bemit8(0x50 + reg_gp_map[reg->index]);
3112 static void bemit_pop(const ir_node *node)
3114 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3115 bemit8(0x58 + reg_gp_map[reg->index]);
3118 static void bemit_popmem(const ir_node *node)
3121 bemit_mod_am(0, node);
3124 static void bemit_call(const ir_node *node)
3126 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3128 if (is_ia32_Immediate(proc)) {
3130 bemit_immediate(proc, true);
3132 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3136 static void bemit_jmp(const ir_node *dest_block)
3139 bemit_jmp_destination(dest_block);
3142 static void bemit_jump(const ir_node *node)
3144 if (can_be_fallthrough(node))
3147 bemit_jmp(get_cfop_target_block(node));
3150 static void bemit_jcc(int pnc, const ir_node *dest_block)
3152 unsigned char cc = pnc2cc(pnc);
3155 bemit_jmp_destination(dest_block);
3158 static void bemit_jp(bool odd, const ir_node *dest_block)
3162 bemit_jmp_destination(dest_block);
3165 static void bemit_ia32_jcc(const ir_node *node)
3167 ia32_condition_code_t cc = get_ia32_condcode(node);
3168 const ir_node *proj_true;
3169 const ir_node *proj_false;
3170 const ir_node *dest_true;
3171 const ir_node *dest_false;
3173 cc = determine_final_cc(node, 0, cc);
3175 /* get both Projs */
3176 proj_true = get_proj(node, pn_ia32_Jcc_true);
3177 assert(proj_true && "Jcc without true Proj");
3179 proj_false = get_proj(node, pn_ia32_Jcc_false);
3180 assert(proj_false && "Jcc without false Proj");
3182 if (can_be_fallthrough(proj_true)) {
3183 /* exchange both proj's so the second one can be omitted */
3184 const ir_node *t = proj_true;
3186 proj_true = proj_false;
3188 cc = ia32_negate_condition_code(cc);
3191 dest_true = get_cfop_target_block(proj_true);
3192 dest_false = get_cfop_target_block(proj_false);
3194 if (cc & ia32_cc_float_parity_cases) {
3195 /* Some floating point comparisons require a test of the parity flag,
3196 * which indicates that the result is unordered */
3197 if (cc & ia32_cc_negated) {
3198 bemit_jp(false, dest_true);
3200 /* we need a local label if the false proj is a fallthrough
3201 * as the falseblock might have no label emitted then */
3202 if (can_be_fallthrough(proj_false)) {
3204 bemit8(0x06); // jp + 6
3206 bemit_jp(false, dest_false);
3210 bemit_jcc(cc, dest_true);
3212 /* the second Proj might be a fallthrough */
3213 if (can_be_fallthrough(proj_false)) {
3214 /* it's a fallthrough */
3216 bemit_jmp(dest_false);
3220 static void bemit_switchjmp(const ir_node *node)
3222 ir_entity *jump_table = get_ia32_am_sc(node);
3223 const ir_switch_table *table = get_ia32_switch_table(node);
3225 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3226 bemit_mod_am(0x05, node);
3228 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3234 static void bemit_return(const ir_node *node)
3236 unsigned pop = be_Return_get_pop(node);
3237 if (pop > 0 || be_Return_get_emit_pop(node)) {
3239 assert(pop <= 0xffff);
3246 static void bemit_subsp(const ir_node *node)
3248 const arch_register_t *out;
3251 /* mov %esp, %out */
3253 out = arch_get_irn_register_out(node, 1);
3254 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3257 static void bemit_incsp(const ir_node *node)
3260 const arch_register_t *reg;
3264 offs = be_get_IncSP_offset(node);
3275 size = get_signed_imm_size(offs);
3276 bemit8(size == 1 ? 0x83 : 0x81);
3278 reg = arch_get_irn_register_out(node, 0);
3279 bemit_modru(reg, ext);
3288 static void bemit_copybi(const ir_node *node)
3290 unsigned size = get_ia32_copyb_size(node);
3292 bemit8(0xA4); // movsb
3295 bemit8(0xA5); // movsw
3299 bemit8(0xA5); // movsl
3303 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3305 if (get_ia32_op_type(node) == ia32_Normal) {
3306 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3307 const arch_register_t *in1 = x87_attr->x87[0];
3308 const arch_register_t *in = x87_attr->x87[1];
3309 const arch_register_t *out = x87_attr->x87[2];
3313 } else if (out == in) {
3317 if (out->index == 0) {
3319 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3322 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3325 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3330 bemit_mod_am(code, node);
3334 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3336 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3337 const arch_register_t *out = x87_attr->x87[2];
3339 bemit8(code + out->index);
3342 static void bemit_fabs(const ir_node *node)
3350 static void bemit_fadd(const ir_node *node)
3352 bemit_fbinop(node, 0, 0);
3355 static void bemit_faddp(const ir_node *node)
3357 bemit_fbinopp(node, 0xC0);
3360 static void bemit_fchs(const ir_node *node)
3368 static void bemit_fdiv(const ir_node *node)
3370 bemit_fbinop(node, 6, 7);
3373 static void bemit_fdivp(const ir_node *node)
3375 bemit_fbinopp(node, 0xF8);
3378 static void bemit_fdivr(const ir_node *node)
3380 bemit_fbinop(node, 7, 6);
3383 static void bemit_fdivrp(const ir_node *node)
3385 bemit_fbinopp(node, 0xF0);
3388 static void bemit_fild(const ir_node *node)
3390 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3392 bemit8(0xDF); // filds
3393 bemit_mod_am(0, node);
3397 bemit8(0xDB); // fildl
3398 bemit_mod_am(0, node);
3402 bemit8(0xDF); // fildll
3403 bemit_mod_am(5, node);
3407 panic("invalid mode size");
3411 static void bemit_fist(const ir_node *node)
3413 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3415 bemit8(0xDF); // fists
3419 bemit8(0xDB); // fistl
3423 panic("invalid mode size");
3425 bemit_mod_am(2, node);
3428 static void bemit_fistp(const ir_node *node)
3430 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3432 bemit8(0xDF); // fistps
3433 bemit_mod_am(3, node);
3437 bemit8(0xDB); // fistpl
3438 bemit_mod_am(3, node);
3442 bemit8(0xDF); // fistpll
3443 bemit_mod_am(7, node);
3447 panic("invalid mode size");
3451 static void bemit_fld(const ir_node *node)
3453 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3455 bemit8(0xD9); // flds
3456 bemit_mod_am(0, node);
3460 bemit8(0xDD); // fldl
3461 bemit_mod_am(0, node);
3466 bemit8(0xDB); // fldt
3467 bemit_mod_am(5, node);
3471 panic("invalid mode size");
3475 static void bemit_fld1(const ir_node *node)
3479 bemit8(0xE8); // fld1
3482 static void bemit_fldcw(const ir_node *node)
3484 bemit8(0xD9); // fldcw
3485 bemit_mod_am(5, node);
3488 static void bemit_fldz(const ir_node *node)
3492 bemit8(0xEE); // fldz
3495 static void bemit_fmul(const ir_node *node)
3497 bemit_fbinop(node, 1, 1);
3500 static void bemit_fmulp(const ir_node *node)
3502 bemit_fbinopp(node, 0xC8);
3505 static void bemit_fpop(const ir_node *node)
3507 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3509 bemit8(0xD8 + attr->x87[0]->index);
3512 static void bemit_fpush(const ir_node *node)
3514 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3516 bemit8(0xC0 + attr->x87[0]->index);
3519 static void bemit_fpushcopy(const ir_node *node)
3521 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3523 bemit8(0xC0 + attr->x87[0]->index);
3526 static void bemit_fst(const ir_node *node)
3528 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3530 bemit8(0xD9); // fsts
3534 bemit8(0xDD); // fstl
3538 panic("invalid mode size");
3540 bemit_mod_am(2, node);
3543 static void bemit_fstp(const ir_node *node)
3545 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3547 bemit8(0xD9); // fstps
3548 bemit_mod_am(3, node);
3552 bemit8(0xDD); // fstpl
3553 bemit_mod_am(3, node);
3558 bemit8(0xDB); // fstpt
3559 bemit_mod_am(7, node);
3563 panic("invalid mode size");
3567 static void bemit_fsub(const ir_node *node)
3569 bemit_fbinop(node, 4, 5);
3572 static void bemit_fsubp(const ir_node *node)
3574 bemit_fbinopp(node, 0xE8);
3577 static void bemit_fsubr(const ir_node *node)
3579 bemit_fbinop(node, 5, 4);
3582 static void bemit_fsubrp(const ir_node *node)
3584 bemit_fbinopp(node, 0xE0);
3587 static void bemit_fnstcw(const ir_node *node)
3589 bemit8(0xD9); // fnstcw
3590 bemit_mod_am(7, node);
3593 static void bemit_fnstsw(void)
3595 bemit8(0xDF); // fnstsw %ax
3599 static void bemit_ftstfnstsw(const ir_node *node)
3603 bemit8(0xD9); // ftst
3608 static void bemit_fucomi(const ir_node *node)
3610 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3611 bemit8(0xDB); // fucomi
3612 bemit8(0xE8 + attr->x87[1]->index);
3615 static void bemit_fucomip(const ir_node *node)
3617 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3618 bemit8(0xDF); // fucomip
3619 bemit8(0xE8 + attr->x87[1]->index);
3622 static void bemit_fucomfnstsw(const ir_node *node)
3624 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3625 bemit8(0xDD); // fucom
3626 bemit8(0xE0 + attr->x87[1]->index);
3630 static void bemit_fucompfnstsw(const ir_node *node)
3632 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3633 bemit8(0xDD); // fucomp
3634 bemit8(0xE8 + attr->x87[1]->index);
3638 static void bemit_fucomppfnstsw(const ir_node *node)
3642 bemit8(0xDA); // fucompp
3647 static void bemit_fxch(const ir_node *node)
3649 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3651 bemit8(0xC8 + attr->x87[0]->index);
3655 * The type of a emitter function.
3657 typedef void (*emit_func) (const ir_node *);
3660 * Set a node emitter. Make it a bit more type safe.
3662 static void register_emitter(ir_op *op, emit_func func)
3664 op->ops.generic = (op_func) func;
3667 static void ia32_register_binary_emitters(void)
3669 /* first clear the generic function pointer for all ops */
3670 ir_clear_opcodes_generic_func();
3672 /* benode emitter */
3673 register_emitter(op_be_Copy, bemit_copy);
3674 register_emitter(op_be_CopyKeep, bemit_copy);
3675 register_emitter(op_be_IncSP, bemit_incsp);
3676 register_emitter(op_be_Perm, bemit_perm);
3677 register_emitter(op_be_Return, bemit_return);
3678 register_emitter(op_ia32_Adc, bemit_adc);
3679 register_emitter(op_ia32_Add, bemit_add);
3680 register_emitter(op_ia32_AddMem, bemit_addmem);
3681 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3682 register_emitter(op_ia32_And, bemit_and);
3683 register_emitter(op_ia32_AndMem, bemit_andmem);
3684 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3685 register_emitter(op_ia32_Breakpoint, bemit_int3);
3686 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3687 register_emitter(op_ia32_Call, bemit_call);
3688 register_emitter(op_ia32_Cltd, bemit_cltd);
3689 register_emitter(op_ia32_Cmc, bemit_cmc);
3690 register_emitter(op_ia32_Cmp, bemit_cmp);
3691 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3692 register_emitter(op_ia32_Const, bemit_mov_const);
3693 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3694 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3695 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3696 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3697 register_emitter(op_ia32_Dec, bemit_dec);
3698 register_emitter(op_ia32_DecMem, bemit_decmem);
3699 register_emitter(op_ia32_Div, bemit_div);
3700 register_emitter(op_ia32_FldCW, bemit_fldcw);
3701 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3702 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3703 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3704 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3705 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3706 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3707 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3708 register_emitter(op_ia32_IDiv, bemit_idiv);
3709 register_emitter(op_ia32_IJmp, bemit_ijmp);
3710 register_emitter(op_ia32_IMul, bemit_imul);
3711 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3712 register_emitter(op_ia32_Inc, bemit_inc);
3713 register_emitter(op_ia32_IncMem, bemit_incmem);
3714 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3715 register_emitter(op_ia32_Jmp, bemit_jump);
3716 register_emitter(op_ia32_LdTls, bemit_ldtls);
3717 register_emitter(op_ia32_Lea, bemit_lea);
3718 register_emitter(op_ia32_Leave, bemit_leave);
3719 register_emitter(op_ia32_Load, bemit_load);
3720 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3721 register_emitter(op_ia32_Mul, bemit_mul);
3722 register_emitter(op_ia32_Neg, bemit_neg);
3723 register_emitter(op_ia32_NegMem, bemit_negmem);
3724 register_emitter(op_ia32_Not, bemit_not);
3725 register_emitter(op_ia32_NotMem, bemit_notmem);
3726 register_emitter(op_ia32_Or, bemit_or);
3727 register_emitter(op_ia32_OrMem, bemit_ormem);
3728 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3729 register_emitter(op_ia32_Pop, bemit_pop);
3730 register_emitter(op_ia32_PopEbp, bemit_pop);
3731 register_emitter(op_ia32_PopMem, bemit_popmem);
3732 register_emitter(op_ia32_Push, bemit_push);
3733 register_emitter(op_ia32_RepPrefix, bemit_rep);
3734 register_emitter(op_ia32_Rol, bemit_rol);
3735 register_emitter(op_ia32_RolMem, bemit_rolmem);
3736 register_emitter(op_ia32_Ror, bemit_ror);
3737 register_emitter(op_ia32_RorMem, bemit_rormem);
3738 register_emitter(op_ia32_Sahf, bemit_sahf);
3739 register_emitter(op_ia32_Sar, bemit_sar);
3740 register_emitter(op_ia32_SarMem, bemit_sarmem);
3741 register_emitter(op_ia32_Sbb, bemit_sbb);
3742 register_emitter(op_ia32_Setcc, bemit_setcc);
3743 register_emitter(op_ia32_Shl, bemit_shl);
3744 register_emitter(op_ia32_ShlD, bemit_shld);
3745 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3746 register_emitter(op_ia32_Shr, bemit_shr);
3747 register_emitter(op_ia32_ShrD, bemit_shrd);
3748 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3749 register_emitter(op_ia32_Stc, bemit_stc);
3750 register_emitter(op_ia32_Store, bemit_store);
3751 register_emitter(op_ia32_Store8Bit, bemit_store);
3752 register_emitter(op_ia32_Sub, bemit_sub);
3753 register_emitter(op_ia32_SubMem, bemit_submem);
3754 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3755 register_emitter(op_ia32_SubSP, bemit_subsp);
3756 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3757 register_emitter(op_ia32_Test, bemit_test);
3758 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3759 register_emitter(op_ia32_Xor, bemit_xor);
3760 register_emitter(op_ia32_Xor0, bemit_xor0);
3761 register_emitter(op_ia32_XorMem, bemit_xormem);
3762 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3763 register_emitter(op_ia32_fabs, bemit_fabs);
3764 register_emitter(op_ia32_fadd, bemit_fadd);
3765 register_emitter(op_ia32_faddp, bemit_faddp);
3766 register_emitter(op_ia32_fchs, bemit_fchs);
3767 register_emitter(op_ia32_fdiv, bemit_fdiv);
3768 register_emitter(op_ia32_fdivp, bemit_fdivp);
3769 register_emitter(op_ia32_fdivr, bemit_fdivr);
3770 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3771 register_emitter(op_ia32_fild, bemit_fild);
3772 register_emitter(op_ia32_fist, bemit_fist);
3773 register_emitter(op_ia32_fistp, bemit_fistp);
3774 register_emitter(op_ia32_fld, bemit_fld);
3775 register_emitter(op_ia32_fld1, bemit_fld1);
3776 register_emitter(op_ia32_fldz, bemit_fldz);
3777 register_emitter(op_ia32_fmul, bemit_fmul);
3778 register_emitter(op_ia32_fmulp, bemit_fmulp);
3779 register_emitter(op_ia32_fpop, bemit_fpop);
3780 register_emitter(op_ia32_fpush, bemit_fpush);
3781 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3782 register_emitter(op_ia32_fst, bemit_fst);
3783 register_emitter(op_ia32_fstp, bemit_fstp);
3784 register_emitter(op_ia32_fsub, bemit_fsub);
3785 register_emitter(op_ia32_fsubp, bemit_fsubp);
3786 register_emitter(op_ia32_fsubr, bemit_fsubr);
3787 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3788 register_emitter(op_ia32_fxch, bemit_fxch);
3790 /* ignore the following nodes */
3791 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3792 register_emitter(op_be_Keep, emit_Nothing);
3793 register_emitter(op_be_Start, emit_Nothing);
3794 register_emitter(op_Phi, emit_Nothing);
3795 register_emitter(op_Start, emit_Nothing);
3798 static void gen_binary_block(ir_node *block)
3802 ia32_emit_block_header(block);
3804 /* emit the contents of the block */
3805 sched_foreach(block, node) {
3806 ia32_emit_node(node);
3810 void ia32_gen_binary_routine(ir_graph *irg)
3812 ir_entity *entity = get_irg_entity(irg);
3813 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3814 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3815 ir_node **blk_sched = irg_data->blk_sched;
3818 isa = (ia32_isa_t*) arch_env;
3820 ia32_register_binary_emitters();
3822 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
3824 /* we use links to point to target blocks */
3825 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3826 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3828 /* initialize next block links */
3829 n = ARR_LEN(blk_sched);
3830 for (i = 0; i < n; ++i) {
3831 ir_node *block = blk_sched[i];
3832 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3834 set_irn_link(block, prev);
3837 for (i = 0; i < n; ++i) {
3838 ir_node *block = blk_sched[i];
3839 gen_binary_block(block);
3842 be_gas_emit_function_epilog(entity);
3844 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3848 void ia32_init_emitter(void)
3850 lc_opt_entry_t *be_grp;
3851 lc_opt_entry_t *ia32_grp;
3853 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3854 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3856 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3860 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");