2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
68 static const arch_env_t *arch_env;
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
73 * Returns the register at in position pos.
75 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
78 const arch_register_t *reg = NULL;
80 assert(get_irn_arity(irn) > pos && "Invalid IN position");
82 /* The out register of the operator at position pos is the
83 in register we need. */
84 op = get_irn_n(irn, pos);
86 reg = arch_get_irn_register(arch_env, op);
88 assert(reg && "no in register found");
90 if(reg == &ia32_gp_regs[REG_GP_NOREG])
91 panic("trying to emit noreg for %+F input %d", irn, pos);
93 /* in case of unknown register: just return a valid register */
94 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
95 const arch_register_req_t *req;
97 /* ask for the requirements */
98 req = arch_get_register_req(arch_env, irn, pos);
100 if (arch_register_req_is(req, limited)) {
101 /* in case of limited requirements: get the first allowed register */
102 unsigned idx = rbitset_next(req->limited, 0, 1);
103 reg = arch_register_for_index(req->cls, idx);
105 /* otherwise get first register in class */
106 reg = arch_register_for_index(req->cls, 0);
114 * Returns the register at out position pos.
116 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
119 const arch_register_t *reg = NULL;
121 /* 1st case: irn is not of mode_T, so it has only */
122 /* one OUT register -> good */
123 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
124 /* Proj with the corresponding projnum for the register */
126 if (get_irn_mode(irn) != mode_T) {
128 reg = arch_get_irn_register(arch_env, irn);
129 } else if (is_ia32_irn(irn)) {
130 reg = get_ia32_out_reg(irn, pos);
132 const ir_edge_t *edge;
134 foreach_out_edge(irn, edge) {
135 proj = get_edge_src_irn(edge);
136 assert(is_Proj(proj) && "non-Proj from mode_T node");
137 if (get_Proj_proj(proj) == pos) {
138 reg = arch_get_irn_register(arch_env, proj);
144 assert(reg && "no out register found");
149 * Add a number to a prefix. This number will not be used a second time.
151 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
153 static unsigned long id = 0;
154 snprintf(buf, buflen, "%s%lu", prefix, ++id);
158 /*************************************************************
160 * (_) | | / _| | | | |
161 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
162 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
163 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
164 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
167 *************************************************************/
169 static void emit_8bit_register(const arch_register_t *reg)
171 const char *reg_name = arch_register_get_name(reg);
174 be_emit_char(reg_name[1]);
178 static void emit_16bit_register(const arch_register_t *reg)
180 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
183 be_emit_string(reg_name);
186 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
188 const char *reg_name;
191 int size = get_mode_size_bits(mode);
193 emit_8bit_register(reg);
195 } else if(size == 16) {
196 emit_16bit_register(reg);
199 assert(mode_is_float(mode) || size == 32);
203 reg_name = arch_register_get_name(reg);
206 be_emit_string(reg_name);
209 void ia32_emit_source_register(const ir_node *node, int pos)
211 const arch_register_t *reg = get_in_reg(node, pos);
213 emit_register(reg, NULL);
216 static void emit_ia32_Immediate(const ir_node *node);
218 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
220 const arch_register_t *reg;
221 ir_node *in = get_irn_n(node, pos);
222 if(is_ia32_Immediate(in)) {
223 emit_ia32_Immediate(in);
227 reg = get_in_reg(node, pos);
228 emit_8bit_register(reg);
231 void ia32_emit_dest_register(const ir_node *node, int pos)
233 const arch_register_t *reg = get_out_reg(node, pos);
235 emit_register(reg, NULL);
238 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
240 const arch_register_t *reg = get_out_reg(node, pos);
242 emit_register(reg, mode_Bu);
245 void ia32_emit_x87_register(const ir_node *node, int pos)
247 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
251 be_emit_string(attr->x87[pos]->name);
254 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
256 if(mode_is_float(mode)) {
257 switch(get_mode_size_bits(mode)) {
258 case 32: be_emit_char('s'); return;
259 case 64: be_emit_char('l'); return;
260 case 80: be_emit_char('t'); return;
263 assert(mode_is_int(mode) || mode_is_reference(mode));
264 switch(get_mode_size_bits(mode)) {
265 case 64: be_emit_cstring("ll"); return;
266 /* gas docu says q is the suffix but gcc, objdump and icc use
268 case 32: be_emit_char('l'); return;
269 case 16: be_emit_char('w'); return;
270 case 8: be_emit_char('b'); return;
273 panic("Can't output mode_suffix for %+F\n", mode);
276 void ia32_emit_mode_suffix(const ir_node *node)
278 ir_mode *mode = get_ia32_ls_mode(node);
282 ia32_emit_mode_suffix_mode(mode);
285 void ia32_emit_x87_mode_suffix(const ir_node *node)
287 ir_mode *mode = get_ia32_ls_mode(node);
288 assert(mode != NULL);
289 /* we only need to emit the mode on address mode */
290 if(get_ia32_op_type(node) != ia32_Normal)
291 ia32_emit_mode_suffix_mode(mode);
295 char get_xmm_mode_suffix(ir_mode *mode)
297 assert(mode_is_float(mode));
298 switch(get_mode_size_bits(mode)) {
309 void ia32_emit_xmm_mode_suffix(const ir_node *node)
311 ir_mode *mode = get_ia32_ls_mode(node);
312 assert(mode != NULL);
314 be_emit_char(get_xmm_mode_suffix(mode));
317 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
319 ir_mode *mode = get_ia32_ls_mode(node);
320 assert(mode != NULL);
321 be_emit_char(get_xmm_mode_suffix(mode));
324 void ia32_emit_extend_suffix(const ir_mode *mode)
326 if(get_mode_size_bits(mode) == 32)
328 if(mode_is_signed(mode)) {
336 void ia32_emit_function_object(const char *name)
338 switch (be_gas_flavour) {
339 case GAS_FLAVOUR_NORMAL:
340 be_emit_cstring("\t.type\t");
341 be_emit_string(name);
342 be_emit_cstring(", @function\n");
343 be_emit_write_line();
345 case GAS_FLAVOUR_MINGW:
346 be_emit_cstring("\t.def\t");
347 be_emit_string(name);
348 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
349 be_emit_write_line();
357 void ia32_emit_function_size(const char *name)
359 switch (be_gas_flavour) {
360 case GAS_FLAVOUR_NORMAL:
361 be_emit_cstring("\t.size\t");
362 be_emit_string(name);
363 be_emit_cstring(", .-");
364 be_emit_string(name);
366 be_emit_write_line();
374 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
376 ir_node *in = get_irn_n(node, pos);
377 if(is_ia32_Immediate(in)) {
378 emit_ia32_Immediate(in);
380 const ir_mode *mode = get_ia32_ls_mode(node);
381 const arch_register_t *reg = get_in_reg(node, pos);
382 emit_register(reg, mode);
387 * Emits registers and/or address mode of a binary operation.
389 void ia32_emit_binop(const ir_node *node) {
390 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
391 const ir_mode *mode = get_ia32_ls_mode(node);
392 const arch_register_t *reg_left;
394 switch(get_ia32_op_type(node)) {
396 reg_left = get_in_reg(node, n_ia32_binary_left);
397 if(is_ia32_Immediate(right_op)) {
398 emit_ia32_Immediate(right_op);
399 be_emit_cstring(", ");
400 emit_register(reg_left, mode);
403 const arch_register_t *reg_right
404 = get_in_reg(node, n_ia32_binary_right);
405 emit_register(reg_right, mode);
406 be_emit_cstring(", ");
407 emit_register(reg_left, mode);
411 if(is_ia32_Immediate(right_op)) {
412 emit_ia32_Immediate(right_op);
413 be_emit_cstring(", ");
416 reg_left = get_in_reg(node, n_ia32_binary_left);
418 be_emit_cstring(", ");
419 emit_register(reg_left, mode);
423 panic("DestMode can't be output by %%binop anymore");
426 assert(0 && "unsupported op type");
431 * Emits registers and/or address mode of a binary operation.
433 void ia32_emit_x87_binop(const ir_node *node) {
434 switch(get_ia32_op_type(node)) {
437 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
438 const arch_register_t *in1 = x87_attr->x87[0];
439 const arch_register_t *in2 = x87_attr->x87[1];
440 const arch_register_t *out = x87_attr->x87[2];
441 const arch_register_t *in;
443 in = out ? ((out == in2) ? in1 : in2) : in2;
444 out = out ? out : in1;
447 be_emit_string(arch_register_get_name(in));
448 be_emit_cstring(", %");
449 be_emit_string(arch_register_get_name(out));
457 assert(0 && "unsupported op type");
461 void ia32_emit_am_or_dest_register(const ir_node *node,
463 if(get_ia32_op_type(node) == ia32_Normal) {
464 ia32_emit_dest_register(node, pos);
466 assert(get_ia32_op_type(node) == ia32_AddrModeD);
472 * Emits registers and/or address mode of a unary operation.
474 void ia32_emit_unop(const ir_node *node, int pos) {
477 switch(get_ia32_op_type(node)) {
479 op = get_irn_n(node, pos);
480 if (is_ia32_Immediate(op)) {
481 emit_ia32_Immediate(op);
483 ia32_emit_source_register(node, pos);
491 assert(0 && "unsupported op type");
496 * Emits address mode.
498 void ia32_emit_am(const ir_node *node) {
499 ir_entity *ent = get_ia32_am_sc(node);
500 int offs = get_ia32_am_offs_int(node);
501 ir_node *base = get_irn_n(node, 0);
502 int has_base = !is_ia32_NoReg_GP(base);
503 ir_node *index = get_irn_n(node, 1);
504 int has_index = !is_ia32_NoReg_GP(index);
506 /* just to be sure... */
507 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
513 set_entity_backend_marked(ent, 1);
514 id = get_entity_ld_ident(ent);
515 if (is_ia32_am_sc_sign(node))
519 if(get_entity_owner(ent) == get_tls_type()) {
520 if (get_entity_visibility(ent) == visibility_external_allocated) {
521 be_emit_cstring("@INDNTPOFF");
523 be_emit_cstring("@NTPOFF");
530 be_emit_irprintf("%+d", offs);
532 be_emit_irprintf("%d", offs);
536 if (has_base || has_index) {
541 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
542 emit_register(reg, NULL);
545 /* emit index + scale */
547 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
550 emit_register(reg, NULL);
552 scale = get_ia32_am_scale(node);
554 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
560 /* special case if nothing is set */
561 if(ent == NULL && offs == 0 && !has_base && !has_index) {
566 /*************************************************
569 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
570 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
571 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
572 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
574 *************************************************/
577 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
580 * coding of conditions
582 struct cmp2conditon_t {
588 * positive conditions for signed compares
590 static const struct cmp2conditon_t cmp2condition_s[] = {
591 { NULL, pn_Cmp_False }, /* always false */
592 { "e", pn_Cmp_Eq }, /* == */
593 { "l", pn_Cmp_Lt }, /* < */
594 { "le", pn_Cmp_Le }, /* <= */
595 { "g", pn_Cmp_Gt }, /* > */
596 { "ge", pn_Cmp_Ge }, /* >= */
597 { "ne", pn_Cmp_Lg }, /* != */
598 { NULL, pn_Cmp_Leg}, /* always true */
602 * positive conditions for unsigned compares
604 static const struct cmp2conditon_t cmp2condition_u[] = {
605 { NULL, pn_Cmp_False }, /* always false */
606 { "e", pn_Cmp_Eq }, /* == */
607 { "b", pn_Cmp_Lt }, /* < */
608 { "be", pn_Cmp_Le }, /* <= */
609 { "a", pn_Cmp_Gt }, /* > */
610 { "ae", pn_Cmp_Ge }, /* >= */
611 { "ne", pn_Cmp_Lg }, /* != */
612 { NULL, pn_Cmp_Leg }, /* always true */
616 ia32_pn_Cmp_unsigned = 0x1000,
617 ia32_pn_Cmp_float = 0x2000,
621 * walks up a tree of copies/perms/spills/reloads to find the original value
622 * that is moved around
624 static ir_node *find_original_value(ir_node *node)
626 inc_irg_visited(current_ir_graph);
628 mark_irn_visited(node);
629 if(be_is_Copy(node)) {
630 node = be_get_Copy_op(node);
631 } else if(be_is_CopyKeep(node)) {
632 node = be_get_CopyKeep_op(node);
633 } else if(is_Proj(node)) {
634 ir_node *pred = get_Proj_pred(node);
635 if(be_is_Perm(pred)) {
636 node = get_irn_n(pred, get_Proj_proj(node));
637 } else if(be_is_MemPerm(pred)) {
638 node = get_irn_n(pred, get_Proj_proj(node) + 1);
639 } else if(is_ia32_Load(pred)) {
640 node = get_irn_n(pred, n_ia32_Load_mem);
644 } else if(is_ia32_Store(node)) {
645 node = get_irn_n(node, n_ia32_Store_val);
646 } else if(is_Phi(node)) {
648 arity = get_irn_arity(node);
649 for(i = 0; i < arity; ++i) {
650 ir_node *in = get_irn_n(node, i);
663 static int determine_final_pnc(const ir_node *node, int flags_pos,
666 ir_node *flags = get_irn_n(node, flags_pos);
667 const ia32_attr_t *flags_attr;
668 flags = skip_Proj(flags);
670 if(is_ia32_Sahf(flags)) {
671 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
672 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
673 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
674 cmp = find_original_value(cmp);
675 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
676 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
679 flags_attr = get_ia32_attr_const(cmp);
680 if(flags_attr->data.cmp_flipped)
681 pnc = get_mirrored_pnc(pnc);
682 pnc |= ia32_pn_Cmp_float;
683 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
684 || is_ia32_Fucompi(flags)) {
685 flags_attr = get_ia32_attr_const(flags);
687 if(flags_attr->data.cmp_flipped)
688 pnc = get_mirrored_pnc(pnc);
689 pnc |= ia32_pn_Cmp_float;
691 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
692 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
693 flags_attr = get_ia32_attr_const(flags);
695 if(flags_attr->data.cmp_flipped)
696 pnc = get_mirrored_pnc(pnc);
697 if(flags_attr->data.cmp_unsigned)
698 pnc |= ia32_pn_Cmp_unsigned;
704 static void ia32_emit_cmp_suffix(int pnc)
708 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
710 assert(cmp2condition_u[pnc].num == pnc);
711 str = cmp2condition_u[pnc].name;
714 assert(cmp2condition_s[pnc].num == pnc);
715 str = cmp2condition_s[pnc].name;
721 void ia32_emit_cmp_suffix_node(const ir_node *node,
724 pn_Cmp pnc = get_ia32_pncode(node);
726 pnc = determine_final_pnc(node, flags_pos, pnc);
727 ia32_emit_cmp_suffix(pnc);
731 * Returns the target block for a control flow node.
734 ir_node *get_cfop_target_block(const ir_node *irn) {
735 return get_irn_link(irn);
739 * Emits a block label for the given block.
742 void ia32_emit_block_name(const ir_node *block)
744 if (has_Block_label(block)) {
745 be_emit_string(be_gas_label_prefix());
746 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
748 be_emit_cstring(BLOCK_PREFIX);
749 be_emit_irprintf("%d", get_irn_node_nr(block));
754 * Emits the target label for a control flow node.
756 static void ia32_emit_cfop_target(const ir_node *node)
758 ir_node *block = get_cfop_target_block(node);
760 ia32_emit_block_name(block);
763 /** Return the next block in Block schedule */
764 static ir_node *next_blk_sched(const ir_node *block)
766 return get_irn_link(block);
770 * Returns the Proj with projection number proj and NOT mode_M
772 static ir_node *get_proj(const ir_node *node, long proj) {
773 const ir_edge_t *edge;
776 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
778 foreach_out_edge(node, edge) {
779 src = get_edge_src_irn(edge);
781 assert(is_Proj(src) && "Proj expected");
782 if (get_irn_mode(src) == mode_M)
785 if (get_Proj_proj(src) == proj)
792 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
794 static void emit_ia32_Jcc(const ir_node *node)
796 const ir_node *proj_true;
797 const ir_node *proj_false;
798 const ir_node *block;
799 const ir_node *next_block;
800 pn_Cmp pnc = get_ia32_pncode(node);
802 pnc = determine_final_pnc(node, 0, pnc);
805 proj_true = get_proj(node, pn_ia32_Jcc_true);
806 assert(proj_true && "Jcc without true Proj");
808 proj_false = get_proj(node, pn_ia32_Jcc_false);
809 assert(proj_false && "Jcc without false Proj");
811 block = get_nodes_block(node);
812 next_block = next_blk_sched(block);
814 if (get_cfop_target_block(proj_true) == next_block) {
815 /* exchange both proj's so the second one can be omitted */
816 const ir_node *t = proj_true;
818 proj_true = proj_false;
820 if(pnc & ia32_pn_Cmp_float) {
821 pnc = get_negated_pnc(pnc, mode_F);
823 pnc = get_negated_pnc(pnc, mode_Iu);
827 if (pnc & ia32_pn_Cmp_float) {
828 /* Some floating point comparisons require a test of the parity flag,
829 * which indicates that the result is unordered */
832 be_emit_cstring("\tjp ");
833 ia32_emit_cfop_target(proj_true);
834 be_emit_finish_line_gas(proj_true);
838 be_emit_cstring("\tjnp ");
839 ia32_emit_cfop_target(proj_true);
840 be_emit_finish_line_gas(proj_true);
846 be_emit_cstring("\tjp ");
847 ia32_emit_cfop_target(proj_false);
848 be_emit_finish_line_gas(proj_false);
854 be_emit_cstring("\tjp ");
855 ia32_emit_cfop_target(proj_true);
856 be_emit_finish_line_gas(proj_true);
864 be_emit_cstring("\tj");
865 ia32_emit_cmp_suffix(pnc);
867 ia32_emit_cfop_target(proj_true);
868 be_emit_finish_line_gas(proj_true);
871 /* the second Proj might be a fallthrough */
872 if (get_cfop_target_block(proj_false) != next_block) {
873 be_emit_cstring("\tjmp ");
874 ia32_emit_cfop_target(proj_false);
875 be_emit_finish_line_gas(proj_false);
877 be_emit_cstring("\t/* fallthrough to ");
878 ia32_emit_cfop_target(proj_false);
879 be_emit_cstring(" */");
880 be_emit_finish_line_gas(proj_false);
884 static void emit_ia32_CMov(const ir_node *node)
886 const arch_register_t *out = arch_get_irn_register(arch_env, node);
887 pn_Cmp pnc = get_ia32_pncode(node);
888 const arch_register_t *in_true;
889 const arch_register_t *in_false;
891 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
893 in_true = arch_get_irn_register(arch_env,
894 get_irn_n(node, n_ia32_CMov_val_true));
895 in_false = arch_get_irn_register(arch_env,
896 get_irn_n(node, n_ia32_CMov_val_false));
898 /* should be same constraint fullfilled? */
899 if(out == in_false) {
900 /* yes -> nothing to do */
901 } else if(out == in_true) {
902 const arch_register_t *tmp;
904 if(pnc & ia32_pn_Cmp_float) {
905 pnc = get_negated_pnc(pnc, mode_F);
907 pnc = get_negated_pnc(pnc, mode_Iu);
915 be_emit_cstring("\tmovl ");
916 emit_register(in_false, NULL);
917 be_emit_cstring(", ");
918 emit_register(out, NULL);
919 be_emit_finish_line_gas(node);
922 /* TODO: handling of Nans isn't correct yet */
924 be_emit_cstring("\tcmov");
925 ia32_emit_cmp_suffix(pnc);
927 if(get_ia32_op_type(node) == ia32_AddrModeS) {
930 emit_register(in_true, get_ia32_ls_mode(node));
932 be_emit_cstring(", ");
933 emit_register(out, get_ia32_ls_mode(node));
934 be_emit_finish_line_gas(node);
937 /*********************************************************
940 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
941 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
942 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
943 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
946 *********************************************************/
948 /* jump table entry (target and corresponding number) */
949 typedef struct _branch_t {
954 /* jump table for switch generation */
955 typedef struct _jmp_tbl_t {
956 ir_node *defProj; /**< default target */
957 long min_value; /**< smallest switch case */
958 long max_value; /**< largest switch case */
959 long num_branches; /**< number of jumps */
960 char *label; /**< label of the jump table */
961 branch_t *branches; /**< jump array */
965 * Compare two variables of type branch_t. Used to sort all switch cases
968 int ia32_cmp_branch_t(const void *a, const void *b) {
969 branch_t *b1 = (branch_t *)a;
970 branch_t *b2 = (branch_t *)b;
972 if (b1->value <= b2->value)
979 * Emits code for a SwitchJmp (creates a jump table if
980 * possible otherwise a cmp-jmp cascade). Port from
984 void emit_ia32_SwitchJmp(const ir_node *node) {
985 unsigned long interval;
990 const ir_edge_t *edge;
992 /* fill the table structure */
993 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
994 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
996 tbl.num_branches = get_irn_n_edges(node);
997 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
998 tbl.min_value = INT_MAX;
999 tbl.max_value = INT_MIN;
1002 /* go over all proj's and collect them */
1003 foreach_out_edge(node, edge) {
1004 proj = get_edge_src_irn(edge);
1005 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1007 pnc = get_Proj_proj(proj);
1009 /* create branch entry */
1010 tbl.branches[i].target = proj;
1011 tbl.branches[i].value = pnc;
1013 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1014 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1016 /* check for default proj */
1017 if (pnc == get_ia32_pncode(node)) {
1018 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1025 /* sort the branches by their number */
1026 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1028 /* two-complement's magic make this work without overflow */
1029 interval = tbl.max_value - tbl.min_value;
1031 /* emit the table */
1032 be_emit_cstring("\tcmpl $");
1033 be_emit_irprintf("%u, ", interval);
1034 ia32_emit_source_register(node, 0);
1035 be_emit_finish_line_gas(node);
1037 be_emit_cstring("\tja ");
1038 ia32_emit_cfop_target(tbl.defProj);
1039 be_emit_finish_line_gas(node);
1041 if (tbl.num_branches > 1) {
1043 be_emit_cstring("\tjmp *");
1044 be_emit_string(tbl.label);
1045 be_emit_cstring("(,");
1046 ia32_emit_source_register(node, 0);
1047 be_emit_cstring(",4)");
1048 be_emit_finish_line_gas(node);
1050 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1051 be_emit_cstring("\t.align 4\n");
1052 be_emit_write_line();
1054 be_emit_string(tbl.label);
1055 be_emit_cstring(":\n");
1056 be_emit_write_line();
1058 be_emit_cstring(".long ");
1059 ia32_emit_cfop_target(tbl.branches[0].target);
1060 be_emit_finish_line_gas(NULL);
1062 last_value = tbl.branches[0].value;
1063 for (i = 1; i < tbl.num_branches; ++i) {
1064 while (++last_value < tbl.branches[i].value) {
1065 be_emit_cstring(".long ");
1066 ia32_emit_cfop_target(tbl.defProj);
1067 be_emit_finish_line_gas(NULL);
1069 be_emit_cstring(".long ");
1070 ia32_emit_cfop_target(tbl.branches[i].target);
1071 be_emit_finish_line_gas(NULL);
1073 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1075 /* one jump is enough */
1076 be_emit_cstring("\tjmp ");
1077 ia32_emit_cfop_target(tbl.branches[0].target);
1078 be_emit_finish_line_gas(node);
1088 * Emits code for a unconditional jump.
1090 static void emit_Jmp(const ir_node *node)
1092 ir_node *block, *next_block;
1094 /* for now, the code works for scheduled and non-schedules blocks */
1095 block = get_nodes_block(node);
1097 /* we have a block schedule */
1098 next_block = next_blk_sched(block);
1099 if (get_cfop_target_block(node) != next_block) {
1100 be_emit_cstring("\tjmp ");
1101 ia32_emit_cfop_target(node);
1103 be_emit_cstring("\t/* fallthrough to ");
1104 ia32_emit_cfop_target(node);
1105 be_emit_cstring(" */");
1107 be_emit_finish_line_gas(node);
1110 static void emit_ia32_Immediate(const ir_node *node)
1112 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1115 if(attr->symconst != NULL) {
1116 ident *id = get_entity_ld_ident(attr->symconst);
1118 if(attr->attr.data.am_sc_sign)
1122 if(attr->symconst == NULL || attr->offset != 0) {
1123 if(attr->symconst != NULL) {
1124 be_emit_irprintf("%+d", attr->offset);
1126 be_emit_irprintf("0x%X", attr->offset);
1131 static const char* emit_asm_operand(const ir_node *node, const char *s)
1133 const arch_register_t *reg;
1134 const char *reg_name;
1138 const ia32_attr_t *attr;
1145 /* parse modifiers */
1148 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1172 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1173 "'%c' for asm op\n", node, c);
1179 sscanf(s, "%d%n", &num, &p);
1181 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1189 attr = get_ia32_attr_const(node);
1190 n_outs = ARR_LEN(attr->slots);
1192 reg = get_out_reg(node, num);
1195 int in = num - n_outs;
1196 if(in >= get_irn_arity(node)) {
1197 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1198 "op (%+F)\n", num, node);
1201 pred = get_irn_n(node, in);
1202 /* might be an immediate value */
1203 if(is_ia32_Immediate(pred)) {
1204 emit_ia32_Immediate(pred);
1207 reg = get_in_reg(node, in);
1210 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1211 "(%+F)\n", num, node);
1219 reg_name = arch_register_get_name(reg);
1222 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1225 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1228 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1231 panic("Invalid asm op modifier");
1233 be_emit_string(reg_name);
1239 * Emits code for an ASM pseudo op.
1241 static void emit_ia32_Asm(const ir_node *node)
1243 const void *gen_attr = get_irn_generic_attr_const(node);
1244 const ia32_asm_attr_t *attr
1245 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1246 ident *asm_text = attr->asm_text;
1247 const char *s = get_id_str(asm_text);
1249 be_emit_cstring("# Begin ASM \t");
1250 be_emit_finish_line_gas(node);
1257 s = emit_asm_operand(node, s);
1266 be_emit_write_line();
1268 be_emit_cstring("# End ASM\n");
1269 be_emit_write_line();
1272 /**********************************
1275 * | | ___ _ __ _ _| |_) |
1276 * | | / _ \| '_ \| | | | _ <
1277 * | |___| (_) | |_) | |_| | |_) |
1278 * \_____\___/| .__/ \__, |____/
1281 **********************************/
1284 * Emit movsb/w instructions to make mov count divideable by 4
1286 static void emit_CopyB_prolog(int rem) {
1287 be_emit_cstring("\tcld");
1288 be_emit_finish_line_gas(NULL);
1292 be_emit_cstring("\tmovsb");
1293 be_emit_finish_line_gas(NULL);
1296 be_emit_cstring("\tmovsw");
1297 be_emit_finish_line_gas(NULL);
1300 be_emit_cstring("\tmovsb");
1301 be_emit_finish_line_gas(NULL);
1302 be_emit_cstring("\tmovsw");
1303 be_emit_finish_line_gas(NULL);
1309 * Emit rep movsd instruction for memcopy.
1311 static void emit_ia32_CopyB(const ir_node *node)
1313 int rem = get_ia32_pncode(node);
1315 emit_CopyB_prolog(rem);
1317 be_emit_cstring("\trep movsd");
1318 be_emit_finish_line_gas(node);
1322 * Emits unrolled memcopy.
1324 static void emit_ia32_CopyB_i(const ir_node *node)
1326 int size = get_ia32_pncode(node);
1328 emit_CopyB_prolog(size & 0x3);
1332 be_emit_cstring("\tmovsd");
1333 be_emit_finish_line_gas(NULL);
1339 /***************************
1343 * | | / _ \| '_ \ \ / /
1344 * | |___| (_) | | | \ V /
1345 * \_____\___/|_| |_|\_/
1347 ***************************/
1350 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1352 static void emit_ia32_Conv_with_FP(const ir_node *node)
1354 ir_mode *ls_mode = get_ia32_ls_mode(node);
1355 int ls_bits = get_mode_size_bits(ls_mode);
1357 be_emit_cstring("\tcvt");
1359 if(is_ia32_Conv_I2FP(node)) {
1361 be_emit_cstring("si2ss");
1363 be_emit_cstring("si2sd");
1365 } else if(is_ia32_Conv_FP2I(node)) {
1367 be_emit_cstring("ss2si");
1369 be_emit_cstring("sd2si");
1372 assert(is_ia32_Conv_FP2FP(node));
1374 be_emit_cstring("sd2ss");
1376 be_emit_cstring("ss2sd");
1381 switch(get_ia32_op_type(node)) {
1383 ia32_emit_source_register(node, n_ia32_unary_op);
1385 case ia32_AddrModeS:
1389 assert(0 && "unsupported op type for Conv");
1391 be_emit_cstring(", ");
1392 ia32_emit_dest_register(node, 0);
1393 be_emit_finish_line_gas(node);
1396 static void emit_ia32_Conv_I2FP(const ir_node *node)
1398 emit_ia32_Conv_with_FP(node);
1401 static void emit_ia32_Conv_FP2I(const ir_node *node)
1403 emit_ia32_Conv_with_FP(node);
1406 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1408 emit_ia32_Conv_with_FP(node);
1412 * Emits code for an Int conversion.
1414 static void emit_ia32_Conv_I2I(const ir_node *node)
1416 const char *sign_suffix;
1417 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1418 int smaller_bits = get_mode_size_bits(smaller_mode);
1420 const arch_register_t *in_reg, *out_reg;
1422 assert(!mode_is_float(smaller_mode));
1423 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1425 signed_mode = mode_is_signed(smaller_mode);
1426 if(smaller_bits == 32) {
1427 // this should not happen as it's no convert
1431 sign_suffix = signed_mode ? "s" : "z";
1434 out_reg = get_out_reg(node, 0);
1436 switch(get_ia32_op_type(node)) {
1438 in_reg = get_in_reg(node, n_ia32_unary_op);
1440 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1441 out_reg == &ia32_gp_regs[REG_EAX] &&
1445 /* argument and result are both in EAX and */
1446 /* signedness is ok: -> use the smaller cwtl opcode */
1447 be_emit_cstring("\tcwtl");
1449 be_emit_cstring("\tmov");
1450 be_emit_string(sign_suffix);
1451 ia32_emit_mode_suffix_mode(smaller_mode);
1452 be_emit_cstring("l ");
1453 emit_register(in_reg, smaller_mode);
1454 be_emit_cstring(", ");
1455 emit_register(out_reg, NULL);
1458 case ia32_AddrModeS: {
1459 be_emit_cstring("\tmov");
1460 be_emit_string(sign_suffix);
1461 ia32_emit_mode_suffix_mode(smaller_mode);
1462 be_emit_cstring("l ");
1464 be_emit_cstring(", ");
1465 emit_register(out_reg, NULL);
1469 assert(0 && "unsupported op type for Conv");
1471 be_emit_finish_line_gas(node);
1475 * Emits code for an 8Bit Int conversion.
1477 static void emit_ia32_Conv_I2I8Bit(const ir_node *node)
1479 emit_ia32_Conv_I2I(node);
1483 /*******************************************
1486 * | |__ ___ _ __ ___ __| | ___ ___
1487 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1488 * | |_) | __/ | | | (_) | (_| | __/\__ \
1489 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1491 *******************************************/
1494 * Emits a backend call
1496 static void emit_be_Call(const ir_node *node)
1498 ir_entity *ent = be_Call_get_entity(node);
1500 be_emit_cstring("\tcall ");
1502 set_entity_backend_marked(ent, 1);
1503 be_emit_string(get_entity_ld_name(ent));
1505 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1507 emit_register(reg, NULL);
1509 be_emit_finish_line_gas(node);
1513 * Emits code to increase stack pointer.
1515 static void emit_be_IncSP(const ir_node *node)
1517 int offs = be_get_IncSP_offset(node);
1518 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1524 be_emit_cstring("\tsubl $");
1525 be_emit_irprintf("%u, ", offs);
1526 emit_register(reg, NULL);
1528 be_emit_cstring("\taddl $");
1529 be_emit_irprintf("%u, ", -offs);
1530 emit_register(reg, NULL);
1532 be_emit_finish_line_gas(node);
1536 * Emits code for Copy/CopyKeep.
1538 static void Copy_emitter(const ir_node *node, const ir_node *op)
1540 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1541 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1547 if(is_unknown_reg(in))
1549 /* copies of vf nodes aren't real... */
1550 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1553 mode = get_irn_mode(node);
1554 if (mode == mode_E) {
1555 be_emit_cstring("\tmovsd ");
1556 emit_register(in, NULL);
1557 be_emit_cstring(", ");
1558 emit_register(out, NULL);
1560 be_emit_cstring("\tmovl ");
1561 emit_register(in, NULL);
1562 be_emit_cstring(", ");
1563 emit_register(out, NULL);
1565 be_emit_finish_line_gas(node);
1568 static void emit_be_Copy(const ir_node *node)
1570 Copy_emitter(node, be_get_Copy_op(node));
1573 static void emit_be_CopyKeep(const ir_node *node)
1575 Copy_emitter(node, be_get_CopyKeep_op(node));
1579 * Emits code for exchange.
1581 static void emit_be_Perm(const ir_node *node)
1583 const arch_register_t *in0, *in1;
1584 const arch_register_class_t *cls0, *cls1;
1586 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1587 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1589 cls0 = arch_register_get_class(in0);
1590 cls1 = arch_register_get_class(in1);
1592 assert(cls0 == cls1 && "Register class mismatch at Perm");
1594 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1595 be_emit_cstring("\txchg ");
1596 emit_register(in1, NULL);
1597 be_emit_cstring(", ");
1598 emit_register(in0, NULL);
1599 be_emit_finish_line_gas(node);
1600 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1601 be_emit_cstring("\txorpd ");
1602 emit_register(in1, NULL);
1603 be_emit_cstring(", ");
1604 emit_register(in0, NULL);
1605 be_emit_finish_line_gas(NULL);
1607 be_emit_cstring("\txorpd ");
1608 emit_register(in0, NULL);
1609 be_emit_cstring(", ");
1610 emit_register(in1, NULL);
1611 be_emit_finish_line_gas(NULL);
1613 be_emit_cstring("\txorpd ");
1614 emit_register(in1, NULL);
1615 be_emit_cstring(", ");
1616 emit_register(in0, NULL);
1617 be_emit_finish_line_gas(node);
1618 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1620 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1623 panic("unexpected register class in be_Perm (%+F)\n", node);
1628 * Emits code for Constant loading.
1630 static void emit_ia32_Const(const ir_node *node)
1632 be_emit_cstring("\tmovl ");
1633 emit_ia32_Immediate(node);
1634 be_emit_cstring(", ");
1635 ia32_emit_dest_register(node, 0);
1637 be_emit_finish_line_gas(node);
1641 * Emits code to load the TLS base
1643 static void emit_ia32_LdTls(const ir_node *node)
1645 be_emit_cstring("\tmovl %gs:0, ");
1646 ia32_emit_dest_register(node, 0);
1647 be_emit_finish_line_gas(node);
1650 /* helper function for emit_ia32_Minus64Bit */
1651 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1653 be_emit_cstring("\tmovl ");
1654 emit_register(src, NULL);
1655 be_emit_cstring(", ");
1656 emit_register(dst, NULL);
1657 be_emit_finish_line_gas(node);
1660 /* helper function for emit_ia32_Minus64Bit */
1661 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1663 be_emit_cstring("\tnegl ");
1664 emit_register(reg, NULL);
1665 be_emit_finish_line_gas(node);
1668 /* helper function for emit_ia32_Minus64Bit */
1669 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1671 be_emit_cstring("\tsbbl $0, ");
1672 emit_register(reg, NULL);
1673 be_emit_finish_line_gas(node);
1676 /* helper function for emit_ia32_Minus64Bit */
1677 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1679 be_emit_cstring("\tsbbl ");
1680 emit_register(src, NULL);
1681 be_emit_cstring(", ");
1682 emit_register(dst, NULL);
1683 be_emit_finish_line_gas(node);
1686 /* helper function for emit_ia32_Minus64Bit */
1687 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1689 be_emit_cstring("\txchgl ");
1690 emit_register(src, NULL);
1691 be_emit_cstring(", ");
1692 emit_register(dst, NULL);
1693 be_emit_finish_line_gas(node);
1696 /* helper function for emit_ia32_Minus64Bit */
1697 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1699 be_emit_cstring("\txorl ");
1700 emit_register(reg, NULL);
1701 be_emit_cstring(", ");
1702 emit_register(reg, NULL);
1703 be_emit_finish_line_gas(node);
1706 static void emit_ia32_Minus64Bit(const ir_node *node)
1708 const arch_register_t *in_lo = get_in_reg(node, 0);
1709 const arch_register_t *in_hi = get_in_reg(node, 1);
1710 const arch_register_t *out_lo = get_out_reg(node, 0);
1711 const arch_register_t *out_hi = get_out_reg(node, 1);
1713 if (out_lo == in_lo) {
1714 if (out_hi != in_hi) {
1715 /* a -> a, b -> d */
1718 /* a -> a, b -> b */
1721 } else if (out_lo == in_hi) {
1722 if (out_hi == in_lo) {
1723 /* a -> b, b -> a */
1724 emit_xchg(node, in_lo, in_hi);
1727 /* a -> b, b -> d */
1728 emit_mov(node, in_hi, out_hi);
1729 emit_mov(node, in_lo, out_lo);
1733 if (out_hi == in_lo) {
1734 /* a -> c, b -> a */
1735 emit_mov(node, in_lo, out_lo);
1737 } else if (out_hi == in_hi) {
1738 /* a -> c, b -> b */
1739 emit_mov(node, in_lo, out_lo);
1742 /* a -> c, b -> d */
1743 emit_mov(node, in_lo, out_lo);
1749 emit_neg( node, out_hi);
1750 emit_neg( node, out_lo);
1751 emit_sbb0(node, out_hi);
1755 emit_zero(node, out_hi);
1756 emit_neg( node, out_lo);
1757 emit_sbb( node, in_hi, out_hi);
1760 static void emit_be_Return(const ir_node *node)
1763 be_emit_cstring("\tret");
1765 pop = be_Return_get_pop(node);
1767 be_emit_irprintf(" $%d", pop);
1769 be_emit_finish_line_gas(node);
1772 static void emit_Nothing(const ir_node *node)
1778 /***********************************************************************************
1781 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1782 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1783 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1784 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1786 ***********************************************************************************/
1789 * Enters the emitter functions for handled nodes into the generic
1790 * pointer of an opcode.
1793 void ia32_register_emitters(void) {
1795 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1796 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1797 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1798 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1799 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1800 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1802 /* first clear the generic function pointer for all ops */
1803 clear_irp_opcodes_generic_func();
1805 /* register all emitter functions defined in spec */
1806 ia32_register_spec_emitters();
1808 /* other ia32 emitter functions */
1811 IA32_EMIT(SwitchJmp);
1814 IA32_EMIT(Conv_I2FP);
1815 IA32_EMIT(Conv_FP2I);
1816 IA32_EMIT(Conv_FP2FP);
1817 IA32_EMIT(Conv_I2I);
1818 IA32_EMIT(Conv_I2I8Bit);
1821 IA32_EMIT(Minus64Bit);
1824 /* benode emitter */
1849 static const char *last_name = NULL;
1850 static unsigned last_line = -1;
1851 static unsigned num = -1;
1854 * Emit the debug support for node node.
1856 static void ia32_emit_dbg(const ir_node *node)
1858 dbg_info *db = get_irn_dbg_info(node);
1860 const char *fname = be_retrieve_dbg_info(db, &lineno);
1862 if (! cg->birg->main_env->options->stabs_debug_support)
1866 if (last_name != fname) {
1868 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1871 if (last_line != lineno) {
1874 snprintf(name, sizeof(name), ".LM%u", ++num);
1876 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1877 be_emit_string(name);
1878 be_emit_cstring(":\n");
1879 be_emit_write_line();
1884 typedef void (*emit_func_ptr) (const ir_node *);
1887 * Emits code for a node.
1889 static void ia32_emit_node(const ir_node *node)
1891 ir_op *op = get_irn_op(node);
1893 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1895 if (op->ops.generic) {
1896 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1897 ia32_emit_dbg(node);
1901 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1907 * Emits gas alignment directives
1909 static void ia32_emit_alignment(unsigned align, unsigned skip)
1911 be_emit_cstring("\t.p2align ");
1912 be_emit_irprintf("%u,,%u\n", align, skip);
1913 be_emit_write_line();
1917 * Emits gas alignment directives for Functions depended on cpu architecture.
1919 static void ia32_emit_align_func(cpu_support cpu)
1922 unsigned maximum_skip;
1937 maximum_skip = (1 << align) - 1;
1938 ia32_emit_alignment(align, maximum_skip);
1942 * Emits gas alignment directives for Labels depended on cpu architecture.
1944 static void ia32_emit_align_label(cpu_support cpu)
1946 unsigned align; unsigned maximum_skip;
1961 maximum_skip = (1 << align) - 1;
1962 ia32_emit_alignment(align, maximum_skip);
1966 * Test wether a block should be aligned.
1967 * For cpus in the P4/Athlon class it is usefull to align jump labels to
1968 * 16 bytes. However we should only do that if the alignment nops before the
1969 * label aren't executed more often than we have jumps to the label.
1971 static int should_align_block(ir_node *block, ir_node *prev)
1973 static const double DELTA = .0001;
1974 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1976 double prev_freq = 0; /**< execfreq of the fallthrough block */
1977 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1978 cpu_support cpu = isa->opt_arch;
1981 if(exec_freq == NULL)
1983 if(cpu == arch_i386 || cpu == arch_i486)
1986 block_freq = get_block_execfreq(exec_freq, block);
1987 if(block_freq < DELTA)
1990 n_cfgpreds = get_Block_n_cfgpreds(block);
1991 for(i = 0; i < n_cfgpreds; ++i) {
1992 ir_node *pred = get_Block_cfgpred_block(block, i);
1993 double pred_freq = get_block_execfreq(exec_freq, pred);
1996 prev_freq += pred_freq;
1998 jmp_freq += pred_freq;
2002 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2005 jmp_freq /= prev_freq;
2009 case arch_athlon_64:
2011 return jmp_freq > 3;
2013 return jmp_freq > 2;
2017 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2022 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2024 n_cfgpreds = get_Block_n_cfgpreds(block);
2025 need_label = (n_cfgpreds != 0);
2027 if (should_align_block(block, prev)) {
2029 ia32_emit_align_label(isa->opt_arch);
2033 ia32_emit_block_name(block);
2036 be_emit_pad_comment();
2037 be_emit_cstring(" /* preds:");
2039 /* emit list of pred blocks in comment */
2040 arity = get_irn_arity(block);
2041 for (i = 0; i < arity; ++i) {
2042 ir_node *predblock = get_Block_cfgpred_block(block, i);
2043 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2046 be_emit_cstring("\t/* ");
2047 ia32_emit_block_name(block);
2048 be_emit_cstring(": ");
2050 if (exec_freq != NULL) {
2051 be_emit_irprintf(" freq: %f",
2052 get_block_execfreq(exec_freq, block));
2054 be_emit_cstring(" */\n");
2055 be_emit_write_line();
2059 * Walks over the nodes in a block connected by scheduling edges
2060 * and emits code for each node.
2062 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2064 const ir_node *node;
2066 ia32_emit_block_header(block, last_block);
2068 /* emit the contents of the block */
2069 ia32_emit_dbg(block);
2070 sched_foreach(block, node) {
2071 ia32_emit_node(node);
2076 * Emits code for function start.
2078 static void ia32_emit_func_prolog(ir_graph *irg)
2080 ir_entity *irg_ent = get_irg_entity(irg);
2081 const char *irg_name = get_entity_ld_name(irg_ent);
2082 cpu_support cpu = isa->opt_arch;
2083 const be_irg_t *birg = cg->birg;
2085 be_emit_write_line();
2086 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2087 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2088 ia32_emit_align_func(cpu);
2089 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2090 be_emit_cstring(".global ");
2091 be_emit_string(irg_name);
2093 be_emit_write_line();
2095 ia32_emit_function_object(irg_name);
2096 be_emit_string(irg_name);
2097 be_emit_cstring(":\n");
2098 be_emit_write_line();
2102 * Emits code for function end
2104 static void ia32_emit_func_epilog(ir_graph *irg)
2106 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2107 const be_irg_t *birg = cg->birg;
2109 ia32_emit_function_size(irg_name);
2110 be_dbg_method_end(birg->main_env->db_handle);
2112 be_emit_write_line();
2117 * Sets labels for control flow nodes (jump target)
2119 static void ia32_gen_labels(ir_node *block, void *data)
2122 int n = get_Block_n_cfgpreds(block);
2125 for (n--; n >= 0; n--) {
2126 pred = get_Block_cfgpred(block, n);
2127 set_irn_link(pred, block);
2132 * Emit an exception label if the current instruction can fail.
2134 void ia32_emit_exc_label(const ir_node *node)
2136 if (get_ia32_exc_label(node)) {
2137 be_emit_irprintf(".EXL%u\n", 0);
2138 be_emit_write_line();
2143 * Main driver. Emits the code for one routine.
2145 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2148 ir_node *last_block = NULL;
2152 isa = (const ia32_isa_t*) cg->arch_env->isa;
2153 arch_env = cg->arch_env;
2155 ia32_register_emitters();
2157 ia32_emit_func_prolog(irg);
2158 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2160 n = ARR_LEN(cg->blk_sched);
2161 for (i = 0; i < n;) {
2164 block = cg->blk_sched[i];
2166 next_bl = i < n ? cg->blk_sched[i] : NULL;
2168 /* set here the link. the emitter expects to find the next block here */
2169 set_irn_link(block, next_bl);
2170 ia32_gen_block(block, last_block);
2174 ia32_emit_func_epilog(irg);
2177 void ia32_init_emitter(void)
2179 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");