nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33
  34 #include "../betranshlp.h"
  35 #include "../beirg_t.h"
  36
  37 #include "ia32_architecture.h"
  38 #include "ia32_common_transform.h"
  39 #include "ia32_new_nodes.h"
  40
  41 #include "gen_ia32_new_nodes.h"
  42 #include "gen_ia32_regalloc_if.h"
  43
  44 /** hold the current code generator during transformation */
  45 ia32_code_gen_t *env_cg = NULL;
  46
  47 heights_t *heights = NULL;
  48
  49 static const arch_register_req_t no_register_req = {
  50         arch_register_req_type_none,
  51         NULL,                         /* regclass */
  52         NULL,                         /* limit bitset */
  53         0,                            /* same pos */
  54         0                             /* different pos */
  55 };
  56
  57 static int check_immediate_constraint(long val, char immediate_constraint_type)
  58 {
  59         switch (immediate_constraint_type) {
  60                 case 0:
  61                 case 'i': return 1;
  62
  63                 case 'I': return    0 <= val && val <=  31;
  64                 case 'J': return    0 <= val && val <=  63;
  65                 case 'K': return -128 <= val && val <= 127;
  66                 case 'L': return val == 0xff || val == 0xffff;
  67                 case 'M': return    0 <= val && val <=   3;
  68                 case 'N': return    0 <= val && val <= 255;
  69                 case 'O': return    0 <= val && val <= 127;
  70
  71                 default: panic("Invalid immediate constraint found");
  72         }
  73 }
  74
  75 /* creates a unique ident by adding a number to a tag */
  76 ident *ia32_unique_id(const char *tag)
  77 {
  78         static unsigned id = 0;
  79         char str[256];
  80
  81         snprintf(str, sizeof(str), tag, ++id);
  82         return new_id_from_str(str);
  83 }
  84
  85 /**
  86  * Get a primitive type for a mode with alignment 16.
  87  */
  88 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  89 {
  90         pmap_entry *e = pmap_find(types, mode);
  91         ir_type *res;
  92
  93         if (! e) {
  94                 char buf[64];
  95                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
  96                 res = new_type_primitive(new_id_from_str(buf), mode);
  97                 /* FIXME: this is too much for most cases */
  98                 set_type_alignment_bytes(res, 16);
  99                 pmap_insert(types, mode, res);
 100         }
 101         else
 102                 res = e->value;
 103         return res;
 104 }
 105
 106 ir_entity *create_float_const_entity(ir_node *cnst)
 107 {
 108         ia32_isa_t *isa = env_cg->isa;
 109         tarval *key     = get_Const_tarval(cnst);
 110         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 111         ir_entity *res;
 112         ir_graph *rem;
 113
 114         if (e == NULL) {
 115                 tarval  *tv   = key;
 116                 ir_mode *mode = get_tarval_mode(tv);
 117                 ir_type *tp;
 118
 119                 if (! ia32_cg_config.use_sse2) {
 120                         /* try to reduce the mode to produce smaller sized entities */
 121                         if (mode != mode_F) {
 122                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 123                                         mode = mode_F;
 124                                         tv = tarval_convert_to(tv, mode);
 125                                 } else if (mode != mode_D) {
 126                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 127                                                 mode = mode_D;
 128                                                 tv = tarval_convert_to(tv, mode);
 129                                         }
 130                                 }
 131                         }
 132                 }
 133
 134                 if (mode == get_irn_mode(cnst)) {
 135                         /* mode was not changed */
 136                         tp = get_Const_type(cnst);
 137                         if (tp == firm_unknown_type)
 138                                 tp = ia32_get_prim_type(isa->types, mode);
 139                 } else
 140                         tp = ia32_get_prim_type(isa->types, mode);
 141
 142                 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
 143
 144                 set_entity_ld_ident(res, get_entity_ident(res));
 145                 set_entity_visibility(res, visibility_local);
 146                 set_entity_variability(res, variability_constant);
 147                 set_entity_allocation(res, allocation_static);
 148
 149                  /* we create a new entity here: It's initialization must resist on the
 150                     const code irg */
 151                 rem = current_ir_graph;
 152                 current_ir_graph = get_const_code_irg();
 153                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 154                 current_ir_graph = rem;
 155
 156                 pmap_insert(isa->tv_ent, key, res);
 157         } else {
 158                 res = e->value;
 159         }
 160
 161         return res;
 162 }
 163
 164 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 165 {
 166         ir_graph *irg         = current_ir_graph;
 167         ir_node  *start_block = get_irg_start_block(irg);
 168         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 169                         symconst_sign, val);
 170         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 171
 172         return immediate;
 173 }
 174
 175 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 176 {
 177         const arch_register_t       *reg = NULL;
 178         int                          c;
 179         size_t                       r;
 180         const arch_register_class_t *cls;
 181
 182         /* TODO: construct a hashmap instead of doing linear search for clobber
 183          * register */
 184         for(c = 0; c < N_CLASSES; ++c) {
 185                 cls = & ia32_reg_classes[c];
 186                 for(r = 0; r < cls->n_regs; ++r) {
 187                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 188                         if (strcmp(temp_reg->name, clobber) == 0
 189                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 190                                 reg = temp_reg;
 191                                 break;
 192                         }
 193                 }
 194                 if (reg != NULL)
 195                         break;
 196         }
 197
 198         return reg;
 199 }
 200
 201 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 202         if (mode == mode_fpcw)
 203                 return 0;
 204         if (get_mode_size_bits(mode) > 32)
 205                 return 0;
 206         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 207 }
 208
 209 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 210                            int is_output)
 211 {
 212         char                         immediate_type     = '\0';
 213         unsigned                     limited            = 0;
 214         const arch_register_class_t *cls                = NULL;
 215         int                          memory_possible       = 0;
 216         int                          all_registers_allowed = 0;
 217         int                          p;
 218         int                          same_as = -1;
 219
 220         memset(constraint, 0, sizeof(constraint[0]));
 221         constraint->same_as = -1;
 222
 223         if (*c == 0) {
 224                 /* a memory constraint: no need to do anything in backend about it
 225                  * (the dependencies are already respected by the memory edge of
 226                  * the node) */
 227                 return;
 228         }
 229
 230         /* TODO: improve error messages with node and source info. (As users can
 231          * easily hit these) */
 232         while(*c != 0) {
 233                 switch(*c) {
 234                 case ' ':
 235                 case '\t':
 236                 case '\n':
 237                         break;
 238
 239                 /* Skip out/in-out marker */
 240                 case '=': break;
 241                 case '+': break;
 242
 243                 case '&': break;
 244
 245                 case '*':
 246                         ++c;
 247                         break;
 248                 case '#':
 249                         while(*c != 0 && *c != ',')
 250                                 ++c;
 251                         break;
 252
 253                 case 'a':
 254                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 255                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 256                         limited |= 1 << REG_EAX;
 257                         break;
 258                 case 'b':
 259                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 260                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 261                         limited |= 1 << REG_EBX;
 262                         break;
 263                 case 'c':
 264                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 265                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 266                         limited |= 1 << REG_ECX;
 267                         break;
 268                 case 'd':
 269                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 270                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 271                         limited |= 1 << REG_EDX;
 272                         break;
 273                 case 'D':
 274                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 275                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 276                         limited |= 1 << REG_EDI;
 277                         break;
 278                 case 'S':
 279                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 280                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 281                         limited |= 1 << REG_ESI;
 282                         break;
 283                 case 'Q':
 284                 case 'q':
 285                         /* q means lower part of the regs only, this makes no
 286                          * difference to Q for us (we only assign whole registers) */
 287                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 288                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 289                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 290                                    1 << REG_EDX;
 291                         break;
 292                 case 'A':
 293                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 294                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 295                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 296                         break;
 297                 case 'l':
 298                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 299                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 300                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 301                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 302                                    1 << REG_EBP;
 303                         break;
 304
 305                 case 'R':
 306                 case 'r':
 307                 case 'p':
 308                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 309                                 panic("multiple register classes not supported");
 310                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 311                         all_registers_allowed = 1;
 312                         break;
 313
 314                 case 'f':
 315                 case 't':
 316                 case 'u':
 317                         /* TODO: mark values so the x87 simulator knows about t and u */
 318                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 319                                 panic("multiple register classes not supported");
 320                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 321                         all_registers_allowed = 1;
 322                         break;
 323
 324                 case 'Y':
 325                 case 'x':
 326                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 327                                 panic("multiple register classes not supproted");
 328                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 329                         all_registers_allowed = 1;
 330                         break;
 331
 332                 case 'I':
 333                 case 'J':
 334                 case 'K':
 335                 case 'L':
 336                 case 'M':
 337                 case 'N':
 338                 case 'O':
 339                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 340                                 panic("multiple register classes not supported");
 341                         if (immediate_type != '\0')
 342                                 panic("multiple immediate types not supported");
 343                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 344                         immediate_type = *c;
 345                         break;
 346                 case 'n':
 347                 case 'i':
 348                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 349                                 panic("multiple register classes not supported");
 350                         if (immediate_type != '\0')
 351                                 panic("multiple immediate types not supported");
 352                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 353                         immediate_type = 'i';
 354                         break;
 355
 356                 case 'X':
 357                 case 'g':
 358                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 359                                 panic("multiple register classes not supported");
 360                         if (immediate_type != '\0')
 361                                 panic("multiple immediate types not supported");
 362                         immediate_type        = 'i';
 363                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 364                         all_registers_allowed = 1;
 365                         memory_possible       = 1;
 366                         break;
 367
 368                 case '0':
 369                 case '1':
 370                 case '2':
 371                 case '3':
 372                 case '4':
 373                 case '5':
 374                 case '6':
 375                 case '7':
 376                 case '8':
 377                 case '9':
 378                         if (is_output)
 379                                 panic("can only specify same constraint on input");
 380
 381                         sscanf(c, "%d%n", &same_as, &p);
 382                         if (same_as >= 0) {
 383                                 c += p;
 384                                 continue;
 385                         }
 386                         break;
 387
 388                 case 'm':
 389                 case 'o':
 390                 case 'V':
 391                         /* memory constraint no need to do anything in backend about it
 392                          * (the dependencies are already respected by the memory edge of
 393                          * the node) */
 394                         memory_possible = 1;
 395                         break;
 396
 397                 case 'E': /* no float consts yet */
 398                 case 'F': /* no float consts yet */
 399                 case 's': /* makes no sense on x86 */
 400                 case '<': /* no autodecrement on x86 */
 401                 case '>': /* no autoincrement on x86 */
 402                 case 'C': /* sse constant not supported yet */
 403                 case 'G': /* 80387 constant not supported yet */
 404                 case 'y': /* we don't support mmx registers yet */
 405                 case 'Z': /* not available in 32 bit mode */
 406                 case 'e': /* not available in 32 bit mode */
 407                         panic("unsupported asm constraint '%c' found in (%+F)",
 408                               *c, current_ir_graph);
 409                         break;
 410                 default:
 411                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 412                               current_ir_graph);
 413                         break;
 414                 }
 415                 ++c;
 416         }
 417
 418         if (same_as >= 0) {
 419                 if (cls != NULL)
 420                         panic("same as and register constraint not supported");
 421                 if (immediate_type != '\0')
 422                         panic("same as and immediate constraint not supported");
 423         }
 424
 425         if (cls == NULL && same_as < 0) {
 426                 if (!memory_possible)
 427                         panic("no constraint specified for assembler input");
 428         }
 429
 430         constraint->same_as               = same_as;
 431         constraint->cls                   = cls;
 432         constraint->allowed_registers     = limited;
 433         constraint->all_registers_allowed = all_registers_allowed;
 434         constraint->memory_possible       = memory_possible;
 435         constraint->immediate_type        = immediate_type;
 436 }
 437
 438 ir_node *gen_ASM(ir_node *node)
 439 {
 440         ir_node                    *block = NULL;
 441         ir_node                    *new_block = NULL;
 442         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 443         int                         i, arity;
 444         int                         out_idx;
 445         ir_node                   **in;
 446         ir_node                    *new_node;
 447         int                         out_arity;
 448         int                         n_out_constraints;
 449         int                         n_clobbers;
 450         const arch_register_req_t **out_reg_reqs;
 451         const arch_register_req_t **in_reg_reqs;
 452         ia32_asm_reg_t             *register_map;
 453         unsigned                    reg_map_size = 0;
 454         struct obstack             *obst;
 455         const ir_asm_constraint    *in_constraints;
 456         const ir_asm_constraint    *out_constraints;
 457         ident                     **clobbers;
 458         int                         clobbers_flags = 0;
 459         unsigned                    clobber_bits[N_CLASSES];
 460
 461         memset(&clobber_bits, 0, sizeof(clobber_bits));
 462
 463         switch (be_transformer) {
 464         case TRANSFORMER_DEFAULT:
 465                 block     = get_nodes_block(node);
 466                 new_block = be_transform_node(block);
 467                 break;
 468
 469 #ifdef FIRM_GRGEN_BE
 470         case TRANSFORMER_PBQP:
 471         case TRANSFORMER_RAND:
 472                 new_block = get_nodes_block(node);
 473                 break;
 474 #endif
 475
 476         default:
 477                 panic("invalid transformer");
 478         }
 479
 480         /* workaround for lots of buggy code out there as most people think volatile
 481          * asm is enough for everything and forget the flags (linux kernel, etc.)
 482          */
 483         if (get_irn_pinned(node) == op_pin_state_pinned) {
 484                 clobbers_flags = 1;
 485         }
 486
 487         arity = get_irn_arity(node);
 488         in    = ALLOCANZ(ir_node*, arity);
 489
 490         clobbers   = get_ASM_clobbers(node);
 491         n_clobbers = 0;
 492         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 493                 const arch_register_req_t *req;
 494                 const char                *c = get_id_str(clobbers[i]);
 495
 496                 if (strcmp(c, "memory") == 0)
 497                         continue;
 498                 if (strcmp(c, "cc") == 0) {
 499                         clobbers_flags = 1;
 500                         continue;
 501                 }
 502
 503                 req = parse_clobber(c);
 504                 clobber_bits[req->cls->index] |= *req->limited;
 505
 506                 n_clobbers++;
 507         }
 508         n_out_constraints = get_ASM_n_output_constraints(node);
 509         out_arity         = n_out_constraints + n_clobbers;
 510
 511         in_constraints  = get_ASM_input_constraints(node);
 512         out_constraints = get_ASM_output_constraints(node);
 513
 514         /* determine size of register_map */
 515         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 516                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 517                 if (constraint->pos > reg_map_size)
 518                         reg_map_size = constraint->pos;
 519         }
 520         for (i = 0; i < arity; ++i) {
 521                 const ir_asm_constraint   *constraint = &in_constraints[i];
 522                 if (constraint->pos > reg_map_size)
 523                         reg_map_size = constraint->pos;
 524         }
 525         ++reg_map_size;
 526
 527         obst         = get_irg_obstack(current_ir_graph);
 528         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 529         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 530
 531         /* construct output constraints */
 532         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 533
 534         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 535                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 536                 const char                *c       = get_id_str(constraint->constraint);
 537                 unsigned                   pos        = constraint->pos;
 538                 constraint_t               parsed_constraint;
 539                 const arch_register_req_t *req;
 540
 541                 parse_asm_constraints(&parsed_constraint, c, 1);
 542                 req = make_register_req(&parsed_constraint, n_out_constraints,
 543                                         out_reg_reqs, out_idx);
 544                 out_reg_reqs[out_idx] = req;
 545
 546                 register_map[pos].use_input = 0;
 547                 register_map[pos].valid     = 1;
 548                 register_map[pos].memory    = 0;
 549                 register_map[pos].inout_pos = out_idx;
 550                 register_map[pos].mode      = constraint->mode;
 551         }
 552
 553         /* inputs + input constraints */
 554         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 555         for (i = 0; i < arity; ++i) {
 556                 ir_node                   *pred         = get_irn_n(node, i);
 557                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 558                 ident                     *constr_id    = constraint->constraint;
 559                 const char                *c            = get_id_str(constr_id);
 560                 unsigned                   pos          = constraint->pos;
 561                 int                        is_memory_op = 0;
 562                 ir_node                   *input        = NULL;
 563                 unsigned                   r_clobber_bits;
 564                 constraint_t               parsed_constraint;
 565                 const arch_register_req_t *req;
 566
 567                 parse_asm_constraints(&parsed_constraint, c, 0);
 568                 if (parsed_constraint.cls != NULL) {
 569                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 570                         if (r_clobber_bits != 0) {
 571                                 if (parsed_constraint.all_registers_allowed) {
 572                                         parsed_constraint.all_registers_allowed = 0;
 573                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 574                                                         parsed_constraint.cls,
 575                                                         &parsed_constraint.allowed_registers);
 576                                 }
 577                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 578                         }
 579                 }
 580
 581                 req = make_register_req(&parsed_constraint, n_out_constraints,
 582                                         out_reg_reqs, i);
 583                 in_reg_reqs[i] = req;
 584
 585                 if (parsed_constraint.immediate_type != '\0') {
 586                         char imm_type = parsed_constraint.immediate_type;
 587                         input = try_create_Immediate(pred, imm_type);
 588                 }
 589
 590                 if (input == NULL) {
 591                         ir_node *pred = NULL;
 592                         switch (be_transformer) {
 593                         case TRANSFORMER_DEFAULT:
 594                                 pred  = get_irn_n(node, i);
 595                                 input = be_transform_node(pred);
 596                                 break;
 597
 598 #ifdef FIRM_GRGEN_BE
 599                         case TRANSFORMER_PBQP:
 600                         case TRANSFORMER_RAND:
 601                                 input = get_irn_n(node, i);
 602                                 break;
 603 #endif
 604
 605                         default: panic("invalid transformer");
 606                         }
 607
 608                         if (parsed_constraint.cls == NULL
 609                                         && parsed_constraint.same_as < 0) {
 610                                 is_memory_op = 1;
 611                         } else if (parsed_constraint.memory_possible) {
 612                                 /* TODO: match Load or Load/Store if memory possible is set */
 613                         }
 614                 }
 615                 in[i] = input;
 616
 617                 register_map[pos].use_input = 1;
 618                 register_map[pos].valid     = 1;
 619                 register_map[pos].memory    = is_memory_op;
 620                 register_map[pos].inout_pos = i;
 621                 register_map[pos].mode      = constraint->mode;
 622         }
 623
 624         /* parse clobbers */
 625         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 626                 const char                *c = get_id_str(clobbers[i]);
 627                 const arch_register_req_t *req;
 628
 629                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 630                         continue;
 631
 632                 req = parse_clobber(c);
 633                 out_reg_reqs[out_idx] = req;
 634                 ++out_idx;
 635         }
 636
 637         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 638                                    get_ASM_text(node), register_map);
 639
 640         if (arity == 0)
 641                 be_dep_on_frame(new_node);
 642
 643         set_ia32_out_req_all(new_node, out_reg_reqs);
 644         set_ia32_in_req_all(new_node, in_reg_reqs);
 645
 646         SET_IA32_ORIG_NODE(new_node, node);
 647
 648         return new_node;
 649 }
 650
 651 ir_node *gen_CopyB(ir_node *node) {
 652         ir_node  *block    = NULL;
 653         ir_node  *src      = NULL;
 654         ir_node  *new_src  = NULL;
 655         ir_node  *dst      = NULL;
 656         ir_node  *new_dst  = NULL;
 657         ir_node  *mem      = NULL;
 658         ir_node  *new_mem  = NULL;
 659         ir_node  *res      = NULL;
 660         dbg_info *dbgi     = get_irn_dbg_info(node);
 661         int      size      = get_type_size_bytes(get_CopyB_type(node));
 662         int      rem;
 663
 664         switch (be_transformer) {
 665                 case TRANSFORMER_DEFAULT:
 666                         block    = be_transform_node(get_nodes_block(node));
 667                         src      = get_CopyB_src(node);
 668                         new_src  = be_transform_node(src);
 669                         dst      = get_CopyB_dst(node);
 670                         new_dst  = be_transform_node(dst);
 671                         mem      = get_CopyB_mem(node);
 672                         new_mem  = be_transform_node(mem);
 673                         break;
 674
 675 #ifdef FIRM_GRGEN_BE
 676                 case TRANSFORMER_PBQP:
 677                 case TRANSFORMER_RAND:
 678                         block    = get_nodes_block(node);
 679                         new_src  = get_CopyB_src(node);
 680                         new_dst  = get_CopyB_dst(node);
 681                         new_mem  = get_CopyB_mem(node);
 682                         break;
 683 #endif
 684
 685                 default: panic("invalid transformer");
 686         }
 687
 688         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 689         /* then we need the size explicitly in ECX.                    */
 690         if (size >= 32 * 4) {
 691                 rem = size & 0x3; /* size % 4 */
 692                 size >>= 2;
 693
 694                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, size);
 695                 be_dep_on_frame(res);
 696
 697                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 698         } else {
 699                 if (size == 0) {
 700                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 701                                    node);
 702                 }
 703                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 704         }
 705
 706         SET_IA32_ORIG_NODE(res, node);
 707
 708         return res;
 709 }
 710
 711 ir_node *gen_Proj_tls(ir_node *node) {
 712         ir_node  *block = NULL;
 713         dbg_info *dbgi  = NULL;
 714         ir_node  *res   = NULL;
 715
 716         switch (be_transformer) {
 717                 case TRANSFORMER_DEFAULT:
 718                         block = be_transform_node(get_nodes_block(node));
 719                         break;
 720
 721 #ifdef FIRM_GRGEN_BE
 722                 case TRANSFORMER_PBQP:
 723                 case TRANSFORMER_RAND:
 724                         block = get_nodes_block(node);
 725                         break;
 726 #endif
 727
 728                 default: panic("invalid transformer");
 729         }
 730
 731         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 732
 733         return res;
 734 }
 735
 736 ir_node *gen_Unknown(ir_node *node)
 737 {
 738         ir_mode *mode = get_irn_mode(node);
 739
 740         if (mode_is_float(mode)) {
 741                 if (ia32_cg_config.use_sse2) {
 742                         return ia32_new_Unknown_xmm(env_cg);
 743                 } else {
 744                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 745                         ir_graph *irg   = current_ir_graph;
 746                         dbg_info *dbgi  = get_irn_dbg_info(node);
 747                         ir_node  *block = get_irg_start_block(irg);
 748                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 749
 750                         be_dep_on_frame(ret);
 751                         return ret;
 752                 }
 753         } else if (ia32_mode_needs_gp_reg(mode)) {
 754                 return ia32_new_Unknown_gp(env_cg);
 755         } else {
 756                 panic("unsupported Unknown-Mode");
 757         }
 758         return NULL;
 759 }
 760
 761 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 762                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 763 {
 764         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 765         int                  same_as = constraint->same_as;
 766         arch_register_req_t *req;
 767
 768         if (same_as >= 0) {
 769                 const arch_register_req_t *other_constr;
 770
 771                 if (same_as >= n_outs)
 772                         panic("invalid output number in same_as constraint");
 773
 774                 other_constr     = out_reqs[same_as];
 775
 776                 req              = obstack_alloc(obst, sizeof(req[0]));
 777                 *req             = *other_constr;
 778                 req->type       |= arch_register_req_type_should_be_same;
 779                 req->other_same  = 1U << pos;
 780
 781                 /* switch constraints. This is because in firm we have same_as
 782                  * constraints on the output constraints while in the gcc asm syntax
 783                  * they are specified on the input constraints */
 784                 out_reqs[same_as] = req;
 785                 return other_constr;
 786         }
 787
 788         /* pure memory ops */
 789         if (constraint->cls == NULL) {
 790                 return &no_register_req;
 791         }
 792
 793         if (constraint->allowed_registers != 0
 794                         && !constraint->all_registers_allowed) {
 795                 unsigned *limited_ptr;
 796
 797                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 798                 memset(req, 0, sizeof(req[0]));
 799                 limited_ptr = (unsigned*) (req+1);
 800
 801                 req->type    = arch_register_req_type_limited;
 802                 *limited_ptr = constraint->allowed_registers;
 803                 req->limited = limited_ptr;
 804         } else {
 805                 req       = obstack_alloc(obst, sizeof(req[0]));
 806                 memset(req, 0, sizeof(req[0]));
 807                 req->type = arch_register_req_type_normal;
 808         }
 809         req->cls = constraint->cls;
 810
 811         return req;
 812 }
 813
 814 const arch_register_req_t *parse_clobber(const char *clobber)
 815 {
 816         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 817         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 818         arch_register_req_t   *req;
 819         unsigned              *limited;
 820
 821         if (reg == NULL) {
 822                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 823         }
 824
 825         assert(reg->index < 32);
 826
 827         limited  = obstack_alloc(obst, sizeof(limited[0]));
 828         *limited = 1 << reg->index;
 829
 830         req          = obstack_alloc(obst, sizeof(req[0]));
 831         memset(req, 0, sizeof(req[0]));
 832         req->type    = arch_register_req_type_limited;
 833         req->cls     = arch_register_get_class(reg);
 834         req->limited = limited;
 835
 836         return req;
 837 }
 838
 839
 840 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 841                        ir_node *const other)
 842 {
 843         if (get_nodes_block(other) != block)
 844                 return 0;
 845
 846         if (is_Sync(other)) {
 847                 int i;
 848
 849                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 850                         ir_node *const pred = get_Sync_pred(other, i);
 851
 852                         if (get_nodes_block(pred) != block)
 853                                 continue;
 854
 855                         /* Do not block ourselves from getting eaten */
 856                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 857                                 continue;
 858
 859                         if (!heights_reachable_in_block(heights, pred, am_candidate))
 860                                 continue;
 861
 862                         return 1;
 863                 }
 864
 865                 return 0;
 866         } else {
 867                 /* Do not block ourselves from getting eaten */
 868                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
 869                         return 0;
 870
 871                 if (!heights_reachable_in_block(heights, other, am_candidate))
 872                         return 0;
 873
 874                 return 1;
 875         }
 876 }
 877
 878 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
 879 {
 880         int          minus         = 0;
 881         tarval      *offset        = NULL;
 882         int          offset_sign   = 0;
 883         long         val = 0;
 884         ir_entity   *symconst_ent  = NULL;
 885         int          symconst_sign = 0;
 886         ir_mode     *mode;
 887         ir_node     *cnst          = NULL;
 888         ir_node     *symconst      = NULL;
 889         ir_node     *new_node;
 890
 891         mode = get_irn_mode(node);
 892         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
 893                 return NULL;
 894         }
 895
 896         if (is_Minus(node)) {
 897                 minus = 1;
 898                 node  = get_Minus_op(node);
 899         }
 900
 901         if (is_Const(node)) {
 902                 cnst        = node;
 903                 symconst    = NULL;
 904                 offset_sign = minus;
 905         } else if (is_SymConst(node)) {
 906                 cnst          = NULL;
 907                 symconst      = node;
 908                 symconst_sign = minus;
 909         } else if (is_Add(node)) {
 910                 ir_node *left  = get_Add_left(node);
 911                 ir_node *right = get_Add_right(node);
 912                 if (is_Const(left) && is_SymConst(right)) {
 913                         cnst          = left;
 914                         symconst      = right;
 915                         symconst_sign = minus;
 916                         offset_sign   = minus;
 917                 } else if (is_SymConst(left) && is_Const(right)) {
 918                         cnst          = right;
 919                         symconst      = left;
 920                         symconst_sign = minus;
 921                         offset_sign   = minus;
 922                 }
 923         } else if (is_Sub(node)) {
 924                 ir_node *left  = get_Sub_left(node);
 925                 ir_node *right = get_Sub_right(node);
 926                 if (is_Const(left) && is_SymConst(right)) {
 927                         cnst          = left;
 928                         symconst      = right;
 929                         symconst_sign = !minus;
 930                         offset_sign   = minus;
 931                 } else if (is_SymConst(left) && is_Const(right)) {
 932                         cnst          = right;
 933                         symconst      = left;
 934                         symconst_sign = minus;
 935                         offset_sign   = !minus;
 936                 }
 937         } else {
 938                 return NULL;
 939         }
 940
 941         if (cnst != NULL) {
 942                 offset = get_Const_tarval(cnst);
 943                 if (tarval_is_long(offset)) {
 944                         val = get_tarval_long(offset);
 945                 } else {
 946                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
 947                                    "long?\n", cnst);
 948                         return NULL;
 949                 }
 950
 951                 if (!check_immediate_constraint(val, immediate_constraint_type))
 952                         return NULL;
 953         }
 954         if (symconst != NULL) {
 955                 if (immediate_constraint_type != 0) {
 956                         /* we need full 32bits for symconsts */
 957                         return NULL;
 958                 }
 959
 960                 /* unfortunately the assembler/linker doesn't support -symconst */
 961                 if (symconst_sign)
 962                         return NULL;
 963
 964                 if (get_SymConst_kind(symconst) != symconst_addr_ent)
 965                         return NULL;
 966                 symconst_ent = get_SymConst_entity(symconst);
 967         }
 968         if (cnst == NULL && symconst == NULL)
 969                 return NULL;
 970
 971         if (offset_sign && offset != NULL) {
 972                 offset = tarval_neg(offset);
 973         }
 974
 975         new_node = create_Immediate(symconst_ent, symconst_sign, val);
 976
 977         return new_node;
 978 }