nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  */
  26 #include "config.h"
  27
  28 #include "error.h"
  29 #include "ircons.h"
  30 #include "irprintf.h"
  31 #include "typerep.h"
  32 #include "bitset.h"
  33 #include "heights.h"
  34
  35 #include "betranshlp.h"
  36 #include "beirg.h"
  37 #include "beabi.h"
  38
  39 #include "ia32_architecture.h"
  40 #include "ia32_common_transform.h"
  41 #include "ia32_new_nodes.h"
  42
  43 #include "gen_ia32_new_nodes.h"
  44 #include "gen_ia32_regalloc_if.h"
  45
  46 ir_heights_t *ia32_heights = NULL;
  47
  48 static int check_immediate_constraint(long val, char immediate_constraint_type)
  49 {
  50         switch (immediate_constraint_type) {
  51                 case 0:
  52                 case 'i': return 1;
  53
  54                 case 'I': return    0 <= val && val <=  31;
  55                 case 'J': return    0 <= val && val <=  63;
  56                 case 'K': return -128 <= val && val <= 127;
  57                 case 'L': return val == 0xff || val == 0xffff;
  58                 case 'M': return    0 <= val && val <=   3;
  59                 case 'N': return    0 <= val && val <= 255;
  60                 case 'O': return    0 <= val && val <= 127;
  61
  62                 default: panic("Invalid immediate constraint found");
  63         }
  64 }
  65
  66 ir_type *ia32_get_prim_type(const ir_mode *mode)
  67 {
  68         if (mode == ia32_mode_E) {
  69                 return ia32_type_E;
  70         } else {
  71                 return get_type_for_mode(mode);
  72         }
  73 }
  74
  75 ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
  76                                           ident *name)
  77 {
  78         ir_entity        *res = (ir_entity*)pmap_get(isa->tv_ent, tv);
  79         ir_initializer_t *initializer;
  80         ir_mode          *mode;
  81         ir_type          *tp;
  82
  83         if (res != NULL)
  84                 return res;
  85
  86         mode = get_tarval_mode(tv);
  87
  88         if (! ia32_cg_config.use_sse2) {
  89                 /* try to reduce the mode to produce smaller sized entities */
  90                 if (mode != mode_F) {
  91                         if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
  92                                 mode = mode_F;
  93                                 tv = tarval_convert_to(tv, mode);
  94                         } else if (mode != mode_D) {
  95                                 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
  96                                         mode = mode_D;
  97                                         tv = tarval_convert_to(tv, mode);
  98                                 }
  99                         }
 100                 }
 101         }
 102
 103         if (name == NULL)
 104                 name = id_unique("C%u");
 105
 106         tp  = ia32_get_prim_type(mode);
 107         res = new_entity(get_glob_type(), name, tp);
 108         set_entity_ld_ident(res, get_entity_ident(res));
 109         set_entity_visibility(res, ir_visibility_private);
 110         add_entity_linkage(res, IR_LINKAGE_CONSTANT);
 111
 112         initializer = create_initializer_tarval(tv);
 113         set_entity_initializer(res, initializer);
 114
 115         pmap_insert(isa->tv_ent, tv, res);
 116         return res;
 117 }
 118
 119 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 120 {
 121         ir_graph *irg         = current_ir_graph;
 122         ir_node  *start_block = get_irg_start_block(irg);
 123         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 124                         symconst_sign, ia32_no_pic_adjust, val);
 125         arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
 126
 127         return immediate;
 128 }
 129
 130 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 131 {
 132         const arch_register_t       *reg = NULL;
 133         int                          c;
 134         size_t                       r;
 135         const arch_register_class_t *cls;
 136
 137         /* TODO: construct a hashmap instead of doing linear search for clobber
 138          * register */
 139         for (c = 0; c < N_IA32_CLASSES; ++c) {
 140                 cls = & ia32_reg_classes[c];
 141                 for (r = 0; r < cls->n_regs; ++r) {
 142                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 143                         if (strcmp(temp_reg->name, clobber) == 0
 144                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 145                                 reg = temp_reg;
 146                                 break;
 147                         }
 148                 }
 149                 if (reg != NULL)
 150                         break;
 151         }
 152
 153         return reg;
 154 }
 155
 156 int ia32_mode_needs_gp_reg(ir_mode *mode)
 157 {
 158         if (mode == ia32_mode_fpcw)
 159                 return 0;
 160         if (get_mode_size_bits(mode) > 32)
 161                 return 0;
 162         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 163 }
 164
 165 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 166                            int is_output)
 167 {
 168         char                         immediate_type     = '\0';
 169         unsigned                     limited            = 0;
 170         const arch_register_class_t *cls                = NULL;
 171         int                          memory_possible       = 0;
 172         int                          all_registers_allowed = 0;
 173         int                          p;
 174         int                          same_as = -1;
 175
 176         memset(constraint, 0, sizeof(constraint[0]));
 177         constraint->same_as = -1;
 178
 179         if (*c == 0) {
 180                 /* a memory constraint: no need to do anything in backend about it
 181                  * (the dependencies are already respected by the memory edge of
 182                  * the node) */
 183                 return;
 184         }
 185
 186         /* TODO: improve error messages with node and source info. (As users can
 187          * easily hit these) */
 188         while (*c != 0) {
 189                 switch (*c) {
 190                 case ' ':
 191                 case '\t':
 192                 case '\n':
 193                         break;
 194
 195                 /* Skip out/in-out marker */
 196                 case '=': break;
 197                 case '+': break;
 198
 199                 case '&': break;
 200
 201                 case '*':
 202                         ++c;
 203                         break;
 204                 case '#':
 205                         while (*c != 0 && *c != ',')
 206                                 ++c;
 207                         break;
 208
 209                 case 'a':
 210                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 211                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 212                         limited |= 1 << REG_GP_EAX;
 213                         break;
 214                 case 'b':
 215                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 216                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 217                         limited |= 1 << REG_GP_EBX;
 218                         break;
 219                 case 'c':
 220                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 221                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 222                         limited |= 1 << REG_GP_ECX;
 223                         break;
 224                 case 'd':
 225                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 226                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 227                         limited |= 1 << REG_GP_EDX;
 228                         break;
 229                 case 'D':
 230                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 231                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 232                         limited |= 1 << REG_GP_EDI;
 233                         break;
 234                 case 'S':
 235                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 236                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 237                         limited |= 1 << REG_GP_ESI;
 238                         break;
 239                 case 'Q':
 240                 case 'q':
 241                         /* q means lower part of the regs only, this makes no
 242                          * difference to Q for us (we only assign whole registers) */
 243                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 244                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 245                         limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
 246                                    1 << REG_GP_EDX;
 247                         break;
 248                 case 'A':
 249                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 250                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 251                         limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
 252                         break;
 253                 case 'l':
 254                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 255                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 256                         limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
 257                                    1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
 258                                    1 << REG_GP_EBP;
 259                         break;
 260
 261                 case 'R':
 262                 case 'r':
 263                 case 'p':
 264                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 265                                 panic("multiple register classes not supported");
 266                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 267                         all_registers_allowed = 1;
 268                         break;
 269
 270                 case 'f':
 271                 case 't':
 272                 case 'u':
 273                         /* TODO: mark values so the x87 simulator knows about t and u */
 274                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 275                                 panic("multiple register classes not supported");
 276                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 277                         all_registers_allowed = 1;
 278                         break;
 279
 280                 case 'Y':
 281                 case 'x':
 282                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 283                                 panic("multiple register classes not supproted");
 284                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 285                         all_registers_allowed = 1;
 286                         break;
 287
 288                 case 'I':
 289                 case 'J':
 290                 case 'K':
 291                 case 'L':
 292                 case 'M':
 293                 case 'N':
 294                 case 'O':
 295                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 296                                 panic("multiple register classes not supported");
 297                         if (immediate_type != '\0')
 298                                 panic("multiple immediate types not supported");
 299                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 300                         immediate_type = *c;
 301                         break;
 302                 case 'n':
 303                 case 'i':
 304                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 305                                 panic("multiple register classes not supported");
 306                         if (immediate_type != '\0')
 307                                 panic("multiple immediate types not supported");
 308                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 309                         immediate_type = 'i';
 310                         break;
 311
 312                 case 'X':
 313                 case 'g':
 314                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 315                                 panic("multiple register classes not supported");
 316                         if (immediate_type != '\0')
 317                                 panic("multiple immediate types not supported");
 318                         immediate_type        = 'i';
 319                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 320                         all_registers_allowed = 1;
 321                         memory_possible       = 1;
 322                         break;
 323
 324                 case '0':
 325                 case '1':
 326                 case '2':
 327                 case '3':
 328                 case '4':
 329                 case '5':
 330                 case '6':
 331                 case '7':
 332                 case '8':
 333                 case '9':
 334                         if (is_output)
 335                                 panic("can only specify same constraint on input");
 336
 337                         sscanf(c, "%d%n", &same_as, &p);
 338                         if (same_as >= 0) {
 339                                 c += p;
 340                                 continue;
 341                         }
 342                         break;
 343
 344                 case 'm':
 345                 case 'o':
 346                 case 'V':
 347                         /* memory constraint no need to do anything in backend about it
 348                          * (the dependencies are already respected by the memory edge of
 349                          * the node) */
 350                         memory_possible = 1;
 351                         break;
 352
 353                 case 'E': /* no float consts yet */
 354                 case 'F': /* no float consts yet */
 355                 case 's': /* makes no sense on x86 */
 356                 case '<': /* no autodecrement on x86 */
 357                 case '>': /* no autoincrement on x86 */
 358                 case 'C': /* sse constant not supported yet */
 359                 case 'G': /* 80387 constant not supported yet */
 360                 case 'y': /* we don't support mmx registers yet */
 361                 case 'Z': /* not available in 32 bit mode */
 362                 case 'e': /* not available in 32 bit mode */
 363                         panic("unsupported asm constraint '%c' found in (%+F)",
 364                               *c, current_ir_graph);
 365                 default:
 366                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 367                               current_ir_graph);
 368                 }
 369                 ++c;
 370         }
 371
 372         if (same_as >= 0) {
 373                 if (cls != NULL)
 374                         panic("same as and register constraint not supported");
 375                 if (immediate_type != '\0')
 376                         panic("same as and immediate constraint not supported");
 377         }
 378
 379         if (cls == NULL && same_as < 0) {
 380                 if (!memory_possible)
 381                         panic("no constraint specified for assembler input");
 382         }
 383
 384         constraint->same_as               = same_as;
 385         constraint->cls                   = cls;
 386         constraint->allowed_registers     = limited;
 387         constraint->all_registers_allowed = all_registers_allowed;
 388         constraint->memory_possible       = memory_possible;
 389         constraint->immediate_type        = immediate_type;
 390 }
 391
 392 static bool can_match(const arch_register_req_t *in,
 393                       const arch_register_req_t *out)
 394 {
 395         if (in->cls != out->cls)
 396                 return false;
 397         if ( (in->type & arch_register_req_type_limited) == 0
 398                 || (out->type & arch_register_req_type_limited) == 0 )
 399                 return true;
 400
 401         return (*in->limited & *out->limited) != 0;
 402 }
 403
 404 static inline ir_node *get_new_node(ir_node *node)
 405 {
 406 #ifdef FIRM_GRGEN_BE
 407         if (be_transformer == TRANSFORMER_DEFAULT) {
 408                 return be_transform_node(node);
 409         } else {
 410                 return node;
 411         }
 412 #else
 413         return be_transform_node(node);
 414 #endif
 415 }
 416
 417 ir_node *ia32_gen_ASM(ir_node *node)
 418 {
 419         ir_node                    *block     = get_nodes_block(node);
 420         ir_node                    *new_block = get_new_node(block);
 421         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 422         int                         i, arity;
 423         int                         value_arity;
 424         int                         out_idx;
 425         ir_node                   **in;
 426         ir_node                    *new_node;
 427         int                         out_arity;
 428         int                         n_out_constraints;
 429         int                         n_clobbers;
 430         const arch_register_req_t **out_reg_reqs;
 431         const arch_register_req_t **in_reg_reqs;
 432         ia32_asm_reg_t             *register_map;
 433         unsigned                    reg_map_size = 0;
 434         struct obstack             *obst;
 435         const ir_asm_constraint    *in_constraints;
 436         const ir_asm_constraint    *out_constraints;
 437         ident                     **clobbers;
 438         unsigned                    clobber_bits[N_IA32_CLASSES];
 439         int                         out_size;
 440         backend_info_t             *info;
 441
 442         memset(&clobber_bits, 0, sizeof(clobber_bits));
 443
 444         arity = get_irn_arity(node);
 445         in    = ALLOCANZ(ir_node*, arity);
 446
 447         clobbers   = get_ASM_clobbers(node);
 448         n_clobbers = 0;
 449         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 450                 const arch_register_req_t *req;
 451                 const char                *c = get_id_str(clobbers[i]);
 452
 453                 if (strcmp(c, "memory") == 0)
 454                         continue;
 455                 if (strcmp(c, "cc") == 0) {
 456                         continue;
 457                 }
 458
 459                 req = ia32_parse_clobber(c);
 460                 clobber_bits[req->cls->index] |= *req->limited;
 461
 462                 n_clobbers++;
 463         }
 464         n_out_constraints = get_ASM_n_output_constraints(node);
 465         out_arity         = n_out_constraints + n_clobbers;
 466
 467         in_constraints  = get_ASM_input_constraints(node);
 468         out_constraints = get_ASM_output_constraints(node);
 469
 470         /* determine size of register_map */
 471         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 472                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 473                 if (constraint->pos > reg_map_size)
 474                         reg_map_size = constraint->pos;
 475         }
 476         for (i = 0; i < arity; ++i) {
 477                 const ir_asm_constraint *constraint = &in_constraints[i];
 478                 if (constraint->pos > reg_map_size)
 479                         reg_map_size = constraint->pos;
 480         }
 481         ++reg_map_size;
 482
 483         obst         = get_irg_obstack(current_ir_graph);
 484         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 485         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 486
 487         /* construct output constraints */
 488         out_size = out_arity + 1;
 489         out_reg_reqs = OALLOCN(obst, const arch_register_req_t*, out_size);
 490
 491         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 492                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 493                 const char                *c       = get_id_str(constraint->constraint);
 494                 unsigned                   pos     = constraint->pos;
 495                 constraint_t               parsed_constraint;
 496                 const arch_register_req_t *req;
 497
 498                 parse_asm_constraints(&parsed_constraint, c, 1);
 499                 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
 500                                         out_reg_reqs, out_idx);
 501                 out_reg_reqs[out_idx] = req;
 502
 503                 /* multiple constraints for same pos. This can happen for example when
 504                  * a =A constraint gets lowered to two constraints: =a and =d for the
 505                  * same pos */
 506                 if (register_map[pos].valid)
 507                         continue;
 508
 509                 register_map[pos].use_input = 0;
 510                 register_map[pos].valid     = 1;
 511                 register_map[pos].memory    = 0;
 512                 register_map[pos].inout_pos = out_idx;
 513                 register_map[pos].mode      = constraint->mode;
 514         }
 515
 516         /* inputs + input constraints */
 517         in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, arity);
 518         for (i = 0; i < arity; ++i) {
 519                 ir_node                   *pred         = get_irn_n(node, i);
 520                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 521                 ident                     *constr_id    = constraint->constraint;
 522                 const char                *c            = get_id_str(constr_id);
 523                 unsigned                   pos          = constraint->pos;
 524                 int                        is_memory_op = 0;
 525                 ir_node                   *input        = NULL;
 526                 unsigned                   r_clobber_bits;
 527                 constraint_t               parsed_constraint;
 528                 const arch_register_req_t *req;
 529
 530                 parse_asm_constraints(&parsed_constraint, c, 0);
 531                 if (parsed_constraint.cls != NULL) {
 532                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 533                         if (r_clobber_bits != 0) {
 534                                 if (parsed_constraint.all_registers_allowed) {
 535                                         parsed_constraint.all_registers_allowed = 0;
 536                                         be_set_allocatable_regs(current_ir_graph,
 537                                                         parsed_constraint.cls,
 538                                                         &parsed_constraint.allowed_registers);
 539                                 }
 540                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 541                         }
 542                 }
 543
 544                 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
 545                                         out_reg_reqs, i);
 546                 in_reg_reqs[i] = req;
 547
 548                 if (parsed_constraint.immediate_type != '\0') {
 549                         char imm_type = parsed_constraint.immediate_type;
 550                         input = ia32_try_create_Immediate(pred, imm_type);
 551                 }
 552
 553                 if (input == NULL) {
 554                         input = get_new_node(pred);
 555
 556                         if (parsed_constraint.cls == NULL
 557                                         && parsed_constraint.same_as < 0) {
 558                                 is_memory_op = 1;
 559                         } else if (parsed_constraint.memory_possible) {
 560                                 /* TODO: match Load or Load/Store if memory possible is set */
 561                         }
 562                 }
 563                 in[i] = input;
 564
 565                 register_map[pos].use_input = 1;
 566                 register_map[pos].valid     = 1;
 567                 register_map[pos].memory    = is_memory_op;
 568                 register_map[pos].inout_pos = i;
 569                 register_map[pos].mode      = constraint->mode;
 570         }
 571
 572         /* parse clobbers */
 573         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 574                 const char                *c = get_id_str(clobbers[i]);
 575                 const arch_register_req_t *req;
 576
 577                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 578                         continue;
 579
 580                 req = ia32_parse_clobber(c);
 581                 out_reg_reqs[out_idx] = req;
 582                 ++out_idx;
 583         }
 584
 585         /* count inputs which are real values (and not memory) */
 586         value_arity = 0;
 587         for (i = 0; i < arity; ++i) {
 588                 ir_node *node_in = get_irn_n(node, i);
 589                 if (get_irn_mode(node_in) == mode_M)
 590                         continue;
 591                 ++value_arity;
 592         }
 593
 594         /* Attempt to make ASM node register pressure faithful.
 595          * (This does not work for complicated cases yet!)
 596          *
 597          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 598          * the smaller list). Then try to match each constraint of the smaller list
 599          * to 1 of the other list. If we can't match it, then we have to add a dummy
 600          * input/output to the other list
 601          *
 602          * FIXME: This is still broken in lots of cases. But at least better than
 603          *        before...
 604          * FIXME: need to do this per register class...
 605          */
 606         if (out_arity <= value_arity) {
 607                 int       orig_arity = arity;
 608                 int       in_size    = arity;
 609                 int       o;
 610                 bitset_t *used_ins = bitset_alloca(arity);
 611                 for (o = 0; o < out_arity; ++o) {
 612                         const arch_register_req_t *outreq = out_reg_reqs[o];
 613
 614                         if (outreq->cls == NULL) {
 615                                 continue;
 616                         }
 617
 618                         for (i = 0; i < orig_arity; ++i) {
 619                                 const arch_register_req_t *inreq;
 620                                 if (bitset_is_set(used_ins, i))
 621                                         continue;
 622                                 inreq = in_reg_reqs[i];
 623                                 if (!can_match(outreq, inreq))
 624                                         continue;
 625                                 bitset_set(used_ins, i);
 626                                 break;
 627                         }
 628                         /* did we find any match? */
 629                         if (i < orig_arity)
 630                                 continue;
 631
 632                         /* we might need more space in the input arrays */
 633                         if (arity >= in_size) {
 634                                 const arch_register_req_t **new_in_reg_reqs;
 635                                 ir_node             **new_in;
 636
 637                                 in_size *= 2;
 638                                 new_in_reg_reqs = OALLOCN(obst, const arch_register_req_t*,
 639                                                           in_size);
 640                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 641                                 new_in = ALLOCANZ(ir_node*, in_size);
 642                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 643
 644                                 in_reg_reqs = new_in_reg_reqs;
 645                                 in          = new_in;
 646                         }
 647
 648                         /* add a new (dummy) input which occupies the register */
 649                         assert(outreq->type & arch_register_req_type_limited);
 650                         in_reg_reqs[arity] = outreq;
 651                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 652                         ++arity;
 653                 }
 654         } else {
 655                 bitset_t *used_outs = bitset_alloca(out_arity);
 656                 int       orig_out_arity = out_arity;
 657                 for (i = 0; i < arity; ++i) {
 658                         int   o;
 659                         const arch_register_req_t *inreq = in_reg_reqs[i];
 660
 661                         if (inreq->cls == NULL) {
 662                                 continue;
 663                         }
 664
 665                         for (o = 0; o < orig_out_arity; ++o) {
 666                                 const arch_register_req_t *outreq;
 667                                 if (bitset_is_set(used_outs, o))
 668                                         continue;
 669                                 outreq = out_reg_reqs[o];
 670                                 if (!can_match(outreq, inreq))
 671                                         continue;
 672                                 bitset_set(used_outs, i);
 673                                 break;
 674                         }
 675                         /* did we find any match? */
 676                         if (o < orig_out_arity)
 677                                 continue;
 678
 679                         /* we might need more space in the output arrays */
 680                         if (out_arity >= out_size) {
 681                                 const arch_register_req_t **new_out_reg_reqs;
 682
 683                                 out_size *= 2;
 684                                 new_out_reg_reqs
 685                                         = OALLOCN(obst, const arch_register_req_t*, out_size);
 686                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 687                                        out_arity * sizeof(new_out_reg_reqs[0]));
 688                                 out_reg_reqs = new_out_reg_reqs;
 689                         }
 690
 691                         /* add a new (dummy) output which occupies the register */
 692                         assert(inreq->type & arch_register_req_type_limited);
 693                         out_reg_reqs[out_arity] = inreq;
 694                         ++out_arity;
 695                 }
 696         }
 697
 698         /* append none register requirement for the memory output */
 699         if (out_arity + 1 >= out_size) {
 700                 const arch_register_req_t **new_out_reg_reqs;
 701
 702                 out_size = out_arity + 1;
 703                 new_out_reg_reqs
 704                         = OALLOCN(obst, const arch_register_req_t*, out_size);
 705                 memcpy(new_out_reg_reqs, out_reg_reqs,
 706                            out_arity * sizeof(new_out_reg_reqs[0]));
 707                 out_reg_reqs = new_out_reg_reqs;
 708         }
 709
 710         /* add a new (dummy) output which occupies the register */
 711         out_reg_reqs[out_arity] = arch_no_register_req;
 712         ++out_arity;
 713
 714         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 715                                    get_ASM_text(node), register_map);
 716
 717         info = be_get_info(new_node);
 718         for (i = 0; i < out_arity; ++i) {
 719                 info->out_infos[i].req = out_reg_reqs[i];
 720         }
 721         arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
 722
 723         SET_IA32_ORIG_NODE(new_node, node);
 724
 725         return new_node;
 726 }
 727
 728 ir_node *ia32_gen_CopyB(ir_node *node)
 729 {
 730         ir_node  *block    = get_new_node(get_nodes_block(node));
 731         ir_node  *src      = get_CopyB_src(node);
 732         ir_node  *new_src  = get_new_node(src);
 733         ir_node  *dst      = get_CopyB_dst(node);
 734         ir_node  *new_dst  = get_new_node(dst);
 735         ir_node  *mem      = get_CopyB_mem(node);
 736         ir_node  *new_mem  = get_new_node(mem);
 737         ir_node  *res      = NULL;
 738         dbg_info *dbgi     = get_irn_dbg_info(node);
 739         int      size      = get_type_size_bytes(get_CopyB_type(node));
 740         int      throws_exception = ir_throws_exception(node);
 741         int      rem;
 742
 743         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 744         /* then we need the size explicitly in ECX.                    */
 745         if (size >= 32 * 4) {
 746                 rem = size & 0x3; /* size % 4 */
 747                 size >>= 2;
 748
 749                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 750
 751                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 752         } else {
 753                 if (size == 0) {
 754                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 755                                    node);
 756                 }
 757                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 758         }
 759         ir_set_throws_exception(res, throws_exception);
 760
 761         SET_IA32_ORIG_NODE(res, node);
 762
 763         return res;
 764 }
 765
 766 ir_node *ia32_gen_Proj_tls(ir_node *node)
 767 {
 768         ir_node *block = get_new_node(get_nodes_block(node));
 769         ir_node *res   = new_bd_ia32_LdTls(NULL, block);
 770         return res;
 771 }
 772
 773 ir_node *ia32_gen_Unknown(ir_node *node)
 774 {
 775         ir_mode  *mode  = get_irn_mode(node);
 776         ir_graph *irg   = current_ir_graph;
 777         dbg_info *dbgi  = get_irn_dbg_info(node);
 778         ir_node  *block = get_irg_start_block(irg);
 779         ir_node  *res   = NULL;
 780
 781         if (mode_is_float(mode)) {
 782                 if (ia32_cg_config.use_sse2) {
 783                         res = new_bd_ia32_xUnknown(dbgi, block);
 784                 } else {
 785                         res = new_bd_ia32_vfldz(dbgi, block);
 786                 }
 787         } else if (ia32_mode_needs_gp_reg(mode)) {
 788                 res = new_bd_ia32_Unknown(dbgi, block);
 789         } else {
 790                 panic("unsupported Unknown-Mode");
 791         }
 792
 793         return res;
 794 }
 795
 796 const arch_register_req_t *ia32_make_register_req(const constraint_t *constraint,
 797                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 798 {
 799         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 800         int                  same_as = constraint->same_as;
 801         arch_register_req_t *req;
 802
 803         if (same_as >= 0) {
 804                 const arch_register_req_t *other_constr;
 805
 806                 if (same_as >= n_outs)
 807                         panic("invalid output number in same_as constraint");
 808
 809                 other_constr     = out_reqs[same_as];
 810
 811                 req              = OALLOC(obst, arch_register_req_t);
 812                 *req             = *other_constr;
 813                 req->type       |= arch_register_req_type_should_be_same;
 814                 req->other_same  = 1U << pos;
 815                 req->width       = 1;
 816
 817                 /* switch constraints. This is because in firm we have same_as
 818                  * constraints on the output constraints while in the gcc asm syntax
 819                  * they are specified on the input constraints */
 820                 out_reqs[same_as] = req;
 821                 return other_constr;
 822         }
 823
 824         /* pure memory ops */
 825         if (constraint->cls == NULL) {
 826                 return arch_no_register_req;
 827         }
 828
 829         if (constraint->allowed_registers != 0
 830                         && !constraint->all_registers_allowed) {
 831                 unsigned *limited_ptr;
 832
 833                 req         = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 834                 memset(req, 0, sizeof(req[0]));
 835                 limited_ptr = (unsigned*) (req+1);
 836
 837                 req->type    = arch_register_req_type_limited;
 838                 *limited_ptr = constraint->allowed_registers;
 839                 req->limited = limited_ptr;
 840         } else {
 841                 req       = OALLOCZ(obst, arch_register_req_t);
 842                 req->type = arch_register_req_type_normal;
 843         }
 844         req->cls   = constraint->cls;
 845         req->width = 1;
 846
 847         return req;
 848 }
 849
 850 const arch_register_req_t *ia32_parse_clobber(const char *clobber)
 851 {
 852         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 853         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 854         arch_register_req_t   *req;
 855         unsigned              *limited;
 856
 857         if (reg == NULL) {
 858                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 859         }
 860
 861         assert(reg->index < 32);
 862
 863         limited  = OALLOC(obst, unsigned);
 864         *limited = 1 << reg->index;
 865
 866         req          = OALLOCZ(obst, arch_register_req_t);
 867         req->type    = arch_register_req_type_limited;
 868         req->cls     = arch_register_get_class(reg);
 869         req->limited = limited;
 870         req->width   = 1;
 871
 872         return req;
 873 }
 874
 875
 876 int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
 877                        ir_node *const other)
 878 {
 879         if (get_nodes_block(other) != block)
 880                 return 0;
 881
 882         if (is_Sync(other)) {
 883                 int i;
 884
 885                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 886                         ir_node *const pred = get_Sync_pred(other, i);
 887
 888                         if (get_nodes_block(pred) != block)
 889                                 continue;
 890
 891                         /* Do not block ourselves from getting eaten */
 892                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 893                                 continue;
 894
 895                         if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
 896                                 continue;
 897
 898                         return 1;
 899                 }
 900
 901                 return 0;
 902         } else {
 903                 /* Do not block ourselves from getting eaten */
 904                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
 905                         return 0;
 906
 907                 if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
 908                         return 0;
 909
 910                 return 1;
 911         }
 912 }
 913
 914 ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
 915 {
 916         long       val = 0;
 917         ir_entity *symconst_ent  = NULL;
 918         ir_mode   *mode;
 919         ir_node   *cnst          = NULL;
 920         ir_node   *symconst      = NULL;
 921         ir_node   *new_node;
 922
 923         mode = get_irn_mode(node);
 924         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
 925                 return NULL;
 926         }
 927
 928         if (is_Const(node)) {
 929                 cnst     = node;
 930                 symconst = NULL;
 931         } else if (is_SymConst_addr_ent(node)
 932                         && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
 933                 cnst     = NULL;
 934                 symconst = node;
 935         } else if (is_Add(node)) {
 936                 ir_node *left  = get_Add_left(node);
 937                 ir_node *right = get_Add_right(node);
 938                 if (is_Const(left) && is_SymConst_addr_ent(right)) {
 939                         cnst     = left;
 940                         symconst = right;
 941                 } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
 942                         cnst     = right;
 943                         symconst = left;
 944                 }
 945         } else {
 946                 return NULL;
 947         }
 948
 949         if (cnst != NULL) {
 950                 ir_tarval *offset = get_Const_tarval(cnst);
 951                 if (!tarval_is_long(offset)) {
 952                         ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
 953                         return NULL;
 954                 }
 955
 956                 val = get_tarval_long(offset);
 957                 if (!check_immediate_constraint(val, immediate_constraint_type))
 958                         return NULL;
 959         }
 960         if (symconst != NULL) {
 961                 if (immediate_constraint_type != 0) {
 962                         /* we need full 32bits for symconsts */
 963                         return NULL;
 964                 }
 965
 966                 symconst_ent = get_SymConst_entity(symconst);
 967         }
 968         if (cnst == NULL && symconst == NULL)
 969                 return NULL;
 970
 971         new_node = ia32_create_Immediate(symconst_ent, 0, val);
 972         return new_node;
 973 }