nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33 #include "bitset.h"
  34
  35 #include "../betranshlp.h"
  36 #include "../beirg.h"
  37 #include "../beabi.h"
  38
  39 #include "ia32_architecture.h"
  40 #include "ia32_common_transform.h"
  41 #include "ia32_new_nodes.h"
  42
  43 #include "gen_ia32_new_nodes.h"
  44 #include "gen_ia32_regalloc_if.h"
  45
  46 /** hold the current code generator during transformation */
  47 ia32_code_gen_t *env_cg = NULL;
  48
  49 heights_t *heights = NULL;
  50
  51 static const arch_register_req_t no_register_req = {
  52         arch_register_req_type_none,
  53         NULL,                         /* regclass */
  54         NULL,                         /* limit bitset */
  55         0,                            /* same pos */
  56         0                             /* different pos */
  57 };
  58
  59 static int check_immediate_constraint(long val, char immediate_constraint_type)
  60 {
  61         switch (immediate_constraint_type) {
  62                 case 0:
  63                 case 'i': return 1;
  64
  65                 case 'I': return    0 <= val && val <=  31;
  66                 case 'J': return    0 <= val && val <=  63;
  67                 case 'K': return -128 <= val && val <= 127;
  68                 case 'L': return val == 0xff || val == 0xffff;
  69                 case 'M': return    0 <= val && val <=   3;
  70                 case 'N': return    0 <= val && val <= 255;
  71                 case 'O': return    0 <= val && val <= 127;
  72
  73                 default: panic("Invalid immediate constraint found");
  74         }
  75 }
  76
  77 /* creates a unique ident by adding a number to a tag */
  78 ident *ia32_unique_id(const char *tag)
  79 {
  80         static unsigned id = 0;
  81         char str[256];
  82
  83         snprintf(str, sizeof(str), tag, ++id);
  84         return new_id_from_str(str);
  85 }
  86
  87 /**
  88  * Get a primitive type for a mode with alignment 16.
  89  */
  90 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  91 {
  92         pmap_entry *e = pmap_find(types, mode);
  93         ir_type *res;
  94
  95         if (! e) {
  96                 res = new_type_primitive(mode);
  97                 if (get_mode_size_bits(mode) >= 80) {
  98                         set_type_alignment_bytes(res, 16);
  99                 }
 100                 pmap_insert(types, mode, res);
 101         }
 102         else
 103                 res = e->value;
 104         return res;
 105 }
 106
 107 ir_entity *create_float_const_entity(ir_node *cnst)
 108 {
 109         ia32_isa_t *isa = env_cg->isa;
 110         tarval *key     = get_Const_tarval(cnst);
 111         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 112         ir_entity *res;
 113         ir_graph *rem;
 114
 115         if (e == NULL) {
 116                 tarval  *tv   = key;
 117                 ir_mode *mode = get_tarval_mode(tv);
 118                 ir_type *tp;
 119
 120                 if (! ia32_cg_config.use_sse2) {
 121                         /* try to reduce the mode to produce smaller sized entities */
 122                         if (mode != mode_F) {
 123                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 124                                         mode = mode_F;
 125                                         tv = tarval_convert_to(tv, mode);
 126                                 } else if (mode != mode_D) {
 127                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 128                                                 mode = mode_D;
 129                                                 tv = tarval_convert_to(tv, mode);
 130                                         }
 131                                 }
 132                         }
 133                 }
 134
 135                 if (mode == get_irn_mode(cnst)) {
 136                         /* mode was not changed */
 137                         tp = get_Const_type(cnst);
 138                         if (tp == firm_unknown_type)
 139                                 tp = ia32_get_prim_type(isa->types, mode);
 140                 } else
 141                         tp = ia32_get_prim_type(isa->types, mode);
 142
 143                 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
 144
 145                 set_entity_ld_ident(res, get_entity_ident(res));
 146                 set_entity_visibility(res, ir_visibility_local);
 147                 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
 148
 149                  /* we create a new entity here: It's initialization must resist on the
 150                     const code irg */
 151                 rem = current_ir_graph;
 152                 current_ir_graph = get_const_code_irg();
 153                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 154                 current_ir_graph = rem;
 155
 156                 pmap_insert(isa->tv_ent, key, res);
 157         } else {
 158                 res = e->value;
 159         }
 160
 161         return res;
 162 }
 163
 164 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 165 {
 166         ir_graph *irg         = current_ir_graph;
 167         ir_node  *start_block = get_irg_start_block(irg);
 168         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 169                         symconst_sign, no_pic_adjust, val);
 170         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 171
 172         return immediate;
 173 }
 174
 175 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 176 {
 177         const arch_register_t       *reg = NULL;
 178         int                          c;
 179         size_t                       r;
 180         const arch_register_class_t *cls;
 181
 182         /* TODO: construct a hashmap instead of doing linear search for clobber
 183          * register */
 184         for (c = 0; c < N_CLASSES; ++c) {
 185                 cls = & ia32_reg_classes[c];
 186                 for (r = 0; r < cls->n_regs; ++r) {
 187                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 188                         if (strcmp(temp_reg->name, clobber) == 0
 189                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 190                                 reg = temp_reg;
 191                                 break;
 192                         }
 193                 }
 194                 if (reg != NULL)
 195                         break;
 196         }
 197
 198         return reg;
 199 }
 200
 201 int ia32_mode_needs_gp_reg(ir_mode *mode)
 202 {
 203         if (mode == mode_fpcw)
 204                 return 0;
 205         if (get_mode_size_bits(mode) > 32)
 206                 return 0;
 207         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 208 }
 209
 210 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 211                            int is_output)
 212 {
 213         char                         immediate_type     = '\0';
 214         unsigned                     limited            = 0;
 215         const arch_register_class_t *cls                = NULL;
 216         int                          memory_possible       = 0;
 217         int                          all_registers_allowed = 0;
 218         int                          p;
 219         int                          same_as = -1;
 220
 221         memset(constraint, 0, sizeof(constraint[0]));
 222         constraint->same_as = -1;
 223
 224         if (*c == 0) {
 225                 /* a memory constraint: no need to do anything in backend about it
 226                  * (the dependencies are already respected by the memory edge of
 227                  * the node) */
 228                 return;
 229         }
 230
 231         /* TODO: improve error messages with node and source info. (As users can
 232          * easily hit these) */
 233         while (*c != 0) {
 234                 switch (*c) {
 235                 case ' ':
 236                 case '\t':
 237                 case '\n':
 238                         break;
 239
 240                 /* Skip out/in-out marker */
 241                 case '=': break;
 242                 case '+': break;
 243
 244                 case '&': break;
 245
 246                 case '*':
 247                         ++c;
 248                         break;
 249                 case '#':
 250                         while (*c != 0 && *c != ',')
 251                                 ++c;
 252                         break;
 253
 254                 case 'a':
 255                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 256                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 257                         limited |= 1 << REG_EAX;
 258                         break;
 259                 case 'b':
 260                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 261                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 262                         limited |= 1 << REG_EBX;
 263                         break;
 264                 case 'c':
 265                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 266                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 267                         limited |= 1 << REG_ECX;
 268                         break;
 269                 case 'd':
 270                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 271                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 272                         limited |= 1 << REG_EDX;
 273                         break;
 274                 case 'D':
 275                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 276                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 277                         limited |= 1 << REG_EDI;
 278                         break;
 279                 case 'S':
 280                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 281                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 282                         limited |= 1 << REG_ESI;
 283                         break;
 284                 case 'Q':
 285                 case 'q':
 286                         /* q means lower part of the regs only, this makes no
 287                          * difference to Q for us (we only assign whole registers) */
 288                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 289                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 290                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 291                                    1 << REG_EDX;
 292                         break;
 293                 case 'A':
 294                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 295                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 296                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 297                         break;
 298                 case 'l':
 299                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 300                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 301                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 302                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 303                                    1 << REG_EBP;
 304                         break;
 305
 306                 case 'R':
 307                 case 'r':
 308                 case 'p':
 309                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 310                                 panic("multiple register classes not supported");
 311                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 312                         all_registers_allowed = 1;
 313                         break;
 314
 315                 case 'f':
 316                 case 't':
 317                 case 'u':
 318                         /* TODO: mark values so the x87 simulator knows about t and u */
 319                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 320                                 panic("multiple register classes not supported");
 321                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 322                         all_registers_allowed = 1;
 323                         break;
 324
 325                 case 'Y':
 326                 case 'x':
 327                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 328                                 panic("multiple register classes not supproted");
 329                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 330                         all_registers_allowed = 1;
 331                         break;
 332
 333                 case 'I':
 334                 case 'J':
 335                 case 'K':
 336                 case 'L':
 337                 case 'M':
 338                 case 'N':
 339                 case 'O':
 340                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 341                                 panic("multiple register classes not supported");
 342                         if (immediate_type != '\0')
 343                                 panic("multiple immediate types not supported");
 344                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 345                         immediate_type = *c;
 346                         break;
 347                 case 'n':
 348                 case 'i':
 349                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 350                                 panic("multiple register classes not supported");
 351                         if (immediate_type != '\0')
 352                                 panic("multiple immediate types not supported");
 353                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 354                         immediate_type = 'i';
 355                         break;
 356
 357                 case 'X':
 358                 case 'g':
 359                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 360                                 panic("multiple register classes not supported");
 361                         if (immediate_type != '\0')
 362                                 panic("multiple immediate types not supported");
 363                         immediate_type        = 'i';
 364                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 365                         all_registers_allowed = 1;
 366                         memory_possible       = 1;
 367                         break;
 368
 369                 case '0':
 370                 case '1':
 371                 case '2':
 372                 case '3':
 373                 case '4':
 374                 case '5':
 375                 case '6':
 376                 case '7':
 377                 case '8':
 378                 case '9':
 379                         if (is_output)
 380                                 panic("can only specify same constraint on input");
 381
 382                         sscanf(c, "%d%n", &same_as, &p);
 383                         if (same_as >= 0) {
 384                                 c += p;
 385                                 continue;
 386                         }
 387                         break;
 388
 389                 case 'm':
 390                 case 'o':
 391                 case 'V':
 392                         /* memory constraint no need to do anything in backend about it
 393                          * (the dependencies are already respected by the memory edge of
 394                          * the node) */
 395                         memory_possible = 1;
 396                         break;
 397
 398                 case 'E': /* no float consts yet */
 399                 case 'F': /* no float consts yet */
 400                 case 's': /* makes no sense on x86 */
 401                 case '<': /* no autodecrement on x86 */
 402                 case '>': /* no autoincrement on x86 */
 403                 case 'C': /* sse constant not supported yet */
 404                 case 'G': /* 80387 constant not supported yet */
 405                 case 'y': /* we don't support mmx registers yet */
 406                 case 'Z': /* not available in 32 bit mode */
 407                 case 'e': /* not available in 32 bit mode */
 408                         panic("unsupported asm constraint '%c' found in (%+F)",
 409                               *c, current_ir_graph);
 410                         break;
 411                 default:
 412                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 413                               current_ir_graph);
 414                         break;
 415                 }
 416                 ++c;
 417         }
 418
 419         if (same_as >= 0) {
 420                 if (cls != NULL)
 421                         panic("same as and register constraint not supported");
 422                 if (immediate_type != '\0')
 423                         panic("same as and immediate constraint not supported");
 424         }
 425
 426         if (cls == NULL && same_as < 0) {
 427                 if (!memory_possible)
 428                         panic("no constraint specified for assembler input");
 429         }
 430
 431         constraint->same_as               = same_as;
 432         constraint->cls                   = cls;
 433         constraint->allowed_registers     = limited;
 434         constraint->all_registers_allowed = all_registers_allowed;
 435         constraint->memory_possible       = memory_possible;
 436         constraint->immediate_type        = immediate_type;
 437 }
 438
 439 static bool can_match(const arch_register_req_t *in,
 440                       const arch_register_req_t *out)
 441 {
 442         if (in->cls != out->cls)
 443                 return false;
 444         if ( (in->type & arch_register_req_type_limited) == 0
 445                 || (out->type & arch_register_req_type_limited) == 0 )
 446                 return true;
 447
 448         return (*in->limited & *out->limited) != 0;
 449 }
 450
 451 ir_node *gen_ASM(ir_node *node)
 452 {
 453         ir_node                    *block = NULL;
 454         ir_node                    *new_block = NULL;
 455         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 456         int                         i, arity;
 457         int                         out_idx;
 458         ir_node                   **in;
 459         ir_node                    *new_node;
 460         int                         out_arity;
 461         int                         n_out_constraints;
 462         int                         n_clobbers;
 463         const arch_register_req_t **out_reg_reqs;
 464         const arch_register_req_t **in_reg_reqs;
 465         ia32_asm_reg_t             *register_map;
 466         unsigned                    reg_map_size = 0;
 467         struct obstack             *obst;
 468         const ir_asm_constraint    *in_constraints;
 469         const ir_asm_constraint    *out_constraints;
 470         ident                     **clobbers;
 471         int                         clobbers_flags = 0;
 472         unsigned                    clobber_bits[N_CLASSES];
 473         int                         out_size;
 474         backend_info_t             *info;
 475
 476         memset(&clobber_bits, 0, sizeof(clobber_bits));
 477
 478         switch (be_transformer) {
 479         case TRANSFORMER_DEFAULT:
 480                 block     = get_nodes_block(node);
 481                 new_block = be_transform_node(block);
 482                 break;
 483
 484 #ifdef FIRM_GRGEN_BE
 485         case TRANSFORMER_PBQP:
 486         case TRANSFORMER_RAND:
 487                 new_block = get_nodes_block(node);
 488                 break;
 489 #endif
 490
 491         default:
 492                 panic("invalid transformer");
 493         }
 494
 495         /* workaround for lots of buggy code out there as most people think volatile
 496          * asm is enough for everything and forget the flags (linux kernel, etc.)
 497          */
 498         if (get_irn_pinned(node) == op_pin_state_pinned) {
 499                 clobbers_flags = 1;
 500         }
 501
 502         arity = get_irn_arity(node);
 503         in    = ALLOCANZ(ir_node*, arity);
 504
 505         clobbers   = get_ASM_clobbers(node);
 506         n_clobbers = 0;
 507         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 508                 const arch_register_req_t *req;
 509                 const char                *c = get_id_str(clobbers[i]);
 510
 511                 if (strcmp(c, "memory") == 0)
 512                         continue;
 513                 if (strcmp(c, "cc") == 0) {
 514                         clobbers_flags = 1;
 515                         continue;
 516                 }
 517
 518                 req = parse_clobber(c);
 519                 clobber_bits[req->cls->index] |= *req->limited;
 520
 521                 n_clobbers++;
 522         }
 523         n_out_constraints = get_ASM_n_output_constraints(node);
 524         out_arity         = n_out_constraints + n_clobbers;
 525
 526         in_constraints  = get_ASM_input_constraints(node);
 527         out_constraints = get_ASM_output_constraints(node);
 528
 529         /* determine size of register_map */
 530         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 531                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 532                 if (constraint->pos > reg_map_size)
 533                         reg_map_size = constraint->pos;
 534         }
 535         for (i = 0; i < arity; ++i) {
 536                 const ir_asm_constraint   *constraint = &in_constraints[i];
 537                 if (constraint->pos > reg_map_size)
 538                         reg_map_size = constraint->pos;
 539         }
 540         ++reg_map_size;
 541
 542         obst         = get_irg_obstack(current_ir_graph);
 543         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 544         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 545
 546         /* construct output constraints */
 547         out_size = out_arity + 1;
 548         out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
 549
 550         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 551                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 552                 const char                *c       = get_id_str(constraint->constraint);
 553                 unsigned                   pos        = constraint->pos;
 554                 constraint_t               parsed_constraint;
 555                 const arch_register_req_t *req;
 556
 557                 parse_asm_constraints(&parsed_constraint, c, 1);
 558                 req = make_register_req(&parsed_constraint, n_out_constraints,
 559                                         out_reg_reqs, out_idx);
 560                 out_reg_reqs[out_idx] = req;
 561
 562                 register_map[pos].use_input = 0;
 563                 register_map[pos].valid     = 1;
 564                 register_map[pos].memory    = 0;
 565                 register_map[pos].inout_pos = out_idx;
 566                 register_map[pos].mode      = constraint->mode;
 567         }
 568
 569         /* inputs + input constraints */
 570         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 571         for (i = 0; i < arity; ++i) {
 572                 ir_node                   *pred         = get_irn_n(node, i);
 573                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 574                 ident                     *constr_id    = constraint->constraint;
 575                 const char                *c            = get_id_str(constr_id);
 576                 unsigned                   pos          = constraint->pos;
 577                 int                        is_memory_op = 0;
 578                 ir_node                   *input        = NULL;
 579                 unsigned                   r_clobber_bits;
 580                 constraint_t               parsed_constraint;
 581                 const arch_register_req_t *req;
 582
 583                 parse_asm_constraints(&parsed_constraint, c, 0);
 584                 if (parsed_constraint.cls != NULL) {
 585                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 586                         if (r_clobber_bits != 0) {
 587                                 if (parsed_constraint.all_registers_allowed) {
 588                                         parsed_constraint.all_registers_allowed = 0;
 589                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 590                                                         parsed_constraint.cls,
 591                                                         &parsed_constraint.allowed_registers);
 592                                 }
 593                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 594                         }
 595                 }
 596
 597                 req = make_register_req(&parsed_constraint, n_out_constraints,
 598                                         out_reg_reqs, i);
 599                 in_reg_reqs[i] = req;
 600
 601                 if (parsed_constraint.immediate_type != '\0') {
 602                         char imm_type = parsed_constraint.immediate_type;
 603                         input = try_create_Immediate(pred, imm_type);
 604                 }
 605
 606                 if (input == NULL) {
 607                         ir_node *pred = NULL;
 608                         switch (be_transformer) {
 609                         case TRANSFORMER_DEFAULT:
 610                                 pred  = get_irn_n(node, i);
 611                                 input = be_transform_node(pred);
 612                                 break;
 613
 614 #ifdef FIRM_GRGEN_BE
 615                         case TRANSFORMER_PBQP:
 616                         case TRANSFORMER_RAND:
 617                                 input = get_irn_n(node, i);
 618                                 break;
 619 #endif
 620
 621                         default: panic("invalid transformer");
 622                         }
 623
 624                         if (parsed_constraint.cls == NULL
 625                                         && parsed_constraint.same_as < 0) {
 626                                 is_memory_op = 1;
 627                         } else if (parsed_constraint.memory_possible) {
 628                                 /* TODO: match Load or Load/Store if memory possible is set */
 629                         }
 630                 }
 631                 in[i] = input;
 632
 633                 register_map[pos].use_input = 1;
 634                 register_map[pos].valid     = 1;
 635                 register_map[pos].memory    = is_memory_op;
 636                 register_map[pos].inout_pos = i;
 637                 register_map[pos].mode      = constraint->mode;
 638         }
 639
 640         /* parse clobbers */
 641         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 642                 const char                *c = get_id_str(clobbers[i]);
 643                 const arch_register_req_t *req;
 644
 645                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 646                         continue;
 647
 648                 req = parse_clobber(c);
 649                 out_reg_reqs[out_idx] = req;
 650                 ++out_idx;
 651         }
 652
 653         /* Attempt to make ASM node register pressure faithful.
 654          * (This does not work for complicated cases yet!)
 655          *
 656          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 657          * the smaller list). Then try to match each constraint of the smaller list
 658          * to 1 of the other list. If we can't match it, then we have to add a dummy
 659          * input/output to the other list
 660          *
 661          * FIXME: This is still broken in lots of cases. But at least better than
 662          *        before...
 663          * FIXME: need to do this per register class...
 664          */
 665         if (out_arity <= arity) {
 666                 int       orig_arity = arity;
 667                 int       in_size    = arity;
 668                 int       o;
 669                 bitset_t *used_ins = bitset_alloca(arity);
 670                 for (o = 0; o < out_arity; ++o) {
 671                         int   i;
 672                         const arch_register_req_t *outreq = out_reg_reqs[o];
 673
 674                         if (outreq->cls == NULL) {
 675                                 continue;
 676                         }
 677
 678                         for (i = 0; i < orig_arity; ++i) {
 679                                 const arch_register_req_t *inreq;
 680                                 if (bitset_is_set(used_ins, i))
 681                                         continue;
 682                                 inreq = in_reg_reqs[i];
 683                                 if (!can_match(outreq, inreq))
 684                                         continue;
 685                                 bitset_set(used_ins, i);
 686                                 break;
 687                         }
 688                         /* did we find any match? */
 689                         if (i < orig_arity)
 690                                 continue;
 691
 692                         /* we might need more space in the input arrays */
 693                         if (arity >= in_size) {
 694                                 const arch_register_req_t **new_in_reg_reqs;
 695                                 ir_node             **new_in;
 696
 697                                 in_size *= 2;
 698                                 new_in_reg_reqs
 699                                         = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
 700                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 701                                 new_in = ALLOCANZ(ir_node*, in_size);
 702                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 703
 704                                 in_reg_reqs = new_in_reg_reqs;
 705                                 in          = new_in;
 706                         }
 707
 708                         /* add a new (dummy) input which occupies the register */
 709                         assert(outreq->type & arch_register_req_type_limited);
 710                         in_reg_reqs[arity] = outreq;
 711                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 712                         be_dep_on_frame(in[arity]);
 713                         ++arity;
 714                 }
 715         } else {
 716                 int       i;
 717                 bitset_t *used_outs = bitset_alloca(out_arity);
 718                 int       orig_out_arity = out_arity;
 719                 for (i = 0; i < arity; ++i) {
 720                         int   o;
 721                         const arch_register_req_t *inreq = in_reg_reqs[i];
 722
 723                         if (inreq->cls == NULL) {
 724                                 continue;
 725                         }
 726
 727                         for (o = 0; o < orig_out_arity; ++o) {
 728                                 const arch_register_req_t *outreq;
 729                                 if (bitset_is_set(used_outs, o))
 730                                         continue;
 731                                 outreq = out_reg_reqs[o];
 732                                 if (!can_match(outreq, inreq))
 733                                         continue;
 734                                 bitset_set(used_outs, i);
 735                                 break;
 736                         }
 737                         /* did we find any match? */
 738                         if (o < orig_out_arity)
 739                                 continue;
 740
 741                         /* we might need more space in the output arrays */
 742                         if (out_arity >= out_size) {
 743                                 const arch_register_req_t **new_out_reg_reqs;
 744
 745                                 out_size *= 2;
 746                                 new_out_reg_reqs
 747                                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 748                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 749                                        out_arity * sizeof(new_out_reg_reqs[0]));
 750                                 out_reg_reqs = new_out_reg_reqs;
 751                         }
 752
 753                         /* add a new (dummy) output which occupies the register */
 754                         assert(inreq->type & arch_register_req_type_limited);
 755                         out_reg_reqs[out_arity] = inreq;
 756                         ++out_arity;
 757                 }
 758         }
 759
 760         /* append none register requirement for the memory output */
 761         if (out_arity + 1 >= out_size) {
 762                 const arch_register_req_t **new_out_reg_reqs;
 763
 764                 out_size = out_arity + 1;
 765                 new_out_reg_reqs
 766                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 767                 memcpy(new_out_reg_reqs, out_reg_reqs,
 768                            out_arity * sizeof(new_out_reg_reqs[0]));
 769                 out_reg_reqs = new_out_reg_reqs;
 770         }
 771
 772         /* add a new (dummy) output which occupies the register */
 773         out_reg_reqs[out_arity] = arch_no_register_req;
 774         ++out_arity;
 775
 776         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 777                                    get_ASM_text(node), register_map);
 778
 779         if (arity == 0)
 780                 be_dep_on_frame(new_node);
 781
 782         info = be_get_info(new_node);
 783         for (i = 0; i < out_arity; ++i) {
 784                 info->out_infos[i].req = out_reg_reqs[i];
 785         }
 786         set_ia32_in_req_all(new_node, in_reg_reqs);
 787
 788         SET_IA32_ORIG_NODE(new_node, node);
 789
 790         return new_node;
 791 }
 792
 793 ir_node *gen_CopyB(ir_node *node)
 794 {
 795         ir_node  *block    = NULL;
 796         ir_node  *src      = NULL;
 797         ir_node  *new_src  = NULL;
 798         ir_node  *dst      = NULL;
 799         ir_node  *new_dst  = NULL;
 800         ir_node  *mem      = NULL;
 801         ir_node  *new_mem  = NULL;
 802         ir_node  *res      = NULL;
 803         dbg_info *dbgi     = get_irn_dbg_info(node);
 804         int      size      = get_type_size_bytes(get_CopyB_type(node));
 805         int      rem;
 806
 807         switch (be_transformer) {
 808                 case TRANSFORMER_DEFAULT:
 809                         block    = be_transform_node(get_nodes_block(node));
 810                         src      = get_CopyB_src(node);
 811                         new_src  = be_transform_node(src);
 812                         dst      = get_CopyB_dst(node);
 813                         new_dst  = be_transform_node(dst);
 814                         mem      = get_CopyB_mem(node);
 815                         new_mem  = be_transform_node(mem);
 816                         break;
 817
 818 #ifdef FIRM_GRGEN_BE
 819                 case TRANSFORMER_PBQP:
 820                 case TRANSFORMER_RAND:
 821                         block    = get_nodes_block(node);
 822                         new_src  = get_CopyB_src(node);
 823                         new_dst  = get_CopyB_dst(node);
 824                         new_mem  = get_CopyB_mem(node);
 825                         break;
 826 #endif
 827
 828                 default: panic("invalid transformer");
 829         }
 830
 831         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 832         /* then we need the size explicitly in ECX.                    */
 833         if (size >= 32 * 4) {
 834                 rem = size & 0x3; /* size % 4 */
 835                 size >>= 2;
 836
 837                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 838                 be_dep_on_frame(res);
 839
 840                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 841         } else {
 842                 if (size == 0) {
 843                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 844                                    node);
 845                 }
 846                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 847         }
 848
 849         SET_IA32_ORIG_NODE(res, node);
 850
 851         return res;
 852 }
 853
 854 ir_node *gen_Proj_tls(ir_node *node)
 855 {
 856         ir_node  *block = NULL;
 857         dbg_info *dbgi  = NULL;
 858         ir_node  *res   = NULL;
 859
 860         switch (be_transformer) {
 861                 case TRANSFORMER_DEFAULT:
 862                         block = be_transform_node(get_nodes_block(node));
 863                         break;
 864
 865 #ifdef FIRM_GRGEN_BE
 866                 case TRANSFORMER_PBQP:
 867                 case TRANSFORMER_RAND:
 868                         block = get_nodes_block(node);
 869                         break;
 870 #endif
 871
 872                 default: panic("invalid transformer");
 873         }
 874
 875         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 876
 877         return res;
 878 }
 879
 880 ir_node *gen_Unknown(ir_node *node)
 881 {
 882         ir_mode *mode = get_irn_mode(node);
 883
 884         if (mode_is_float(mode)) {
 885                 if (ia32_cg_config.use_sse2) {
 886                         return ia32_new_Unknown_xmm(env_cg);
 887                 } else {
 888                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 889                         ir_graph *irg   = current_ir_graph;
 890                         dbg_info *dbgi  = get_irn_dbg_info(node);
 891                         ir_node  *block = get_irg_start_block(irg);
 892                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 893
 894                         be_dep_on_frame(ret);
 895                         return ret;
 896                 }
 897         } else if (ia32_mode_needs_gp_reg(mode)) {
 898                 return ia32_new_Unknown_gp(env_cg);
 899         } else {
 900                 panic("unsupported Unknown-Mode");
 901         }
 902         return NULL;
 903 }
 904
 905 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 906                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 907 {
 908         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 909         int                  same_as = constraint->same_as;
 910         arch_register_req_t *req;
 911
 912         if (same_as >= 0) {
 913                 const arch_register_req_t *other_constr;
 914
 915                 if (same_as >= n_outs)
 916                         panic("invalid output number in same_as constraint");
 917
 918                 other_constr     = out_reqs[same_as];
 919
 920                 req              = obstack_alloc(obst, sizeof(req[0]));
 921                 *req             = *other_constr;
 922                 req->type       |= arch_register_req_type_should_be_same;
 923                 req->other_same  = 1U << pos;
 924
 925                 /* switch constraints. This is because in firm we have same_as
 926                  * constraints on the output constraints while in the gcc asm syntax
 927                  * they are specified on the input constraints */
 928                 out_reqs[same_as] = req;
 929                 return other_constr;
 930         }
 931
 932         /* pure memory ops */
 933         if (constraint->cls == NULL) {
 934                 return &no_register_req;
 935         }
 936
 937         if (constraint->allowed_registers != 0
 938                         && !constraint->all_registers_allowed) {
 939                 unsigned *limited_ptr;
 940
 941                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 942                 memset(req, 0, sizeof(req[0]));
 943                 limited_ptr = (unsigned*) (req+1);
 944
 945                 req->type    = arch_register_req_type_limited;
 946                 *limited_ptr = constraint->allowed_registers;
 947                 req->limited = limited_ptr;
 948         } else {
 949                 req       = obstack_alloc(obst, sizeof(req[0]));
 950                 memset(req, 0, sizeof(req[0]));
 951                 req->type = arch_register_req_type_normal;
 952         }
 953         req->cls = constraint->cls;
 954
 955         return req;
 956 }
 957
 958 const arch_register_req_t *parse_clobber(const char *clobber)
 959 {
 960         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 961         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 962         arch_register_req_t   *req;
 963         unsigned              *limited;
 964
 965         if (reg == NULL) {
 966                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 967         }
 968
 969         assert(reg->index < 32);
 970
 971         limited  = obstack_alloc(obst, sizeof(limited[0]));
 972         *limited = 1 << reg->index;
 973
 974         req          = obstack_alloc(obst, sizeof(req[0]));
 975         memset(req, 0, sizeof(req[0]));
 976         req->type    = arch_register_req_type_limited;
 977         req->cls     = arch_register_get_class(reg);
 978         req->limited = limited;
 979
 980         return req;
 981 }
 982
 983
 984 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 985                        ir_node *const other)
 986 {
 987         if (get_nodes_block(other) != block)
 988                 return 0;
 989
 990         if (is_Sync(other)) {
 991                 int i;
 992
 993                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 994                         ir_node *const pred = get_Sync_pred(other, i);
 995
 996                         if (get_nodes_block(pred) != block)
 997                                 continue;
 998
 999                         /* Do not block ourselves from getting eaten */
1000                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
1001                                 continue;
1002
1003                         if (!heights_reachable_in_block(heights, pred, am_candidate))
1004                                 continue;
1005
1006                         return 1;
1007                 }
1008
1009                 return 0;
1010         } else {
1011                 /* Do not block ourselves from getting eaten */
1012                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
1013                         return 0;
1014
1015                 if (!heights_reachable_in_block(heights, other, am_candidate))
1016                         return 0;
1017
1018                 return 1;
1019         }
1020 }
1021
1022 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
1023 {
1024         long         val = 0;
1025         ir_entity   *symconst_ent  = NULL;
1026         ir_mode     *mode;
1027         ir_node     *cnst          = NULL;
1028         ir_node     *symconst      = NULL;
1029         ir_node     *new_node;
1030
1031         mode = get_irn_mode(node);
1032         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
1033                 return NULL;
1034         }
1035
1036         if (is_Const(node)) {
1037                 cnst     = node;
1038                 symconst = NULL;
1039         } else if (is_Global(node)) {
1040                 cnst     = NULL;
1041                 symconst = node;
1042         } else if (is_Add(node)) {
1043                 ir_node *left  = get_Add_left(node);
1044                 ir_node *right = get_Add_right(node);
1045                 if (is_Const(left) && is_Global(right)) {
1046                         cnst     = left;
1047                         symconst = right;
1048                 } else if (is_Global(left) && is_Const(right)) {
1049                         cnst     = right;
1050                         symconst = left;
1051                 }
1052         } else {
1053                 return NULL;
1054         }
1055
1056         if (cnst != NULL) {
1057                 tarval *offset = get_Const_tarval(cnst);
1058                 if (!tarval_is_long(offset)) {
1059                         ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
1060                         return NULL;
1061                 }
1062
1063                 val = get_tarval_long(offset);
1064                 if (!check_immediate_constraint(val, immediate_constraint_type))
1065                         return NULL;
1066         }
1067         if (symconst != NULL) {
1068                 if (immediate_constraint_type != 0) {
1069                         /* we need full 32bits for symconsts */
1070                         return NULL;
1071                 }
1072
1073                 symconst_ent = get_Global_entity(symconst);
1074         }
1075         if (cnst == NULL && symconst == NULL)
1076                 return NULL;
1077
1078         new_node = ia32_create_Immediate(symconst_ent, 0, val);
1079         return new_node;
1080 }