nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33 #include "bitset.h"
  34
  35 #include "../betranshlp.h"
  36 #include "../beirg.h"
  37 #include "../beabi.h"
  38
  39 #include "ia32_architecture.h"
  40 #include "ia32_common_transform.h"
  41 #include "ia32_new_nodes.h"
  42
  43 #include "gen_ia32_new_nodes.h"
  44 #include "gen_ia32_regalloc_if.h"
  45
  46 /** hold the current code generator during transformation */
  47 ia32_code_gen_t *env_cg = NULL;
  48
  49 heights_t *heights = NULL;
  50
  51 static const arch_register_req_t no_register_req = {
  52         arch_register_req_type_none,
  53         NULL,                         /* regclass */
  54         NULL,                         /* limit bitset */
  55         0,                            /* same pos */
  56         0                             /* different pos */
  57 };
  58
  59 static int check_immediate_constraint(long val, char immediate_constraint_type)
  60 {
  61         switch (immediate_constraint_type) {
  62                 case 0:
  63                 case 'i': return 1;
  64
  65                 case 'I': return    0 <= val && val <=  31;
  66                 case 'J': return    0 <= val && val <=  63;
  67                 case 'K': return -128 <= val && val <= 127;
  68                 case 'L': return val == 0xff || val == 0xffff;
  69                 case 'M': return    0 <= val && val <=   3;
  70                 case 'N': return    0 <= val && val <= 255;
  71                 case 'O': return    0 <= val && val <= 127;
  72
  73                 default: panic("Invalid immediate constraint found");
  74         }
  75 }
  76
  77 /* creates a unique ident by adding a number to a tag */
  78 ident *ia32_unique_id(const char *tag)
  79 {
  80         static unsigned id = 0;
  81         char str[256];
  82
  83         snprintf(str, sizeof(str), tag, ++id);
  84         return new_id_from_str(str);
  85 }
  86
  87 /**
  88  * Get a primitive type for a mode with alignment 16.
  89  */
  90 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  91 {
  92         pmap_entry *e = pmap_find(types, mode);
  93         ir_type *res;
  94
  95         if (! e) {
  96                 char buf[64];
  97                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
  98                 res = new_type_primitive(new_id_from_str(buf), mode);
  99                 if (get_mode_size_bits(mode) >= 80) {
 100                         set_type_alignment_bytes(res, 16);
 101                 }
 102                 pmap_insert(types, mode, res);
 103         }
 104         else
 105                 res = e->value;
 106         return res;
 107 }
 108
 109 ir_entity *create_float_const_entity(ir_node *cnst)
 110 {
 111         ia32_isa_t *isa = env_cg->isa;
 112         tarval *key     = get_Const_tarval(cnst);
 113         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 114         ir_entity *res;
 115         ir_graph *rem;
 116
 117         if (e == NULL) {
 118                 tarval  *tv   = key;
 119                 ir_mode *mode = get_tarval_mode(tv);
 120                 ir_type *tp;
 121
 122                 if (! ia32_cg_config.use_sse2) {
 123                         /* try to reduce the mode to produce smaller sized entities */
 124                         if (mode != mode_F) {
 125                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 126                                         mode = mode_F;
 127                                         tv = tarval_convert_to(tv, mode);
 128                                 } else if (mode != mode_D) {
 129                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 130                                                 mode = mode_D;
 131                                                 tv = tarval_convert_to(tv, mode);
 132                                         }
 133                                 }
 134                         }
 135                 }
 136
 137                 if (mode == get_irn_mode(cnst)) {
 138                         /* mode was not changed */
 139                         tp = get_Const_type(cnst);
 140                         if (tp == firm_unknown_type)
 141                                 tp = ia32_get_prim_type(isa->types, mode);
 142                 } else
 143                         tp = ia32_get_prim_type(isa->types, mode);
 144
 145                 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
 146
 147                 set_entity_ld_ident(res, get_entity_ident(res));
 148                 set_entity_visibility(res, visibility_local);
 149                 set_entity_variability(res, variability_constant);
 150                 set_entity_allocation(res, allocation_static);
 151
 152                  /* we create a new entity here: It's initialization must resist on the
 153                     const code irg */
 154                 rem = current_ir_graph;
 155                 current_ir_graph = get_const_code_irg();
 156                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 157                 current_ir_graph = rem;
 158
 159                 pmap_insert(isa->tv_ent, key, res);
 160         } else {
 161                 res = e->value;
 162         }
 163
 164         return res;
 165 }
 166
 167 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 168 {
 169         ir_graph *irg         = current_ir_graph;
 170         ir_node  *start_block = get_irg_start_block(irg);
 171         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 172                         symconst_sign, no_pic_adjust, val);
 173         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 174
 175         return immediate;
 176 }
 177
 178 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 179 {
 180         const arch_register_t       *reg = NULL;
 181         int                          c;
 182         size_t                       r;
 183         const arch_register_class_t *cls;
 184
 185         /* TODO: construct a hashmap instead of doing linear search for clobber
 186          * register */
 187         for(c = 0; c < N_CLASSES; ++c) {
 188                 cls = & ia32_reg_classes[c];
 189                 for(r = 0; r < cls->n_regs; ++r) {
 190                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 191                         if (strcmp(temp_reg->name, clobber) == 0
 192                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 193                                 reg = temp_reg;
 194                                 break;
 195                         }
 196                 }
 197                 if (reg != NULL)
 198                         break;
 199         }
 200
 201         return reg;
 202 }
 203
 204 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 205         if (mode == mode_fpcw)
 206                 return 0;
 207         if (get_mode_size_bits(mode) > 32)
 208                 return 0;
 209         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 210 }
 211
 212 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 213                            int is_output)
 214 {
 215         char                         immediate_type     = '\0';
 216         unsigned                     limited            = 0;
 217         const arch_register_class_t *cls                = NULL;
 218         int                          memory_possible       = 0;
 219         int                          all_registers_allowed = 0;
 220         int                          p;
 221         int                          same_as = -1;
 222
 223         memset(constraint, 0, sizeof(constraint[0]));
 224         constraint->same_as = -1;
 225
 226         if (*c == 0) {
 227                 /* a memory constraint: no need to do anything in backend about it
 228                  * (the dependencies are already respected by the memory edge of
 229                  * the node) */
 230                 return;
 231         }
 232
 233         /* TODO: improve error messages with node and source info. (As users can
 234          * easily hit these) */
 235         while(*c != 0) {
 236                 switch(*c) {
 237                 case ' ':
 238                 case '\t':
 239                 case '\n':
 240                         break;
 241
 242                 /* Skip out/in-out marker */
 243                 case '=': break;
 244                 case '+': break;
 245
 246                 case '&': break;
 247
 248                 case '*':
 249                         ++c;
 250                         break;
 251                 case '#':
 252                         while(*c != 0 && *c != ',')
 253                                 ++c;
 254                         break;
 255
 256                 case 'a':
 257                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 258                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 259                         limited |= 1 << REG_EAX;
 260                         break;
 261                 case 'b':
 262                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 263                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 264                         limited |= 1 << REG_EBX;
 265                         break;
 266                 case 'c':
 267                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 268                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 269                         limited |= 1 << REG_ECX;
 270                         break;
 271                 case 'd':
 272                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 273                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 274                         limited |= 1 << REG_EDX;
 275                         break;
 276                 case 'D':
 277                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 278                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 279                         limited |= 1 << REG_EDI;
 280                         break;
 281                 case 'S':
 282                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 283                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 284                         limited |= 1 << REG_ESI;
 285                         break;
 286                 case 'Q':
 287                 case 'q':
 288                         /* q means lower part of the regs only, this makes no
 289                          * difference to Q for us (we only assign whole registers) */
 290                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 291                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 292                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 293                                    1 << REG_EDX;
 294                         break;
 295                 case 'A':
 296                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 297                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 298                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 299                         break;
 300                 case 'l':
 301                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 302                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 303                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 304                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 305                                    1 << REG_EBP;
 306                         break;
 307
 308                 case 'R':
 309                 case 'r':
 310                 case 'p':
 311                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 312                                 panic("multiple register classes not supported");
 313                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 314                         all_registers_allowed = 1;
 315                         break;
 316
 317                 case 'f':
 318                 case 't':
 319                 case 'u':
 320                         /* TODO: mark values so the x87 simulator knows about t and u */
 321                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 322                                 panic("multiple register classes not supported");
 323                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 324                         all_registers_allowed = 1;
 325                         break;
 326
 327                 case 'Y':
 328                 case 'x':
 329                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 330                                 panic("multiple register classes not supproted");
 331                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 332                         all_registers_allowed = 1;
 333                         break;
 334
 335                 case 'I':
 336                 case 'J':
 337                 case 'K':
 338                 case 'L':
 339                 case 'M':
 340                 case 'N':
 341                 case 'O':
 342                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 343                                 panic("multiple register classes not supported");
 344                         if (immediate_type != '\0')
 345                                 panic("multiple immediate types not supported");
 346                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 347                         immediate_type = *c;
 348                         break;
 349                 case 'n':
 350                 case 'i':
 351                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 352                                 panic("multiple register classes not supported");
 353                         if (immediate_type != '\0')
 354                                 panic("multiple immediate types not supported");
 355                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 356                         immediate_type = 'i';
 357                         break;
 358
 359                 case 'X':
 360                 case 'g':
 361                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 362                                 panic("multiple register classes not supported");
 363                         if (immediate_type != '\0')
 364                                 panic("multiple immediate types not supported");
 365                         immediate_type        = 'i';
 366                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 367                         all_registers_allowed = 1;
 368                         memory_possible       = 1;
 369                         break;
 370
 371                 case '0':
 372                 case '1':
 373                 case '2':
 374                 case '3':
 375                 case '4':
 376                 case '5':
 377                 case '6':
 378                 case '7':
 379                 case '8':
 380                 case '9':
 381                         if (is_output)
 382                                 panic("can only specify same constraint on input");
 383
 384                         sscanf(c, "%d%n", &same_as, &p);
 385                         if (same_as >= 0) {
 386                                 c += p;
 387                                 continue;
 388                         }
 389                         break;
 390
 391                 case 'm':
 392                 case 'o':
 393                 case 'V':
 394                         /* memory constraint no need to do anything in backend about it
 395                          * (the dependencies are already respected by the memory edge of
 396                          * the node) */
 397                         memory_possible = 1;
 398                         break;
 399
 400                 case 'E': /* no float consts yet */
 401                 case 'F': /* no float consts yet */
 402                 case 's': /* makes no sense on x86 */
 403                 case '<': /* no autodecrement on x86 */
 404                 case '>': /* no autoincrement on x86 */
 405                 case 'C': /* sse constant not supported yet */
 406                 case 'G': /* 80387 constant not supported yet */
 407                 case 'y': /* we don't support mmx registers yet */
 408                 case 'Z': /* not available in 32 bit mode */
 409                 case 'e': /* not available in 32 bit mode */
 410                         panic("unsupported asm constraint '%c' found in (%+F)",
 411                               *c, current_ir_graph);
 412                         break;
 413                 default:
 414                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 415                               current_ir_graph);
 416                         break;
 417                 }
 418                 ++c;
 419         }
 420
 421         if (same_as >= 0) {
 422                 if (cls != NULL)
 423                         panic("same as and register constraint not supported");
 424                 if (immediate_type != '\0')
 425                         panic("same as and immediate constraint not supported");
 426         }
 427
 428         if (cls == NULL && same_as < 0) {
 429                 if (!memory_possible)
 430                         panic("no constraint specified for assembler input");
 431         }
 432
 433         constraint->same_as               = same_as;
 434         constraint->cls                   = cls;
 435         constraint->allowed_registers     = limited;
 436         constraint->all_registers_allowed = all_registers_allowed;
 437         constraint->memory_possible       = memory_possible;
 438         constraint->immediate_type        = immediate_type;
 439 }
 440
 441 static bool can_match(const arch_register_req_t *in,
 442                       const arch_register_req_t *out)
 443 {
 444         if (in->cls != out->cls)
 445                 return false;
 446         if ( (in->type & arch_register_req_type_limited) == 0
 447                 || (out->type & arch_register_req_type_limited) == 0 )
 448                 return true;
 449
 450         return (*in->limited & *out->limited) != 0;
 451 }
 452
 453 ir_node *gen_ASM(ir_node *node)
 454 {
 455         ir_node                    *block = NULL;
 456         ir_node                    *new_block = NULL;
 457         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 458         int                         i, arity;
 459         int                         out_idx;
 460         ir_node                   **in;
 461         ir_node                    *new_node;
 462         int                         out_arity;
 463         int                         n_out_constraints;
 464         int                         n_clobbers;
 465         const arch_register_req_t **out_reg_reqs;
 466         const arch_register_req_t **in_reg_reqs;
 467         ia32_asm_reg_t             *register_map;
 468         unsigned                    reg_map_size = 0;
 469         struct obstack             *obst;
 470         const ir_asm_constraint    *in_constraints;
 471         const ir_asm_constraint    *out_constraints;
 472         ident                     **clobbers;
 473         int                         clobbers_flags = 0;
 474         unsigned                    clobber_bits[N_CLASSES];
 475
 476         memset(&clobber_bits, 0, sizeof(clobber_bits));
 477
 478         switch (be_transformer) {
 479         case TRANSFORMER_DEFAULT:
 480                 block     = get_nodes_block(node);
 481                 new_block = be_transform_node(block);
 482                 break;
 483
 484 #ifdef FIRM_GRGEN_BE
 485         case TRANSFORMER_PBQP:
 486         case TRANSFORMER_RAND:
 487                 new_block = get_nodes_block(node);
 488                 break;
 489 #endif
 490
 491         default:
 492                 panic("invalid transformer");
 493         }
 494
 495         /* workaround for lots of buggy code out there as most people think volatile
 496          * asm is enough for everything and forget the flags (linux kernel, etc.)
 497          */
 498         if (get_irn_pinned(node) == op_pin_state_pinned) {
 499                 clobbers_flags = 1;
 500         }
 501
 502         arity = get_irn_arity(node);
 503         in    = ALLOCANZ(ir_node*, arity);
 504
 505         clobbers   = get_ASM_clobbers(node);
 506         n_clobbers = 0;
 507         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 508                 const arch_register_req_t *req;
 509                 const char                *c = get_id_str(clobbers[i]);
 510
 511                 if (strcmp(c, "memory") == 0)
 512                         continue;
 513                 if (strcmp(c, "cc") == 0) {
 514                         clobbers_flags = 1;
 515                         continue;
 516                 }
 517
 518                 req = parse_clobber(c);
 519                 clobber_bits[req->cls->index] |= *req->limited;
 520
 521                 n_clobbers++;
 522         }
 523         n_out_constraints = get_ASM_n_output_constraints(node);
 524         out_arity         = n_out_constraints + n_clobbers;
 525
 526         in_constraints  = get_ASM_input_constraints(node);
 527         out_constraints = get_ASM_output_constraints(node);
 528
 529         /* determine size of register_map */
 530         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 531                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 532                 if (constraint->pos > reg_map_size)
 533                         reg_map_size = constraint->pos;
 534         }
 535         for (i = 0; i < arity; ++i) {
 536                 const ir_asm_constraint   *constraint = &in_constraints[i];
 537                 if (constraint->pos > reg_map_size)
 538                         reg_map_size = constraint->pos;
 539         }
 540         ++reg_map_size;
 541
 542         obst         = get_irg_obstack(current_ir_graph);
 543         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 544         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 545
 546         /* construct output constraints */
 547         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 548
 549         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 550                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 551                 const char                *c       = get_id_str(constraint->constraint);
 552                 unsigned                   pos        = constraint->pos;
 553                 constraint_t               parsed_constraint;
 554                 const arch_register_req_t *req;
 555
 556                 parse_asm_constraints(&parsed_constraint, c, 1);
 557                 req = make_register_req(&parsed_constraint, n_out_constraints,
 558                                         out_reg_reqs, out_idx);
 559                 out_reg_reqs[out_idx] = req;
 560
 561                 register_map[pos].use_input = 0;
 562                 register_map[pos].valid     = 1;
 563                 register_map[pos].memory    = 0;
 564                 register_map[pos].inout_pos = out_idx;
 565                 register_map[pos].mode      = constraint->mode;
 566         }
 567
 568         /* inputs + input constraints */
 569         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 570         for (i = 0; i < arity; ++i) {
 571                 ir_node                   *pred         = get_irn_n(node, i);
 572                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 573                 ident                     *constr_id    = constraint->constraint;
 574                 const char                *c            = get_id_str(constr_id);
 575                 unsigned                   pos          = constraint->pos;
 576                 int                        is_memory_op = 0;
 577                 ir_node                   *input        = NULL;
 578                 unsigned                   r_clobber_bits;
 579                 constraint_t               parsed_constraint;
 580                 const arch_register_req_t *req;
 581
 582                 parse_asm_constraints(&parsed_constraint, c, 0);
 583                 if (parsed_constraint.cls != NULL) {
 584                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 585                         if (r_clobber_bits != 0) {
 586                                 if (parsed_constraint.all_registers_allowed) {
 587                                         parsed_constraint.all_registers_allowed = 0;
 588                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 589                                                         parsed_constraint.cls,
 590                                                         &parsed_constraint.allowed_registers);
 591                                 }
 592                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 593                         }
 594                 }
 595
 596                 req = make_register_req(&parsed_constraint, n_out_constraints,
 597                                         out_reg_reqs, i);
 598                 in_reg_reqs[i] = req;
 599
 600                 if (parsed_constraint.immediate_type != '\0') {
 601                         char imm_type = parsed_constraint.immediate_type;
 602                         input = try_create_Immediate(pred, imm_type);
 603                 }
 604
 605                 if (input == NULL) {
 606                         ir_node *pred = NULL;
 607                         switch (be_transformer) {
 608                         case TRANSFORMER_DEFAULT:
 609                                 pred  = get_irn_n(node, i);
 610                                 input = be_transform_node(pred);
 611                                 break;
 612
 613 #ifdef FIRM_GRGEN_BE
 614                         case TRANSFORMER_PBQP:
 615                         case TRANSFORMER_RAND:
 616                                 input = get_irn_n(node, i);
 617                                 break;
 618 #endif
 619
 620                         default: panic("invalid transformer");
 621                         }
 622
 623                         if (parsed_constraint.cls == NULL
 624                                         && parsed_constraint.same_as < 0) {
 625                                 is_memory_op = 1;
 626                         } else if (parsed_constraint.memory_possible) {
 627                                 /* TODO: match Load or Load/Store if memory possible is set */
 628                         }
 629                 }
 630                 in[i] = input;
 631
 632                 register_map[pos].use_input = 1;
 633                 register_map[pos].valid     = 1;
 634                 register_map[pos].memory    = is_memory_op;
 635                 register_map[pos].inout_pos = i;
 636                 register_map[pos].mode      = constraint->mode;
 637         }
 638
 639         /* parse clobbers */
 640         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 641                 const char                *c = get_id_str(clobbers[i]);
 642                 const arch_register_req_t *req;
 643
 644                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 645                         continue;
 646
 647                 req = parse_clobber(c);
 648                 out_reg_reqs[out_idx] = req;
 649                 ++out_idx;
 650         }
 651
 652         /* Attempt to make ASM node register pressure faithfull.
 653          * (This does not work for complicated cases yet!)
 654          *
 655          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 656          * the smaller list). Then try to match each constraint of the smaller list
 657          * to 1 of the other list. If we can't match it, then we have to add a dummy
 658          * input/output to the other list
 659          *
 660          * FIXME: This is still broken in lots of cases. But at least better than
 661          *        before...
 662          * FIXME: need to do this per register class...
 663          */
 664         if (out_arity <= arity) {
 665                 int       orig_arity = arity;
 666                 int       in_size    = arity;
 667                 int       o;
 668                 bitset_t *used_ins = bitset_alloca(arity);
 669                 for (o = 0; o < out_arity; ++o) {
 670                         int   i;
 671                         const arch_register_req_t *outreq = out_reg_reqs[o];
 672
 673                         if (outreq->cls == NULL) {
 674                                 continue;
 675                         }
 676
 677                         for (i = 0; i < orig_arity; ++i) {
 678                                 const arch_register_req_t *inreq;
 679                                 if (bitset_is_set(used_ins, i))
 680                                         continue;
 681                                 inreq = in_reg_reqs[i];
 682                                 if (!can_match(outreq, inreq))
 683                                         continue;
 684                                 bitset_set(used_ins, i);
 685                                 break;
 686                         }
 687                         /* did we find any match? */
 688                         if (i < orig_arity)
 689                                 continue;
 690
 691                         /* we might need more space in the input arrays */
 692                         if (arity >= in_size) {
 693                                 const arch_register_req_t **new_in_reg_reqs;
 694                                 ir_node             **new_in;
 695
 696                                 in_size *= 2;
 697                                 new_in_reg_reqs
 698                                         = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
 699                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 700                                 new_in = ALLOCANZ(ir_node*, in_size);
 701                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 702
 703                                 in_reg_reqs = new_in_reg_reqs;
 704                                 in          = new_in;
 705                         }
 706
 707                         /* add a new (dummy) input which occupies the register */
 708                         assert(outreq->type & arch_register_req_type_limited);
 709                         in_reg_reqs[arity] = outreq;
 710                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 711                         be_dep_on_frame(in[arity]);
 712                         ++arity;
 713                 }
 714         } else {
 715                 int       i;
 716                 bitset_t *used_outs = bitset_alloca(out_arity);
 717                 int       orig_out_arity = out_arity;
 718                 int       out_size       = out_arity;
 719                 for (i = 0; i < arity; ++i) {
 720                         int   o;
 721                         const arch_register_req_t *inreq = in_reg_reqs[i];
 722
 723                         if (inreq->cls == NULL) {
 724                                 continue;
 725                         }
 726
 727                         for (o = 0; o < orig_out_arity; ++o) {
 728                                 const arch_register_req_t *outreq;
 729                                 if (bitset_is_set(used_outs, o))
 730                                         continue;
 731                                 outreq = out_reg_reqs[o];
 732                                 if (!can_match(outreq, inreq))
 733                                         continue;
 734                                 bitset_set(used_outs, i);
 735                                 break;
 736                         }
 737                         /* did we find any match? */
 738                         if (o < orig_out_arity)
 739                                 continue;
 740
 741                         /* we might need more space in the output arrays */
 742                         if (out_arity >= out_size) {
 743                                 const arch_register_req_t **new_out_reg_reqs;
 744
 745                                 out_size *= 2;
 746                                 new_out_reg_reqs
 747                                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 748                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 749                                        out_arity * sizeof(new_out_reg_reqs[0]));
 750                                 out_reg_reqs = new_out_reg_reqs;
 751                         }
 752
 753                         /* add a new (dummy) output which occupies the register */
 754                         assert(inreq->type & arch_register_req_type_limited);
 755                         out_reg_reqs[out_arity] = inreq;
 756                         ++out_arity;
 757                 }
 758         }
 759
 760         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 761                                    get_ASM_text(node), register_map);
 762
 763         if (arity == 0)
 764                 be_dep_on_frame(new_node);
 765
 766         set_ia32_out_req_all(new_node, out_reg_reqs);
 767         set_ia32_in_req_all(new_node, in_reg_reqs);
 768
 769         SET_IA32_ORIG_NODE(new_node, node);
 770
 771         return new_node;
 772 }
 773
 774 ir_node *gen_CopyB(ir_node *node) {
 775         ir_node  *block    = NULL;
 776         ir_node  *src      = NULL;
 777         ir_node  *new_src  = NULL;
 778         ir_node  *dst      = NULL;
 779         ir_node  *new_dst  = NULL;
 780         ir_node  *mem      = NULL;
 781         ir_node  *new_mem  = NULL;
 782         ir_node  *res      = NULL;
 783         dbg_info *dbgi     = get_irn_dbg_info(node);
 784         int      size      = get_type_size_bytes(get_CopyB_type(node));
 785         int      rem;
 786
 787         switch (be_transformer) {
 788                 case TRANSFORMER_DEFAULT:
 789                         block    = be_transform_node(get_nodes_block(node));
 790                         src      = get_CopyB_src(node);
 791                         new_src  = be_transform_node(src);
 792                         dst      = get_CopyB_dst(node);
 793                         new_dst  = be_transform_node(dst);
 794                         mem      = get_CopyB_mem(node);
 795                         new_mem  = be_transform_node(mem);
 796                         break;
 797
 798 #ifdef FIRM_GRGEN_BE
 799                 case TRANSFORMER_PBQP:
 800                 case TRANSFORMER_RAND:
 801                         block    = get_nodes_block(node);
 802                         new_src  = get_CopyB_src(node);
 803                         new_dst  = get_CopyB_dst(node);
 804                         new_mem  = get_CopyB_mem(node);
 805                         break;
 806 #endif
 807
 808                 default: panic("invalid transformer");
 809         }
 810
 811         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 812         /* then we need the size explicitly in ECX.                    */
 813         if (size >= 32 * 4) {
 814                 rem = size & 0x3; /* size % 4 */
 815                 size >>= 2;
 816
 817                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 818                 be_dep_on_frame(res);
 819
 820                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 821         } else {
 822                 if (size == 0) {
 823                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 824                                    node);
 825                 }
 826                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 827         }
 828
 829         SET_IA32_ORIG_NODE(res, node);
 830
 831         return res;
 832 }
 833
 834 ir_node *gen_Proj_tls(ir_node *node) {
 835         ir_node  *block = NULL;
 836         dbg_info *dbgi  = NULL;
 837         ir_node  *res   = NULL;
 838
 839         switch (be_transformer) {
 840                 case TRANSFORMER_DEFAULT:
 841                         block = be_transform_node(get_nodes_block(node));
 842                         break;
 843
 844 #ifdef FIRM_GRGEN_BE
 845                 case TRANSFORMER_PBQP:
 846                 case TRANSFORMER_RAND:
 847                         block = get_nodes_block(node);
 848                         break;
 849 #endif
 850
 851                 default: panic("invalid transformer");
 852         }
 853
 854         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 855
 856         return res;
 857 }
 858
 859 ir_node *gen_Unknown(ir_node *node)
 860 {
 861         ir_mode *mode = get_irn_mode(node);
 862
 863         if (mode_is_float(mode)) {
 864                 if (ia32_cg_config.use_sse2) {
 865                         return ia32_new_Unknown_xmm(env_cg);
 866                 } else {
 867                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 868                         ir_graph *irg   = current_ir_graph;
 869                         dbg_info *dbgi  = get_irn_dbg_info(node);
 870                         ir_node  *block = get_irg_start_block(irg);
 871                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 872
 873                         be_dep_on_frame(ret);
 874                         return ret;
 875                 }
 876         } else if (ia32_mode_needs_gp_reg(mode)) {
 877                 return ia32_new_Unknown_gp(env_cg);
 878         } else {
 879                 panic("unsupported Unknown-Mode");
 880         }
 881         return NULL;
 882 }
 883
 884 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 885                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 886 {
 887         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 888         int                  same_as = constraint->same_as;
 889         arch_register_req_t *req;
 890
 891         if (same_as >= 0) {
 892                 const arch_register_req_t *other_constr;
 893
 894                 if (same_as >= n_outs)
 895                         panic("invalid output number in same_as constraint");
 896
 897                 other_constr     = out_reqs[same_as];
 898
 899                 req              = obstack_alloc(obst, sizeof(req[0]));
 900                 *req             = *other_constr;
 901                 req->type       |= arch_register_req_type_should_be_same;
 902                 req->other_same  = 1U << pos;
 903
 904                 /* switch constraints. This is because in firm we have same_as
 905                  * constraints on the output constraints while in the gcc asm syntax
 906                  * they are specified on the input constraints */
 907                 out_reqs[same_as] = req;
 908                 return other_constr;
 909         }
 910
 911         /* pure memory ops */
 912         if (constraint->cls == NULL) {
 913                 return &no_register_req;
 914         }
 915
 916         if (constraint->allowed_registers != 0
 917                         && !constraint->all_registers_allowed) {
 918                 unsigned *limited_ptr;
 919
 920                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 921                 memset(req, 0, sizeof(req[0]));
 922                 limited_ptr = (unsigned*) (req+1);
 923
 924                 req->type    = arch_register_req_type_limited;
 925                 *limited_ptr = constraint->allowed_registers;
 926                 req->limited = limited_ptr;
 927         } else {
 928                 req       = obstack_alloc(obst, sizeof(req[0]));
 929                 memset(req, 0, sizeof(req[0]));
 930                 req->type = arch_register_req_type_normal;
 931         }
 932         req->cls = constraint->cls;
 933
 934         return req;
 935 }
 936
 937 const arch_register_req_t *parse_clobber(const char *clobber)
 938 {
 939         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 940         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 941         arch_register_req_t   *req;
 942         unsigned              *limited;
 943
 944         if (reg == NULL) {
 945                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 946         }
 947
 948         assert(reg->index < 32);
 949
 950         limited  = obstack_alloc(obst, sizeof(limited[0]));
 951         *limited = 1 << reg->index;
 952
 953         req          = obstack_alloc(obst, sizeof(req[0]));
 954         memset(req, 0, sizeof(req[0]));
 955         req->type    = arch_register_req_type_limited;
 956         req->cls     = arch_register_get_class(reg);
 957         req->limited = limited;
 958
 959         return req;
 960 }
 961
 962
 963 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 964                        ir_node *const other)
 965 {
 966         if (get_nodes_block(other) != block)
 967                 return 0;
 968
 969         if (is_Sync(other)) {
 970                 int i;
 971
 972                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 973                         ir_node *const pred = get_Sync_pred(other, i);
 974
 975                         if (get_nodes_block(pred) != block)
 976                                 continue;
 977
 978                         /* Do not block ourselves from getting eaten */
 979                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 980                                 continue;
 981
 982                         if (!heights_reachable_in_block(heights, pred, am_candidate))
 983                                 continue;
 984
 985                         return 1;
 986                 }
 987
 988                 return 0;
 989         } else {
 990                 /* Do not block ourselves from getting eaten */
 991                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
 992                         return 0;
 993
 994                 if (!heights_reachable_in_block(heights, other, am_candidate))
 995                         return 0;
 996
 997                 return 1;
 998         }
 999 }
1000
1001 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
1002 {
1003         int          minus         = 0;
1004         tarval      *offset        = NULL;
1005         int          offset_sign   = 0;
1006         long         val = 0;
1007         ir_entity   *symconst_ent  = NULL;
1008         int          symconst_sign = 0;
1009         ir_mode     *mode;
1010         ir_node     *cnst          = NULL;
1011         ir_node     *symconst      = NULL;
1012         ir_node     *new_node;
1013
1014         mode = get_irn_mode(node);
1015         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
1016                 return NULL;
1017         }
1018
1019         if (is_Minus(node)) {
1020                 minus = 1;
1021                 node  = get_Minus_op(node);
1022         }
1023
1024         if (is_Const(node)) {
1025                 cnst        = node;
1026                 symconst    = NULL;
1027                 offset_sign = minus;
1028         } else if (is_SymConst(node)) {
1029                 cnst          = NULL;
1030                 symconst      = node;
1031                 symconst_sign = minus;
1032         } else if (is_Add(node)) {
1033                 ir_node *left  = get_Add_left(node);
1034                 ir_node *right = get_Add_right(node);
1035                 if (is_Const(left) && is_SymConst(right)) {
1036                         cnst          = left;
1037                         symconst      = right;
1038                         symconst_sign = minus;
1039                         offset_sign   = minus;
1040                 } else if (is_SymConst(left) && is_Const(right)) {
1041                         cnst          = right;
1042                         symconst      = left;
1043                         symconst_sign = minus;
1044                         offset_sign   = minus;
1045                 }
1046         } else if (is_Sub(node)) {
1047                 ir_node *left  = get_Sub_left(node);
1048                 ir_node *right = get_Sub_right(node);
1049                 if (is_Const(left) && is_SymConst(right)) {
1050                         cnst          = left;
1051                         symconst      = right;
1052                         symconst_sign = !minus;
1053                         offset_sign   = minus;
1054                 } else if (is_SymConst(left) && is_Const(right)) {
1055                         cnst          = right;
1056                         symconst      = left;
1057                         symconst_sign = minus;
1058                         offset_sign   = !minus;
1059                 }
1060         } else {
1061                 return NULL;
1062         }
1063
1064         if (cnst != NULL) {
1065                 offset = get_Const_tarval(cnst);
1066                 if (tarval_is_long(offset)) {
1067                         val = get_tarval_long(offset);
1068                 } else {
1069                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
1070                                    "long?\n", cnst);
1071                         return NULL;
1072                 }
1073
1074                 if (!check_immediate_constraint(val, immediate_constraint_type))
1075                         return NULL;
1076         }
1077         if (symconst != NULL) {
1078                 if (immediate_constraint_type != 0) {
1079                         /* we need full 32bits for symconsts */
1080                         return NULL;
1081                 }
1082
1083                 /* unfortunately the assembler/linker doesn't support -symconst */
1084                 if (symconst_sign)
1085                         return NULL;
1086
1087                 if (get_SymConst_kind(symconst) != symconst_addr_ent)
1088                         return NULL;
1089                 symconst_ent = get_SymConst_entity(symconst);
1090         }
1091         if (cnst == NULL && symconst == NULL)
1092                 return NULL;
1093
1094         if (offset_sign && offset != NULL) {
1095                 offset = tarval_neg(offset);
1096         }
1097
1098         new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val);
1099
1100         return new_node;
1101 }