nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33 #include "bitset.h"
  34
  35 #include "../betranshlp.h"
  36 #include "../beirg.h"
  37 #include "../beabi.h"
  38
  39 #include "ia32_architecture.h"
  40 #include "ia32_common_transform.h"
  41 #include "ia32_new_nodes.h"
  42
  43 #include "gen_ia32_new_nodes.h"
  44 #include "gen_ia32_regalloc_if.h"
  45
  46 /** hold the current code generator during transformation */
  47 ia32_code_gen_t *env_cg = NULL;
  48
  49 heights_t *heights = NULL;
  50
  51 static const arch_register_req_t no_register_req = {
  52         arch_register_req_type_none,
  53         NULL,                         /* regclass */
  54         NULL,                         /* limit bitset */
  55         0,                            /* same pos */
  56         0                             /* different pos */
  57 };
  58
  59 static int check_immediate_constraint(long val, char immediate_constraint_type)
  60 {
  61         switch (immediate_constraint_type) {
  62                 case 0:
  63                 case 'i': return 1;
  64
  65                 case 'I': return    0 <= val && val <=  31;
  66                 case 'J': return    0 <= val && val <=  63;
  67                 case 'K': return -128 <= val && val <= 127;
  68                 case 'L': return val == 0xff || val == 0xffff;
  69                 case 'M': return    0 <= val && val <=   3;
  70                 case 'N': return    0 <= val && val <= 255;
  71                 case 'O': return    0 <= val && val <= 127;
  72
  73                 default: panic("Invalid immediate constraint found");
  74         }
  75 }
  76
  77 /* creates a unique ident by adding a number to a tag */
  78 ident *ia32_unique_id(const char *tag)
  79 {
  80         static unsigned id = 0;
  81         char str[256];
  82
  83         snprintf(str, sizeof(str), tag, ++id);
  84         return new_id_from_str(str);
  85 }
  86
  87 /**
  88  * Get a primitive type for a mode with alignment 16.
  89  */
  90 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  91 {
  92         pmap_entry *e = pmap_find(types, mode);
  93         ir_type *res;
  94
  95         if (! e) {
  96                 res = new_type_primitive(mode);
  97                 if (get_mode_size_bits(mode) >= 80) {
  98                         set_type_alignment_bytes(res, 16);
  99                 }
 100                 pmap_insert(types, mode, res);
 101         }
 102         else
 103                 res = e->value;
 104         return res;
 105 }
 106
 107 ir_entity *create_float_const_entity(ir_node *cnst)
 108 {
 109         ia32_isa_t *isa = env_cg->isa;
 110         tarval *key     = get_Const_tarval(cnst);
 111         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 112         ir_entity *res;
 113         ir_graph *rem;
 114
 115         if (e == NULL) {
 116                 tarval  *tv   = key;
 117                 ir_mode *mode = get_tarval_mode(tv);
 118                 ir_type *tp;
 119
 120                 if (! ia32_cg_config.use_sse2) {
 121                         /* try to reduce the mode to produce smaller sized entities */
 122                         if (mode != mode_F) {
 123                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 124                                         mode = mode_F;
 125                                         tv = tarval_convert_to(tv, mode);
 126                                 } else if (mode != mode_D) {
 127                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 128                                                 mode = mode_D;
 129                                                 tv = tarval_convert_to(tv, mode);
 130                                         }
 131                                 }
 132                         }
 133                 }
 134
 135                 if (mode == get_irn_mode(cnst)) {
 136                         /* mode was not changed */
 137                         tp = get_Const_type(cnst);
 138                         if (tp == firm_unknown_type)
 139                                 tp = ia32_get_prim_type(isa->types, mode);
 140                 } else
 141                         tp = ia32_get_prim_type(isa->types, mode);
 142
 143                 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
 144
 145                 set_entity_ld_ident(res, get_entity_ident(res));
 146                 set_entity_visibility(res, ir_visibility_local);
 147                 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
 148
 149                  /* we create a new entity here: It's initialization must resist on the
 150                     const code irg */
 151                 rem = current_ir_graph;
 152                 current_ir_graph = get_const_code_irg();
 153                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 154                 current_ir_graph = rem;
 155
 156                 pmap_insert(isa->tv_ent, key, res);
 157         } else {
 158                 res = e->value;
 159         }
 160
 161         return res;
 162 }
 163
 164 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 165 {
 166         ir_graph *irg         = current_ir_graph;
 167         ir_node  *start_block = get_irg_start_block(irg);
 168         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 169                         symconst_sign, no_pic_adjust, val);
 170         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 171
 172         return immediate;
 173 }
 174
 175 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 176 {
 177         const arch_register_t       *reg = NULL;
 178         int                          c;
 179         size_t                       r;
 180         const arch_register_class_t *cls;
 181
 182         /* TODO: construct a hashmap instead of doing linear search for clobber
 183          * register */
 184         for(c = 0; c < N_CLASSES; ++c) {
 185                 cls = & ia32_reg_classes[c];
 186                 for(r = 0; r < cls->n_regs; ++r) {
 187                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 188                         if (strcmp(temp_reg->name, clobber) == 0
 189                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 190                                 reg = temp_reg;
 191                                 break;
 192                         }
 193                 }
 194                 if (reg != NULL)
 195                         break;
 196         }
 197
 198         return reg;
 199 }
 200
 201 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 202         if (mode == mode_fpcw)
 203                 return 0;
 204         if (get_mode_size_bits(mode) > 32)
 205                 return 0;
 206         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 207 }
 208
 209 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 210                            int is_output)
 211 {
 212         char                         immediate_type     = '\0';
 213         unsigned                     limited            = 0;
 214         const arch_register_class_t *cls                = NULL;
 215         int                          memory_possible       = 0;
 216         int                          all_registers_allowed = 0;
 217         int                          p;
 218         int                          same_as = -1;
 219
 220         memset(constraint, 0, sizeof(constraint[0]));
 221         constraint->same_as = -1;
 222
 223         if (*c == 0) {
 224                 /* a memory constraint: no need to do anything in backend about it
 225                  * (the dependencies are already respected by the memory edge of
 226                  * the node) */
 227                 return;
 228         }
 229
 230         /* TODO: improve error messages with node and source info. (As users can
 231          * easily hit these) */
 232         while(*c != 0) {
 233                 switch(*c) {
 234                 case ' ':
 235                 case '\t':
 236                 case '\n':
 237                         break;
 238
 239                 /* Skip out/in-out marker */
 240                 case '=': break;
 241                 case '+': break;
 242
 243                 case '&': break;
 244
 245                 case '*':
 246                         ++c;
 247                         break;
 248                 case '#':
 249                         while(*c != 0 && *c != ',')
 250                                 ++c;
 251                         break;
 252
 253                 case 'a':
 254                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 255                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 256                         limited |= 1 << REG_EAX;
 257                         break;
 258                 case 'b':
 259                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 260                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 261                         limited |= 1 << REG_EBX;
 262                         break;
 263                 case 'c':
 264                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 265                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 266                         limited |= 1 << REG_ECX;
 267                         break;
 268                 case 'd':
 269                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 270                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 271                         limited |= 1 << REG_EDX;
 272                         break;
 273                 case 'D':
 274                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 275                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 276                         limited |= 1 << REG_EDI;
 277                         break;
 278                 case 'S':
 279                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 280                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 281                         limited |= 1 << REG_ESI;
 282                         break;
 283                 case 'Q':
 284                 case 'q':
 285                         /* q means lower part of the regs only, this makes no
 286                          * difference to Q for us (we only assign whole registers) */
 287                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 288                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 289                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 290                                    1 << REG_EDX;
 291                         break;
 292                 case 'A':
 293                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 294                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 295                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 296                         break;
 297                 case 'l':
 298                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 299                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 300                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 301                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 302                                    1 << REG_EBP;
 303                         break;
 304
 305                 case 'R':
 306                 case 'r':
 307                 case 'p':
 308                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 309                                 panic("multiple register classes not supported");
 310                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 311                         all_registers_allowed = 1;
 312                         break;
 313
 314                 case 'f':
 315                 case 't':
 316                 case 'u':
 317                         /* TODO: mark values so the x87 simulator knows about t and u */
 318                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 319                                 panic("multiple register classes not supported");
 320                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 321                         all_registers_allowed = 1;
 322                         break;
 323
 324                 case 'Y':
 325                 case 'x':
 326                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 327                                 panic("multiple register classes not supproted");
 328                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 329                         all_registers_allowed = 1;
 330                         break;
 331
 332                 case 'I':
 333                 case 'J':
 334                 case 'K':
 335                 case 'L':
 336                 case 'M':
 337                 case 'N':
 338                 case 'O':
 339                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 340                                 panic("multiple register classes not supported");
 341                         if (immediate_type != '\0')
 342                                 panic("multiple immediate types not supported");
 343                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 344                         immediate_type = *c;
 345                         break;
 346                 case 'n':
 347                 case 'i':
 348                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 349                                 panic("multiple register classes not supported");
 350                         if (immediate_type != '\0')
 351                                 panic("multiple immediate types not supported");
 352                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 353                         immediate_type = 'i';
 354                         break;
 355
 356                 case 'X':
 357                 case 'g':
 358                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 359                                 panic("multiple register classes not supported");
 360                         if (immediate_type != '\0')
 361                                 panic("multiple immediate types not supported");
 362                         immediate_type        = 'i';
 363                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 364                         all_registers_allowed = 1;
 365                         memory_possible       = 1;
 366                         break;
 367
 368                 case '0':
 369                 case '1':
 370                 case '2':
 371                 case '3':
 372                 case '4':
 373                 case '5':
 374                 case '6':
 375                 case '7':
 376                 case '8':
 377                 case '9':
 378                         if (is_output)
 379                                 panic("can only specify same constraint on input");
 380
 381                         sscanf(c, "%d%n", &same_as, &p);
 382                         if (same_as >= 0) {
 383                                 c += p;
 384                                 continue;
 385                         }
 386                         break;
 387
 388                 case 'm':
 389                 case 'o':
 390                 case 'V':
 391                         /* memory constraint no need to do anything in backend about it
 392                          * (the dependencies are already respected by the memory edge of
 393                          * the node) */
 394                         memory_possible = 1;
 395                         break;
 396
 397                 case 'E': /* no float consts yet */
 398                 case 'F': /* no float consts yet */
 399                 case 's': /* makes no sense on x86 */
 400                 case '<': /* no autodecrement on x86 */
 401                 case '>': /* no autoincrement on x86 */
 402                 case 'C': /* sse constant not supported yet */
 403                 case 'G': /* 80387 constant not supported yet */
 404                 case 'y': /* we don't support mmx registers yet */
 405                 case 'Z': /* not available in 32 bit mode */
 406                 case 'e': /* not available in 32 bit mode */
 407                         panic("unsupported asm constraint '%c' found in (%+F)",
 408                               *c, current_ir_graph);
 409                         break;
 410                 default:
 411                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 412                               current_ir_graph);
 413                         break;
 414                 }
 415                 ++c;
 416         }
 417
 418         if (same_as >= 0) {
 419                 if (cls != NULL)
 420                         panic("same as and register constraint not supported");
 421                 if (immediate_type != '\0')
 422                         panic("same as and immediate constraint not supported");
 423         }
 424
 425         if (cls == NULL && same_as < 0) {
 426                 if (!memory_possible)
 427                         panic("no constraint specified for assembler input");
 428         }
 429
 430         constraint->same_as               = same_as;
 431         constraint->cls                   = cls;
 432         constraint->allowed_registers     = limited;
 433         constraint->all_registers_allowed = all_registers_allowed;
 434         constraint->memory_possible       = memory_possible;
 435         constraint->immediate_type        = immediate_type;
 436 }
 437
 438 static bool can_match(const arch_register_req_t *in,
 439                       const arch_register_req_t *out)
 440 {
 441         if (in->cls != out->cls)
 442                 return false;
 443         if ( (in->type & arch_register_req_type_limited) == 0
 444                 || (out->type & arch_register_req_type_limited) == 0 )
 445                 return true;
 446
 447         return (*in->limited & *out->limited) != 0;
 448 }
 449
 450 ir_node *gen_ASM(ir_node *node)
 451 {
 452         ir_node                    *block = NULL;
 453         ir_node                    *new_block = NULL;
 454         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 455         int                         i, arity;
 456         int                         out_idx;
 457         ir_node                   **in;
 458         ir_node                    *new_node;
 459         int                         out_arity;
 460         int                         n_out_constraints;
 461         int                         n_clobbers;
 462         const arch_register_req_t **out_reg_reqs;
 463         const arch_register_req_t **in_reg_reqs;
 464         ia32_asm_reg_t             *register_map;
 465         unsigned                    reg_map_size = 0;
 466         struct obstack             *obst;
 467         const ir_asm_constraint    *in_constraints;
 468         const ir_asm_constraint    *out_constraints;
 469         ident                     **clobbers;
 470         int                         clobbers_flags = 0;
 471         unsigned                    clobber_bits[N_CLASSES];
 472         int                         out_size;
 473         backend_info_t             *info;
 474
 475         memset(&clobber_bits, 0, sizeof(clobber_bits));
 476
 477         switch (be_transformer) {
 478         case TRANSFORMER_DEFAULT:
 479                 block     = get_nodes_block(node);
 480                 new_block = be_transform_node(block);
 481                 break;
 482
 483 #ifdef FIRM_GRGEN_BE
 484         case TRANSFORMER_PBQP:
 485         case TRANSFORMER_RAND:
 486                 new_block = get_nodes_block(node);
 487                 break;
 488 #endif
 489
 490         default:
 491                 panic("invalid transformer");
 492         }
 493
 494         /* workaround for lots of buggy code out there as most people think volatile
 495          * asm is enough for everything and forget the flags (linux kernel, etc.)
 496          */
 497         if (get_irn_pinned(node) == op_pin_state_pinned) {
 498                 clobbers_flags = 1;
 499         }
 500
 501         arity = get_irn_arity(node);
 502         in    = ALLOCANZ(ir_node*, arity);
 503
 504         clobbers   = get_ASM_clobbers(node);
 505         n_clobbers = 0;
 506         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 507                 const arch_register_req_t *req;
 508                 const char                *c = get_id_str(clobbers[i]);
 509
 510                 if (strcmp(c, "memory") == 0)
 511                         continue;
 512                 if (strcmp(c, "cc") == 0) {
 513                         clobbers_flags = 1;
 514                         continue;
 515                 }
 516
 517                 req = parse_clobber(c);
 518                 clobber_bits[req->cls->index] |= *req->limited;
 519
 520                 n_clobbers++;
 521         }
 522         n_out_constraints = get_ASM_n_output_constraints(node);
 523         out_arity         = n_out_constraints + n_clobbers;
 524
 525         in_constraints  = get_ASM_input_constraints(node);
 526         out_constraints = get_ASM_output_constraints(node);
 527
 528         /* determine size of register_map */
 529         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 530                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 531                 if (constraint->pos > reg_map_size)
 532                         reg_map_size = constraint->pos;
 533         }
 534         for (i = 0; i < arity; ++i) {
 535                 const ir_asm_constraint   *constraint = &in_constraints[i];
 536                 if (constraint->pos > reg_map_size)
 537                         reg_map_size = constraint->pos;
 538         }
 539         ++reg_map_size;
 540
 541         obst         = get_irg_obstack(current_ir_graph);
 542         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 543         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 544
 545         /* construct output constraints */
 546         out_size = out_arity + 1;
 547         out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
 548
 549         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 550                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 551                 const char                *c       = get_id_str(constraint->constraint);
 552                 unsigned                   pos        = constraint->pos;
 553                 constraint_t               parsed_constraint;
 554                 const arch_register_req_t *req;
 555
 556                 parse_asm_constraints(&parsed_constraint, c, 1);
 557                 req = make_register_req(&parsed_constraint, n_out_constraints,
 558                                         out_reg_reqs, out_idx);
 559                 out_reg_reqs[out_idx] = req;
 560
 561                 register_map[pos].use_input = 0;
 562                 register_map[pos].valid     = 1;
 563                 register_map[pos].memory    = 0;
 564                 register_map[pos].inout_pos = out_idx;
 565                 register_map[pos].mode      = constraint->mode;
 566         }
 567
 568         /* inputs + input constraints */
 569         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 570         for (i = 0; i < arity; ++i) {
 571                 ir_node                   *pred         = get_irn_n(node, i);
 572                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 573                 ident                     *constr_id    = constraint->constraint;
 574                 const char                *c            = get_id_str(constr_id);
 575                 unsigned                   pos          = constraint->pos;
 576                 int                        is_memory_op = 0;
 577                 ir_node                   *input        = NULL;
 578                 unsigned                   r_clobber_bits;
 579                 constraint_t               parsed_constraint;
 580                 const arch_register_req_t *req;
 581
 582                 parse_asm_constraints(&parsed_constraint, c, 0);
 583                 if (parsed_constraint.cls != NULL) {
 584                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 585                         if (r_clobber_bits != 0) {
 586                                 if (parsed_constraint.all_registers_allowed) {
 587                                         parsed_constraint.all_registers_allowed = 0;
 588                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 589                                                         parsed_constraint.cls,
 590                                                         &parsed_constraint.allowed_registers);
 591                                 }
 592                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 593                         }
 594                 }
 595
 596                 req = make_register_req(&parsed_constraint, n_out_constraints,
 597                                         out_reg_reqs, i);
 598                 in_reg_reqs[i] = req;
 599
 600                 if (parsed_constraint.immediate_type != '\0') {
 601                         char imm_type = parsed_constraint.immediate_type;
 602                         input = try_create_Immediate(pred, imm_type);
 603                 }
 604
 605                 if (input == NULL) {
 606                         ir_node *pred = NULL;
 607                         switch (be_transformer) {
 608                         case TRANSFORMER_DEFAULT:
 609                                 pred  = get_irn_n(node, i);
 610                                 input = be_transform_node(pred);
 611                                 break;
 612
 613 #ifdef FIRM_GRGEN_BE
 614                         case TRANSFORMER_PBQP:
 615                         case TRANSFORMER_RAND:
 616                                 input = get_irn_n(node, i);
 617                                 break;
 618 #endif
 619
 620                         default: panic("invalid transformer");
 621                         }
 622
 623                         if (parsed_constraint.cls == NULL
 624                                         && parsed_constraint.same_as < 0) {
 625                                 is_memory_op = 1;
 626                         } else if (parsed_constraint.memory_possible) {
 627                                 /* TODO: match Load or Load/Store if memory possible is set */
 628                         }
 629                 }
 630                 in[i] = input;
 631
 632                 register_map[pos].use_input = 1;
 633                 register_map[pos].valid     = 1;
 634                 register_map[pos].memory    = is_memory_op;
 635                 register_map[pos].inout_pos = i;
 636                 register_map[pos].mode      = constraint->mode;
 637         }
 638
 639         /* parse clobbers */
 640         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 641                 const char                *c = get_id_str(clobbers[i]);
 642                 const arch_register_req_t *req;
 643
 644                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 645                         continue;
 646
 647                 req = parse_clobber(c);
 648                 out_reg_reqs[out_idx] = req;
 649                 ++out_idx;
 650         }
 651
 652         /* Attempt to make ASM node register pressure faithful.
 653          * (This does not work for complicated cases yet!)
 654          *
 655          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 656          * the smaller list). Then try to match each constraint of the smaller list
 657          * to 1 of the other list. If we can't match it, then we have to add a dummy
 658          * input/output to the other list
 659          *
 660          * FIXME: This is still broken in lots of cases. But at least better than
 661          *        before...
 662          * FIXME: need to do this per register class...
 663          */
 664         if (out_arity <= arity) {
 665                 int       orig_arity = arity;
 666                 int       in_size    = arity;
 667                 int       o;
 668                 bitset_t *used_ins = bitset_alloca(arity);
 669                 for (o = 0; o < out_arity; ++o) {
 670                         int   i;
 671                         const arch_register_req_t *outreq = out_reg_reqs[o];
 672
 673                         if (outreq->cls == NULL) {
 674                                 continue;
 675                         }
 676
 677                         for (i = 0; i < orig_arity; ++i) {
 678                                 const arch_register_req_t *inreq;
 679                                 if (bitset_is_set(used_ins, i))
 680                                         continue;
 681                                 inreq = in_reg_reqs[i];
 682                                 if (!can_match(outreq, inreq))
 683                                         continue;
 684                                 bitset_set(used_ins, i);
 685                                 break;
 686                         }
 687                         /* did we find any match? */
 688                         if (i < orig_arity)
 689                                 continue;
 690
 691                         /* we might need more space in the input arrays */
 692                         if (arity >= in_size) {
 693                                 const arch_register_req_t **new_in_reg_reqs;
 694                                 ir_node             **new_in;
 695
 696                                 in_size *= 2;
 697                                 new_in_reg_reqs
 698                                         = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
 699                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 700                                 new_in = ALLOCANZ(ir_node*, in_size);
 701                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 702
 703                                 in_reg_reqs = new_in_reg_reqs;
 704                                 in          = new_in;
 705                         }
 706
 707                         /* add a new (dummy) input which occupies the register */
 708                         assert(outreq->type & arch_register_req_type_limited);
 709                         in_reg_reqs[arity] = outreq;
 710                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 711                         be_dep_on_frame(in[arity]);
 712                         ++arity;
 713                 }
 714         } else {
 715                 int       i;
 716                 bitset_t *used_outs = bitset_alloca(out_arity);
 717                 int       orig_out_arity = out_arity;
 718                 for (i = 0; i < arity; ++i) {
 719                         int   o;
 720                         const arch_register_req_t *inreq = in_reg_reqs[i];
 721
 722                         if (inreq->cls == NULL) {
 723                                 continue;
 724                         }
 725
 726                         for (o = 0; o < orig_out_arity; ++o) {
 727                                 const arch_register_req_t *outreq;
 728                                 if (bitset_is_set(used_outs, o))
 729                                         continue;
 730                                 outreq = out_reg_reqs[o];
 731                                 if (!can_match(outreq, inreq))
 732                                         continue;
 733                                 bitset_set(used_outs, i);
 734                                 break;
 735                         }
 736                         /* did we find any match? */
 737                         if (o < orig_out_arity)
 738                                 continue;
 739
 740                         /* we might need more space in the output arrays */
 741                         if (out_arity >= out_size) {
 742                                 const arch_register_req_t **new_out_reg_reqs;
 743
 744                                 out_size *= 2;
 745                                 new_out_reg_reqs
 746                                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 747                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 748                                        out_arity * sizeof(new_out_reg_reqs[0]));
 749                                 out_reg_reqs = new_out_reg_reqs;
 750                         }
 751
 752                         /* add a new (dummy) output which occupies the register */
 753                         assert(inreq->type & arch_register_req_type_limited);
 754                         out_reg_reqs[out_arity] = inreq;
 755                         ++out_arity;
 756                 }
 757         }
 758
 759         /* append none register requirement for the memory output */
 760         if (out_arity + 1 >= out_size) {
 761                 const arch_register_req_t **new_out_reg_reqs;
 762
 763                 out_size = out_arity + 1;
 764                 new_out_reg_reqs
 765                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 766                 memcpy(new_out_reg_reqs, out_reg_reqs,
 767                            out_arity * sizeof(new_out_reg_reqs[0]));
 768                 out_reg_reqs = new_out_reg_reqs;
 769         }
 770
 771         /* add a new (dummy) output which occupies the register */
 772         out_reg_reqs[out_arity] = arch_no_register_req;
 773         ++out_arity;
 774
 775         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 776                                    get_ASM_text(node), register_map);
 777
 778         if (arity == 0)
 779                 be_dep_on_frame(new_node);
 780
 781         info = be_get_info(new_node);
 782         for (i = 0; i < out_arity; ++i) {
 783                 info->out_infos[i].req = out_reg_reqs[i];
 784         }
 785         set_ia32_in_req_all(new_node, in_reg_reqs);
 786
 787         SET_IA32_ORIG_NODE(new_node, node);
 788
 789         return new_node;
 790 }
 791
 792 ir_node *gen_CopyB(ir_node *node) {
 793         ir_node  *block    = NULL;
 794         ir_node  *src      = NULL;
 795         ir_node  *new_src  = NULL;
 796         ir_node  *dst      = NULL;
 797         ir_node  *new_dst  = NULL;
 798         ir_node  *mem      = NULL;
 799         ir_node  *new_mem  = NULL;
 800         ir_node  *res      = NULL;
 801         dbg_info *dbgi     = get_irn_dbg_info(node);
 802         int      size      = get_type_size_bytes(get_CopyB_type(node));
 803         int      rem;
 804
 805         switch (be_transformer) {
 806                 case TRANSFORMER_DEFAULT:
 807                         block    = be_transform_node(get_nodes_block(node));
 808                         src      = get_CopyB_src(node);
 809                         new_src  = be_transform_node(src);
 810                         dst      = get_CopyB_dst(node);
 811                         new_dst  = be_transform_node(dst);
 812                         mem      = get_CopyB_mem(node);
 813                         new_mem  = be_transform_node(mem);
 814                         break;
 815
 816 #ifdef FIRM_GRGEN_BE
 817                 case TRANSFORMER_PBQP:
 818                 case TRANSFORMER_RAND:
 819                         block    = get_nodes_block(node);
 820                         new_src  = get_CopyB_src(node);
 821                         new_dst  = get_CopyB_dst(node);
 822                         new_mem  = get_CopyB_mem(node);
 823                         break;
 824 #endif
 825
 826                 default: panic("invalid transformer");
 827         }
 828
 829         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 830         /* then we need the size explicitly in ECX.                    */
 831         if (size >= 32 * 4) {
 832                 rem = size & 0x3; /* size % 4 */
 833                 size >>= 2;
 834
 835                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 836                 be_dep_on_frame(res);
 837
 838                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 839         } else {
 840                 if (size == 0) {
 841                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 842                                    node);
 843                 }
 844                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 845         }
 846
 847         SET_IA32_ORIG_NODE(res, node);
 848
 849         return res;
 850 }
 851
 852 ir_node *gen_Proj_tls(ir_node *node) {
 853         ir_node  *block = NULL;
 854         dbg_info *dbgi  = NULL;
 855         ir_node  *res   = NULL;
 856
 857         switch (be_transformer) {
 858                 case TRANSFORMER_DEFAULT:
 859                         block = be_transform_node(get_nodes_block(node));
 860                         break;
 861
 862 #ifdef FIRM_GRGEN_BE
 863                 case TRANSFORMER_PBQP:
 864                 case TRANSFORMER_RAND:
 865                         block = get_nodes_block(node);
 866                         break;
 867 #endif
 868
 869                 default: panic("invalid transformer");
 870         }
 871
 872         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 873
 874         return res;
 875 }
 876
 877 ir_node *gen_Unknown(ir_node *node)
 878 {
 879         ir_mode *mode = get_irn_mode(node);
 880
 881         if (mode_is_float(mode)) {
 882                 if (ia32_cg_config.use_sse2) {
 883                         return ia32_new_Unknown_xmm(env_cg);
 884                 } else {
 885                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 886                         ir_graph *irg   = current_ir_graph;
 887                         dbg_info *dbgi  = get_irn_dbg_info(node);
 888                         ir_node  *block = get_irg_start_block(irg);
 889                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 890
 891                         be_dep_on_frame(ret);
 892                         return ret;
 893                 }
 894         } else if (ia32_mode_needs_gp_reg(mode)) {
 895                 return ia32_new_Unknown_gp(env_cg);
 896         } else {
 897                 panic("unsupported Unknown-Mode");
 898         }
 899         return NULL;
 900 }
 901
 902 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 903                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 904 {
 905         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 906         int                  same_as = constraint->same_as;
 907         arch_register_req_t *req;
 908
 909         if (same_as >= 0) {
 910                 const arch_register_req_t *other_constr;
 911
 912                 if (same_as >= n_outs)
 913                         panic("invalid output number in same_as constraint");
 914
 915                 other_constr     = out_reqs[same_as];
 916
 917                 req              = obstack_alloc(obst, sizeof(req[0]));
 918                 *req             = *other_constr;
 919                 req->type       |= arch_register_req_type_should_be_same;
 920                 req->other_same  = 1U << pos;
 921
 922                 /* switch constraints. This is because in firm we have same_as
 923                  * constraints on the output constraints while in the gcc asm syntax
 924                  * they are specified on the input constraints */
 925                 out_reqs[same_as] = req;
 926                 return other_constr;
 927         }
 928
 929         /* pure memory ops */
 930         if (constraint->cls == NULL) {
 931                 return &no_register_req;
 932         }
 933
 934         if (constraint->allowed_registers != 0
 935                         && !constraint->all_registers_allowed) {
 936                 unsigned *limited_ptr;
 937
 938                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 939                 memset(req, 0, sizeof(req[0]));
 940                 limited_ptr = (unsigned*) (req+1);
 941
 942                 req->type    = arch_register_req_type_limited;
 943                 *limited_ptr = constraint->allowed_registers;
 944                 req->limited = limited_ptr;
 945         } else {
 946                 req       = obstack_alloc(obst, sizeof(req[0]));
 947                 memset(req, 0, sizeof(req[0]));
 948                 req->type = arch_register_req_type_normal;
 949         }
 950         req->cls = constraint->cls;
 951
 952         return req;
 953 }
 954
 955 const arch_register_req_t *parse_clobber(const char *clobber)
 956 {
 957         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 958         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 959         arch_register_req_t   *req;
 960         unsigned              *limited;
 961
 962         if (reg == NULL) {
 963                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 964         }
 965
 966         assert(reg->index < 32);
 967
 968         limited  = obstack_alloc(obst, sizeof(limited[0]));
 969         *limited = 1 << reg->index;
 970
 971         req          = obstack_alloc(obst, sizeof(req[0]));
 972         memset(req, 0, sizeof(req[0]));
 973         req->type    = arch_register_req_type_limited;
 974         req->cls     = arch_register_get_class(reg);
 975         req->limited = limited;
 976
 977         return req;
 978 }
 979
 980
 981 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 982                        ir_node *const other)
 983 {
 984         if (get_nodes_block(other) != block)
 985                 return 0;
 986
 987         if (is_Sync(other)) {
 988                 int i;
 989
 990                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 991                         ir_node *const pred = get_Sync_pred(other, i);
 992
 993                         if (get_nodes_block(pred) != block)
 994                                 continue;
 995
 996                         /* Do not block ourselves from getting eaten */
 997                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 998                                 continue;
 999
1000                         if (!heights_reachable_in_block(heights, pred, am_candidate))
1001                                 continue;
1002
1003                         return 1;
1004                 }
1005
1006                 return 0;
1007         } else {
1008                 /* Do not block ourselves from getting eaten */
1009                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
1010                         return 0;
1011
1012                 if (!heights_reachable_in_block(heights, other, am_candidate))
1013                         return 0;
1014
1015                 return 1;
1016         }
1017 }
1018
1019 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
1020 {
1021         int          minus         = 0;
1022         tarval      *offset        = NULL;
1023         int          offset_sign   = 0;
1024         long         val = 0;
1025         ir_entity   *symconst_ent  = NULL;
1026         int          symconst_sign = 0;
1027         ir_mode     *mode;
1028         ir_node     *cnst          = NULL;
1029         ir_node     *symconst      = NULL;
1030         ir_node     *new_node;
1031
1032         mode = get_irn_mode(node);
1033         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
1034                 return NULL;
1035         }
1036
1037         if (is_Minus(node)) {
1038                 minus = 1;
1039                 node  = get_Minus_op(node);
1040         }
1041
1042         if (is_Const(node)) {
1043                 cnst        = node;
1044                 symconst    = NULL;
1045                 offset_sign = minus;
1046         } else if (is_SymConst(node)) {
1047                 cnst          = NULL;
1048                 symconst      = node;
1049                 symconst_sign = minus;
1050         } else if (is_Add(node)) {
1051                 ir_node *left  = get_Add_left(node);
1052                 ir_node *right = get_Add_right(node);
1053                 if (is_Const(left) && is_SymConst(right)) {
1054                         cnst          = left;
1055                         symconst      = right;
1056                         symconst_sign = minus;
1057                         offset_sign   = minus;
1058                 } else if (is_SymConst(left) && is_Const(right)) {
1059                         cnst          = right;
1060                         symconst      = left;
1061                         symconst_sign = minus;
1062                         offset_sign   = minus;
1063                 }
1064         } else if (is_Sub(node)) {
1065                 ir_node *left  = get_Sub_left(node);
1066                 ir_node *right = get_Sub_right(node);
1067                 if (is_Const(left) && is_SymConst(right)) {
1068                         cnst          = left;
1069                         symconst      = right;
1070                         symconst_sign = !minus;
1071                         offset_sign   = minus;
1072                 } else if (is_SymConst(left) && is_Const(right)) {
1073                         cnst          = right;
1074                         symconst      = left;
1075                         symconst_sign = minus;
1076                         offset_sign   = !minus;
1077                 }
1078         } else {
1079                 return NULL;
1080         }
1081
1082         if (cnst != NULL) {
1083                 offset = get_Const_tarval(cnst);
1084                 if (tarval_is_long(offset)) {
1085                         val = get_tarval_long(offset);
1086                 } else {
1087                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
1088                                    "long?\n", cnst);
1089                         return NULL;
1090                 }
1091
1092                 if (!check_immediate_constraint(val, immediate_constraint_type))
1093                         return NULL;
1094         }
1095         if (symconst != NULL) {
1096                 if (immediate_constraint_type != 0) {
1097                         /* we need full 32bits for symconsts */
1098                         return NULL;
1099                 }
1100
1101                 /* unfortunately the assembler/linker doesn't support -symconst */
1102                 if (symconst_sign)
1103                         return NULL;
1104
1105                 if (get_SymConst_kind(symconst) != symconst_addr_ent)
1106                         return NULL;
1107                 symconst_ent = get_SymConst_entity(symconst);
1108         }
1109         if (cnst == NULL && symconst == NULL)
1110                 return NULL;
1111
1112         if (offset_sign && offset != NULL) {
1113                 offset = tarval_neg(offset);
1114         }
1115
1116         new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val);
1117
1118         return new_node;
1119 }