nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33 #include "bitset.h"
  34
  35 #include "../betranshlp.h"
  36 #include "../beirg.h"
  37 #include "../beabi.h"
  38
  39 #include "ia32_architecture.h"
  40 #include "ia32_common_transform.h"
  41 #include "ia32_new_nodes.h"
  42
  43 #include "gen_ia32_new_nodes.h"
  44 #include "gen_ia32_regalloc_if.h"
  45
  46 /** hold the current code generator during transformation */
  47 ia32_code_gen_t *env_cg = NULL;
  48
  49 heights_t *heights = NULL;
  50
  51 static const arch_register_req_t no_register_req = {
  52         arch_register_req_type_none,
  53         NULL,                         /* regclass */
  54         NULL,                         /* limit bitset */
  55         0,                            /* same pos */
  56         0                             /* different pos */
  57 };
  58
  59 static int check_immediate_constraint(long val, char immediate_constraint_type)
  60 {
  61         switch (immediate_constraint_type) {
  62                 case 0:
  63                 case 'i': return 1;
  64
  65                 case 'I': return    0 <= val && val <=  31;
  66                 case 'J': return    0 <= val && val <=  63;
  67                 case 'K': return -128 <= val && val <= 127;
  68                 case 'L': return val == 0xff || val == 0xffff;
  69                 case 'M': return    0 <= val && val <=   3;
  70                 case 'N': return    0 <= val && val <= 255;
  71                 case 'O': return    0 <= val && val <= 127;
  72
  73                 default: panic("Invalid immediate constraint found");
  74         }
  75 }
  76
  77 /**
  78  * Get a primitive type for a mode with alignment 16.
  79  */
  80 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  81 {
  82         ir_type *res = pmap_get(types, mode);
  83         if (res != NULL)
  84                 return res;
  85
  86         res = new_type_primitive(mode);
  87         if (get_mode_size_bits(mode) >= 80) {
  88                 set_type_alignment_bytes(res, 16);
  89         }
  90         pmap_insert(types, mode, res);
  91         return res;
  92 }
  93
  94 ir_entity *create_float_const_entity(ir_node *cnst)
  95 {
  96         ia32_isa_t       *isa = env_cg->isa;
  97         tarval           *tv  = get_Const_tarval(cnst);
  98         ir_entity        *res = pmap_get(isa->tv_ent, tv);
  99         ir_initializer_t *initializer;
 100         ir_mode          *mode;
 101         ir_type          *tp;
 102
 103         if (res != NULL)
 104                 return res;
 105
 106         mode = get_tarval_mode(tv);
 107
 108         if (! ia32_cg_config.use_sse2) {
 109                 /* try to reduce the mode to produce smaller sized entities */
 110                 if (mode != mode_F) {
 111                         if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 112                                 mode = mode_F;
 113                                 tv = tarval_convert_to(tv, mode);
 114                         } else if (mode != mode_D) {
 115                                 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 116                                         mode = mode_D;
 117                                         tv = tarval_convert_to(tv, mode);
 118                                 }
 119                         }
 120                 }
 121         }
 122
 123         tp  = ia32_get_prim_type(isa->types, mode);
 124         res = new_entity(get_glob_type(), id_unique("C%u"), tp);
 125         set_entity_ld_ident(res, get_entity_ident(res));
 126         set_entity_visibility(res, ir_visibility_private);
 127         add_entity_linkage(res, IR_LINKAGE_CONSTANT);
 128
 129         initializer = create_initializer_tarval(tv);
 130         set_entity_initializer(res, initializer);
 131
 132         pmap_insert(isa->tv_ent, tv, res);
 133         return res;
 134 }
 135
 136 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 137 {
 138         ir_graph *irg         = current_ir_graph;
 139         ir_node  *start_block = get_irg_start_block(irg);
 140         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 141                         symconst_sign, no_pic_adjust, val);
 142         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 143
 144         return immediate;
 145 }
 146
 147 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 148 {
 149         const arch_register_t       *reg = NULL;
 150         int                          c;
 151         size_t                       r;
 152         const arch_register_class_t *cls;
 153
 154         /* TODO: construct a hashmap instead of doing linear search for clobber
 155          * register */
 156         for (c = 0; c < N_CLASSES; ++c) {
 157                 cls = & ia32_reg_classes[c];
 158                 for (r = 0; r < cls->n_regs; ++r) {
 159                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 160                         if (strcmp(temp_reg->name, clobber) == 0
 161                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 162                                 reg = temp_reg;
 163                                 break;
 164                         }
 165                 }
 166                 if (reg != NULL)
 167                         break;
 168         }
 169
 170         return reg;
 171 }
 172
 173 int ia32_mode_needs_gp_reg(ir_mode *mode)
 174 {
 175         if (mode == mode_fpcw)
 176                 return 0;
 177         if (get_mode_size_bits(mode) > 32)
 178                 return 0;
 179         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 180 }
 181
 182 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 183                            int is_output)
 184 {
 185         char                         immediate_type     = '\0';
 186         unsigned                     limited            = 0;
 187         const arch_register_class_t *cls                = NULL;
 188         int                          memory_possible       = 0;
 189         int                          all_registers_allowed = 0;
 190         int                          p;
 191         int                          same_as = -1;
 192
 193         memset(constraint, 0, sizeof(constraint[0]));
 194         constraint->same_as = -1;
 195
 196         if (*c == 0) {
 197                 /* a memory constraint: no need to do anything in backend about it
 198                  * (the dependencies are already respected by the memory edge of
 199                  * the node) */
 200                 return;
 201         }
 202
 203         /* TODO: improve error messages with node and source info. (As users can
 204          * easily hit these) */
 205         while (*c != 0) {
 206                 switch (*c) {
 207                 case ' ':
 208                 case '\t':
 209                 case '\n':
 210                         break;
 211
 212                 /* Skip out/in-out marker */
 213                 case '=': break;
 214                 case '+': break;
 215
 216                 case '&': break;
 217
 218                 case '*':
 219                         ++c;
 220                         break;
 221                 case '#':
 222                         while (*c != 0 && *c != ',')
 223                                 ++c;
 224                         break;
 225
 226                 case 'a':
 227                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 228                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 229                         limited |= 1 << REG_EAX;
 230                         break;
 231                 case 'b':
 232                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 233                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 234                         limited |= 1 << REG_EBX;
 235                         break;
 236                 case 'c':
 237                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 238                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 239                         limited |= 1 << REG_ECX;
 240                         break;
 241                 case 'd':
 242                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 243                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 244                         limited |= 1 << REG_EDX;
 245                         break;
 246                 case 'D':
 247                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 248                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 249                         limited |= 1 << REG_EDI;
 250                         break;
 251                 case 'S':
 252                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 253                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 254                         limited |= 1 << REG_ESI;
 255                         break;
 256                 case 'Q':
 257                 case 'q':
 258                         /* q means lower part of the regs only, this makes no
 259                          * difference to Q for us (we only assign whole registers) */
 260                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 261                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 262                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 263                                    1 << REG_EDX;
 264                         break;
 265                 case 'A':
 266                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 267                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 268                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 269                         break;
 270                 case 'l':
 271                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 272                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 273                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 274                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 275                                    1 << REG_EBP;
 276                         break;
 277
 278                 case 'R':
 279                 case 'r':
 280                 case 'p':
 281                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 282                                 panic("multiple register classes not supported");
 283                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 284                         all_registers_allowed = 1;
 285                         break;
 286
 287                 case 'f':
 288                 case 't':
 289                 case 'u':
 290                         /* TODO: mark values so the x87 simulator knows about t and u */
 291                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 292                                 panic("multiple register classes not supported");
 293                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 294                         all_registers_allowed = 1;
 295                         break;
 296
 297                 case 'Y':
 298                 case 'x':
 299                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 300                                 panic("multiple register classes not supproted");
 301                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 302                         all_registers_allowed = 1;
 303                         break;
 304
 305                 case 'I':
 306                 case 'J':
 307                 case 'K':
 308                 case 'L':
 309                 case 'M':
 310                 case 'N':
 311                 case 'O':
 312                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 313                                 panic("multiple register classes not supported");
 314                         if (immediate_type != '\0')
 315                                 panic("multiple immediate types not supported");
 316                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 317                         immediate_type = *c;
 318                         break;
 319                 case 'n':
 320                 case 'i':
 321                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 322                                 panic("multiple register classes not supported");
 323                         if (immediate_type != '\0')
 324                                 panic("multiple immediate types not supported");
 325                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 326                         immediate_type = 'i';
 327                         break;
 328
 329                 case 'X':
 330                 case 'g':
 331                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 332                                 panic("multiple register classes not supported");
 333                         if (immediate_type != '\0')
 334                                 panic("multiple immediate types not supported");
 335                         immediate_type        = 'i';
 336                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 337                         all_registers_allowed = 1;
 338                         memory_possible       = 1;
 339                         break;
 340
 341                 case '0':
 342                 case '1':
 343                 case '2':
 344                 case '3':
 345                 case '4':
 346                 case '5':
 347                 case '6':
 348                 case '7':
 349                 case '8':
 350                 case '9':
 351                         if (is_output)
 352                                 panic("can only specify same constraint on input");
 353
 354                         sscanf(c, "%d%n", &same_as, &p);
 355                         if (same_as >= 0) {
 356                                 c += p;
 357                                 continue;
 358                         }
 359                         break;
 360
 361                 case 'm':
 362                 case 'o':
 363                 case 'V':
 364                         /* memory constraint no need to do anything in backend about it
 365                          * (the dependencies are already respected by the memory edge of
 366                          * the node) */
 367                         memory_possible = 1;
 368                         break;
 369
 370                 case 'E': /* no float consts yet */
 371                 case 'F': /* no float consts yet */
 372                 case 's': /* makes no sense on x86 */
 373                 case '<': /* no autodecrement on x86 */
 374                 case '>': /* no autoincrement on x86 */
 375                 case 'C': /* sse constant not supported yet */
 376                 case 'G': /* 80387 constant not supported yet */
 377                 case 'y': /* we don't support mmx registers yet */
 378                 case 'Z': /* not available in 32 bit mode */
 379                 case 'e': /* not available in 32 bit mode */
 380                         panic("unsupported asm constraint '%c' found in (%+F)",
 381                               *c, current_ir_graph);
 382                         break;
 383                 default:
 384                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 385                               current_ir_graph);
 386                         break;
 387                 }
 388                 ++c;
 389         }
 390
 391         if (same_as >= 0) {
 392                 if (cls != NULL)
 393                         panic("same as and register constraint not supported");
 394                 if (immediate_type != '\0')
 395                         panic("same as and immediate constraint not supported");
 396         }
 397
 398         if (cls == NULL && same_as < 0) {
 399                 if (!memory_possible)
 400                         panic("no constraint specified for assembler input");
 401         }
 402
 403         constraint->same_as               = same_as;
 404         constraint->cls                   = cls;
 405         constraint->allowed_registers     = limited;
 406         constraint->all_registers_allowed = all_registers_allowed;
 407         constraint->memory_possible       = memory_possible;
 408         constraint->immediate_type        = immediate_type;
 409 }
 410
 411 static bool can_match(const arch_register_req_t *in,
 412                       const arch_register_req_t *out)
 413 {
 414         if (in->cls != out->cls)
 415                 return false;
 416         if ( (in->type & arch_register_req_type_limited) == 0
 417                 || (out->type & arch_register_req_type_limited) == 0 )
 418                 return true;
 419
 420         return (*in->limited & *out->limited) != 0;
 421 }
 422
 423 static inline ir_node *get_new_node(ir_node *node)
 424 {
 425 #ifdef FIRM_GRGEN_BE
 426         if (be_transformer == TRANSFORMER_DEFAULT) {
 427                 return be_transform_node(node);
 428         } else {
 429                 return node;
 430         }
 431 #else
 432         return be_transform_node(node);
 433 #endif
 434 }
 435
 436 ir_node *gen_ASM(ir_node *node)
 437 {
 438         ir_node                    *block     = get_nodes_block(node);
 439         ir_node                    *new_block = get_new_node(block);
 440         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 441         int                         i, arity;
 442         int                         value_arity;
 443         int                         out_idx;
 444         ir_node                   **in;
 445         ir_node                    *new_node;
 446         int                         out_arity;
 447         int                         n_out_constraints;
 448         int                         n_clobbers;
 449         const arch_register_req_t **out_reg_reqs;
 450         const arch_register_req_t **in_reg_reqs;
 451         ia32_asm_reg_t             *register_map;
 452         unsigned                    reg_map_size = 0;
 453         struct obstack             *obst;
 454         const ir_asm_constraint    *in_constraints;
 455         const ir_asm_constraint    *out_constraints;
 456         ident                     **clobbers;
 457         int                         clobbers_flags = 0;
 458         unsigned                    clobber_bits[N_CLASSES];
 459         int                         out_size;
 460         backend_info_t             *info;
 461
 462         memset(&clobber_bits, 0, sizeof(clobber_bits));
 463
 464         /* workaround for lots of buggy code out there as most people think volatile
 465          * asm is enough for everything and forget the flags (linux kernel, etc.)
 466          */
 467         if (get_irn_pinned(node) == op_pin_state_pinned) {
 468                 clobbers_flags = 1;
 469         }
 470
 471         arity = get_irn_arity(node);
 472         in    = ALLOCANZ(ir_node*, arity);
 473
 474         clobbers   = get_ASM_clobbers(node);
 475         n_clobbers = 0;
 476         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 477                 const arch_register_req_t *req;
 478                 const char                *c = get_id_str(clobbers[i]);
 479
 480                 if (strcmp(c, "memory") == 0)
 481                         continue;
 482                 if (strcmp(c, "cc") == 0) {
 483                         clobbers_flags = 1;
 484                         continue;
 485                 }
 486
 487                 req = parse_clobber(c);
 488                 clobber_bits[req->cls->index] |= *req->limited;
 489
 490                 n_clobbers++;
 491         }
 492         n_out_constraints = get_ASM_n_output_constraints(node);
 493         out_arity         = n_out_constraints + n_clobbers;
 494
 495         in_constraints  = get_ASM_input_constraints(node);
 496         out_constraints = get_ASM_output_constraints(node);
 497
 498         /* determine size of register_map */
 499         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 500                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 501                 if (constraint->pos > reg_map_size)
 502                         reg_map_size = constraint->pos;
 503         }
 504         for (i = 0; i < arity; ++i) {
 505                 const ir_asm_constraint *constraint = &in_constraints[i];
 506                 if (constraint->pos > reg_map_size)
 507                         reg_map_size = constraint->pos;
 508         }
 509         ++reg_map_size;
 510
 511         obst         = get_irg_obstack(current_ir_graph);
 512         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 513         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 514
 515         /* construct output constraints */
 516         out_size = out_arity + 1;
 517         out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
 518
 519         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 520                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 521                 const char                *c       = get_id_str(constraint->constraint);
 522                 unsigned                   pos        = constraint->pos;
 523                 constraint_t               parsed_constraint;
 524                 const arch_register_req_t *req;
 525
 526                 parse_asm_constraints(&parsed_constraint, c, 1);
 527                 req = make_register_req(&parsed_constraint, n_out_constraints,
 528                                         out_reg_reqs, out_idx);
 529                 out_reg_reqs[out_idx] = req;
 530
 531                 register_map[pos].use_input = 0;
 532                 register_map[pos].valid     = 1;
 533                 register_map[pos].memory    = 0;
 534                 register_map[pos].inout_pos = out_idx;
 535                 register_map[pos].mode      = constraint->mode;
 536         }
 537
 538         /* inputs + input constraints */
 539         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 540         for (i = 0; i < arity; ++i) {
 541                 ir_node                   *pred         = get_irn_n(node, i);
 542                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 543                 ident                     *constr_id    = constraint->constraint;
 544                 const char                *c            = get_id_str(constr_id);
 545                 unsigned                   pos          = constraint->pos;
 546                 int                        is_memory_op = 0;
 547                 ir_node                   *input        = NULL;
 548                 unsigned                   r_clobber_bits;
 549                 constraint_t               parsed_constraint;
 550                 const arch_register_req_t *req;
 551
 552                 parse_asm_constraints(&parsed_constraint, c, 0);
 553                 if (parsed_constraint.cls != NULL) {
 554                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 555                         if (r_clobber_bits != 0) {
 556                                 if (parsed_constraint.all_registers_allowed) {
 557                                         parsed_constraint.all_registers_allowed = 0;
 558                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 559                                                         parsed_constraint.cls,
 560                                                         &parsed_constraint.allowed_registers);
 561                                 }
 562                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 563                         }
 564                 }
 565
 566                 req = make_register_req(&parsed_constraint, n_out_constraints,
 567                                         out_reg_reqs, i);
 568                 in_reg_reqs[i] = req;
 569
 570                 if (parsed_constraint.immediate_type != '\0') {
 571                         char imm_type = parsed_constraint.immediate_type;
 572                         input = try_create_Immediate(pred, imm_type);
 573                 }
 574
 575                 if (input == NULL) {
 576                         ir_node *pred = get_irn_n(node, i);
 577                         input = get_new_node(pred);
 578
 579                         if (parsed_constraint.cls == NULL
 580                                         && parsed_constraint.same_as < 0) {
 581                                 is_memory_op = 1;
 582                         } else if (parsed_constraint.memory_possible) {
 583                                 /* TODO: match Load or Load/Store if memory possible is set */
 584                         }
 585                 }
 586                 in[i] = input;
 587
 588                 register_map[pos].use_input = 1;
 589                 register_map[pos].valid     = 1;
 590                 register_map[pos].memory    = is_memory_op;
 591                 register_map[pos].inout_pos = i;
 592                 register_map[pos].mode      = constraint->mode;
 593         }
 594
 595         /* parse clobbers */
 596         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 597                 const char                *c = get_id_str(clobbers[i]);
 598                 const arch_register_req_t *req;
 599
 600                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 601                         continue;
 602
 603                 req = parse_clobber(c);
 604                 out_reg_reqs[out_idx] = req;
 605                 ++out_idx;
 606         }
 607
 608         /* count inputs which are real values (and not memory) */
 609         value_arity = 0;
 610         for (i = 0; i < arity; ++i) {
 611                 ir_node *in = get_irn_n(node, i);
 612                 if (get_irn_mode(in) == mode_M)
 613                         continue;
 614                 ++value_arity;
 615         }
 616
 617         /* Attempt to make ASM node register pressure faithful.
 618          * (This does not work for complicated cases yet!)
 619          *
 620          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 621          * the smaller list). Then try to match each constraint of the smaller list
 622          * to 1 of the other list. If we can't match it, then we have to add a dummy
 623          * input/output to the other list
 624          *
 625          * FIXME: This is still broken in lots of cases. But at least better than
 626          *        before...
 627          * FIXME: need to do this per register class...
 628          */
 629         if (out_arity <= value_arity) {
 630                 int       orig_arity = arity;
 631                 int       in_size    = arity;
 632                 int       o;
 633                 bitset_t *used_ins = bitset_alloca(arity);
 634                 for (o = 0; o < out_arity; ++o) {
 635                         int   i;
 636                         const arch_register_req_t *outreq = out_reg_reqs[o];
 637
 638                         if (outreq->cls == NULL) {
 639                                 continue;
 640                         }
 641
 642                         for (i = 0; i < orig_arity; ++i) {
 643                                 const arch_register_req_t *inreq;
 644                                 if (bitset_is_set(used_ins, i))
 645                                         continue;
 646                                 inreq = in_reg_reqs[i];
 647                                 if (!can_match(outreq, inreq))
 648                                         continue;
 649                                 bitset_set(used_ins, i);
 650                                 break;
 651                         }
 652                         /* did we find any match? */
 653                         if (i < orig_arity)
 654                                 continue;
 655
 656                         /* we might need more space in the input arrays */
 657                         if (arity >= in_size) {
 658                                 const arch_register_req_t **new_in_reg_reqs;
 659                                 ir_node             **new_in;
 660
 661                                 in_size *= 2;
 662                                 new_in_reg_reqs
 663                                         = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
 664                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 665                                 new_in = ALLOCANZ(ir_node*, in_size);
 666                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 667
 668                                 in_reg_reqs = new_in_reg_reqs;
 669                                 in          = new_in;
 670                         }
 671
 672                         /* add a new (dummy) input which occupies the register */
 673                         assert(outreq->type & arch_register_req_type_limited);
 674                         in_reg_reqs[arity] = outreq;
 675                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 676                         be_dep_on_frame(in[arity]);
 677                         ++arity;
 678                 }
 679         } else {
 680                 int       i;
 681                 bitset_t *used_outs = bitset_alloca(out_arity);
 682                 int       orig_out_arity = out_arity;
 683                 for (i = 0; i < arity; ++i) {
 684                         int   o;
 685                         const arch_register_req_t *inreq = in_reg_reqs[i];
 686
 687                         if (inreq->cls == NULL) {
 688                                 continue;
 689                         }
 690
 691                         for (o = 0; o < orig_out_arity; ++o) {
 692                                 const arch_register_req_t *outreq;
 693                                 if (bitset_is_set(used_outs, o))
 694                                         continue;
 695                                 outreq = out_reg_reqs[o];
 696                                 if (!can_match(outreq, inreq))
 697                                         continue;
 698                                 bitset_set(used_outs, i);
 699                                 break;
 700                         }
 701                         /* did we find any match? */
 702                         if (o < orig_out_arity)
 703                                 continue;
 704
 705                         /* we might need more space in the output arrays */
 706                         if (out_arity >= out_size) {
 707                                 const arch_register_req_t **new_out_reg_reqs;
 708
 709                                 out_size *= 2;
 710                                 new_out_reg_reqs
 711                                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 712                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 713                                        out_arity * sizeof(new_out_reg_reqs[0]));
 714                                 out_reg_reqs = new_out_reg_reqs;
 715                         }
 716
 717                         /* add a new (dummy) output which occupies the register */
 718                         assert(inreq->type & arch_register_req_type_limited);
 719                         out_reg_reqs[out_arity] = inreq;
 720                         ++out_arity;
 721                 }
 722         }
 723
 724         /* append none register requirement for the memory output */
 725         if (out_arity + 1 >= out_size) {
 726                 const arch_register_req_t **new_out_reg_reqs;
 727
 728                 out_size = out_arity + 1;
 729                 new_out_reg_reqs
 730                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 731                 memcpy(new_out_reg_reqs, out_reg_reqs,
 732                            out_arity * sizeof(new_out_reg_reqs[0]));
 733                 out_reg_reqs = new_out_reg_reqs;
 734         }
 735
 736         /* add a new (dummy) output which occupies the register */
 737         out_reg_reqs[out_arity] = arch_no_register_req;
 738         ++out_arity;
 739
 740         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 741                                    get_ASM_text(node), register_map);
 742
 743         if (arity == 0)
 744                 be_dep_on_frame(new_node);
 745
 746         info = be_get_info(new_node);
 747         for (i = 0; i < out_arity; ++i) {
 748                 info->out_infos[i].req = out_reg_reqs[i];
 749         }
 750         set_ia32_in_req_all(new_node, in_reg_reqs);
 751
 752         SET_IA32_ORIG_NODE(new_node, node);
 753
 754         return new_node;
 755 }
 756
 757 ir_node *gen_CopyB(ir_node *node)
 758 {
 759         ir_node  *block    = get_new_node(get_nodes_block(node));
 760         ir_node  *src      = get_CopyB_src(node);
 761         ir_node  *new_src  = get_new_node(src);
 762         ir_node  *dst      = get_CopyB_dst(node);
 763         ir_node  *new_dst  = get_new_node(dst);
 764         ir_node  *mem      = get_CopyB_mem(node);
 765         ir_node  *new_mem  = get_new_node(mem);
 766         ir_node  *res      = NULL;
 767         dbg_info *dbgi     = get_irn_dbg_info(node);
 768         int      size      = get_type_size_bytes(get_CopyB_type(node));
 769         int      rem;
 770
 771         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 772         /* then we need the size explicitly in ECX.                    */
 773         if (size >= 32 * 4) {
 774                 rem = size & 0x3; /* size % 4 */
 775                 size >>= 2;
 776
 777                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 778                 be_dep_on_frame(res);
 779
 780                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 781         } else {
 782                 if (size == 0) {
 783                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 784                                    node);
 785                 }
 786                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 787         }
 788
 789         SET_IA32_ORIG_NODE(res, node);
 790
 791         return res;
 792 }
 793
 794 ir_node *gen_Proj_tls(ir_node *node)
 795 {
 796         ir_node *block = get_new_node(get_nodes_block(node));
 797         ir_node *res   = NULL;
 798
 799         res = new_bd_ia32_LdTls(NULL, block, mode_Iu);
 800
 801         return res;
 802 }
 803
 804 ir_node *gen_Unknown(ir_node *node)
 805 {
 806         ir_mode  *mode  = get_irn_mode(node);
 807         ir_graph *irg   = current_ir_graph;
 808         dbg_info *dbgi  = get_irn_dbg_info(node);
 809         ir_node  *block = get_irg_start_block(irg);
 810         ir_node  *res   = NULL;
 811
 812         if (mode_is_float(mode)) {
 813                 if (ia32_cg_config.use_sse2) {
 814                         res = new_bd_ia32_xUnknown(dbgi, block);
 815                 } else {
 816                         res = new_bd_ia32_vfldz(dbgi, block);
 817                 }
 818         } else if (ia32_mode_needs_gp_reg(mode)) {
 819                 res = new_bd_ia32_Unknown(dbgi, block);
 820         } else {
 821                 panic("unsupported Unknown-Mode");
 822         }
 823
 824         be_dep_on_frame(res);
 825         return res;
 826 }
 827
 828 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 829                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 830 {
 831         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 832         int                  same_as = constraint->same_as;
 833         arch_register_req_t *req;
 834
 835         if (same_as >= 0) {
 836                 const arch_register_req_t *other_constr;
 837
 838                 if (same_as >= n_outs)
 839                         panic("invalid output number in same_as constraint");
 840
 841                 other_constr     = out_reqs[same_as];
 842
 843                 req              = obstack_alloc(obst, sizeof(req[0]));
 844                 *req             = *other_constr;
 845                 req->type       |= arch_register_req_type_should_be_same;
 846                 req->other_same  = 1U << pos;
 847
 848                 /* switch constraints. This is because in firm we have same_as
 849                  * constraints on the output constraints while in the gcc asm syntax
 850                  * they are specified on the input constraints */
 851                 out_reqs[same_as] = req;
 852                 return other_constr;
 853         }
 854
 855         /* pure memory ops */
 856         if (constraint->cls == NULL) {
 857                 return &no_register_req;
 858         }
 859
 860         if (constraint->allowed_registers != 0
 861                         && !constraint->all_registers_allowed) {
 862                 unsigned *limited_ptr;
 863
 864                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 865                 memset(req, 0, sizeof(req[0]));
 866                 limited_ptr = (unsigned*) (req+1);
 867
 868                 req->type    = arch_register_req_type_limited;
 869                 *limited_ptr = constraint->allowed_registers;
 870                 req->limited = limited_ptr;
 871         } else {
 872                 req       = obstack_alloc(obst, sizeof(req[0]));
 873                 memset(req, 0, sizeof(req[0]));
 874                 req->type = arch_register_req_type_normal;
 875         }
 876         req->cls = constraint->cls;
 877
 878         return req;
 879 }
 880
 881 const arch_register_req_t *parse_clobber(const char *clobber)
 882 {
 883         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 884         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 885         arch_register_req_t   *req;
 886         unsigned              *limited;
 887
 888         if (reg == NULL) {
 889                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 890         }
 891
 892         assert(reg->index < 32);
 893
 894         limited  = obstack_alloc(obst, sizeof(limited[0]));
 895         *limited = 1 << reg->index;
 896
 897         req          = obstack_alloc(obst, sizeof(req[0]));
 898         memset(req, 0, sizeof(req[0]));
 899         req->type    = arch_register_req_type_limited;
 900         req->cls     = arch_register_get_class(reg);
 901         req->limited = limited;
 902
 903         return req;
 904 }
 905
 906
 907 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 908                        ir_node *const other)
 909 {
 910         if (get_nodes_block(other) != block)
 911                 return 0;
 912
 913         if (is_Sync(other)) {
 914                 int i;
 915
 916                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 917                         ir_node *const pred = get_Sync_pred(other, i);
 918
 919                         if (get_nodes_block(pred) != block)
 920                                 continue;
 921
 922                         /* Do not block ourselves from getting eaten */
 923                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 924                                 continue;
 925
 926                         if (!heights_reachable_in_block(heights, pred, am_candidate))
 927                                 continue;
 928
 929                         return 1;
 930                 }
 931
 932                 return 0;
 933         } else {
 934                 /* Do not block ourselves from getting eaten */
 935                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
 936                         return 0;
 937
 938                 if (!heights_reachable_in_block(heights, other, am_candidate))
 939                         return 0;
 940
 941                 return 1;
 942         }
 943 }
 944
 945 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
 946 {
 947         long         val = 0;
 948         ir_entity   *symconst_ent  = NULL;
 949         ir_mode     *mode;
 950         ir_node     *cnst          = NULL;
 951         ir_node     *symconst      = NULL;
 952         ir_node     *new_node;
 953
 954         mode = get_irn_mode(node);
 955         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
 956                 return NULL;
 957         }
 958
 959         if (is_Const(node)) {
 960                 cnst     = node;
 961                 symconst = NULL;
 962         } else if (is_Global(node)) {
 963                 cnst     = NULL;
 964                 symconst = node;
 965         } else if (is_Add(node)) {
 966                 ir_node *left  = get_Add_left(node);
 967                 ir_node *right = get_Add_right(node);
 968                 if (is_Const(left) && is_Global(right)) {
 969                         cnst     = left;
 970                         symconst = right;
 971                 } else if (is_Global(left) && is_Const(right)) {
 972                         cnst     = right;
 973                         symconst = left;
 974                 }
 975         } else {
 976                 return NULL;
 977         }
 978
 979         if (cnst != NULL) {
 980                 tarval *offset = get_Const_tarval(cnst);
 981                 if (!tarval_is_long(offset)) {
 982                         ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
 983                         return NULL;
 984                 }
 985
 986                 val = get_tarval_long(offset);
 987                 if (!check_immediate_constraint(val, immediate_constraint_type))
 988                         return NULL;
 989         }
 990         if (symconst != NULL) {
 991                 if (immediate_constraint_type != 0) {
 992                         /* we need full 32bits for symconsts */
 993                         return NULL;
 994                 }
 995
 996                 symconst_ent = get_Global_entity(symconst);
 997         }
 998         if (cnst == NULL && symconst == NULL)
 999                 return NULL;
1000
1001         new_node = ia32_create_Immediate(symconst_ent, 0, val);
1002         return new_node;
1003 }