2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
35 #include "betranshlp.h"
39 #include "ia32_architecture.h"
40 #include "ia32_common_transform.h"
41 #include "ia32_new_nodes.h"
43 #include "gen_ia32_new_nodes.h"
44 #include "gen_ia32_regalloc_if.h"
46 ir_heights_t *ia32_heights = NULL;
48 static int check_immediate_constraint(long val, char immediate_constraint_type)
50 switch (immediate_constraint_type) {
54 case 'I': return 0 <= val && val <= 31;
55 case 'J': return 0 <= val && val <= 63;
56 case 'K': return -128 <= val && val <= 127;
57 case 'L': return val == 0xff || val == 0xffff;
58 case 'M': return 0 <= val && val <= 3;
59 case 'N': return 0 <= val && val <= 255;
60 case 'O': return 0 <= val && val <= 127;
62 default: panic("Invalid immediate constraint found");
66 ir_type *ia32_get_prim_type(const ir_mode *mode)
68 if (mode == ia32_mode_E) {
71 return get_type_for_mode(mode);
75 ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
78 ir_entity *res = pmap_get(ir_entity, isa->tv_ent, tv);
79 ir_initializer_t *initializer;
86 mode = get_tarval_mode(tv);
88 if (! ia32_cg_config.use_sse2) {
89 /* try to reduce the mode to produce smaller sized entities */
91 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
93 tv = tarval_convert_to(tv, mode);
94 } else if (mode != mode_D) {
95 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
97 tv = tarval_convert_to(tv, mode);
104 name = id_unique("C%u");
106 tp = ia32_get_prim_type(mode);
107 res = new_entity(get_glob_type(), name, tp);
108 set_entity_ld_ident(res, get_entity_ident(res));
109 set_entity_visibility(res, ir_visibility_private);
110 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
112 initializer = create_initializer_tarval(tv);
113 set_entity_initializer(res, initializer);
115 pmap_insert(isa->tv_ent, tv, res);
119 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
121 ir_graph *irg = current_ir_graph;
122 ir_node *start_block = get_irg_start_block(irg);
123 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
124 symconst_sign, ia32_no_pic_adjust, val);
125 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
130 const arch_register_t *ia32_get_clobber_register(const char *clobber)
132 const arch_register_t *reg = NULL;
135 const arch_register_class_t *cls;
137 /* TODO: construct a hashmap instead of doing linear search for clobber
139 for (c = 0; c < N_IA32_CLASSES; ++c) {
140 cls = & ia32_reg_classes[c];
141 for (r = 0; r < cls->n_regs; ++r) {
142 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
143 if (strcmp(temp_reg->name, clobber) == 0
144 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
156 int ia32_mode_needs_gp_reg(ir_mode *mode)
158 if (mode == ia32_mode_fpcw)
160 if (get_mode_size_bits(mode) > 32)
162 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
165 static void parse_asm_constraints(constraint_t *constraint, const char *c,
168 char immediate_type = '\0';
169 unsigned limited = 0;
170 const arch_register_class_t *cls = NULL;
171 int memory_possible = 0;
172 int all_registers_allowed = 0;
176 memset(constraint, 0, sizeof(constraint[0]));
177 constraint->same_as = -1;
180 /* a memory constraint: no need to do anything in backend about it
181 * (the dependencies are already respected by the memory edge of
186 /* TODO: improve error messages with node and source info. (As users can
187 * easily hit these) */
195 /* Skip out/in-out marker */
205 while (*c != 0 && *c != ',')
210 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
211 cls = &ia32_reg_classes[CLASS_ia32_gp];
212 limited |= 1 << REG_GP_EAX;
215 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
216 cls = &ia32_reg_classes[CLASS_ia32_gp];
217 limited |= 1 << REG_GP_EBX;
220 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
221 cls = &ia32_reg_classes[CLASS_ia32_gp];
222 limited |= 1 << REG_GP_ECX;
225 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
226 cls = &ia32_reg_classes[CLASS_ia32_gp];
227 limited |= 1 << REG_GP_EDX;
230 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
231 cls = &ia32_reg_classes[CLASS_ia32_gp];
232 limited |= 1 << REG_GP_EDI;
235 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
236 cls = &ia32_reg_classes[CLASS_ia32_gp];
237 limited |= 1 << REG_GP_ESI;
241 /* q means lower part of the regs only, this makes no
242 * difference to Q for us (we only assign whole registers) */
243 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
244 cls = &ia32_reg_classes[CLASS_ia32_gp];
245 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
249 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
250 cls = &ia32_reg_classes[CLASS_ia32_gp];
251 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
254 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
255 cls = &ia32_reg_classes[CLASS_ia32_gp];
256 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
257 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
264 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
265 panic("multiple register classes not supported");
266 cls = &ia32_reg_classes[CLASS_ia32_gp];
267 all_registers_allowed = 1;
273 /* TODO: mark values so the x87 simulator knows about t and u */
274 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_fp])
275 panic("multiple register classes not supported");
276 cls = &ia32_reg_classes[CLASS_ia32_fp];
277 all_registers_allowed = 1;
282 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
283 panic("multiple register classes not supproted");
284 cls = &ia32_reg_classes[CLASS_ia32_xmm];
285 all_registers_allowed = 1;
295 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
296 panic("multiple register classes not supported");
297 if (immediate_type != '\0')
298 panic("multiple immediate types not supported");
299 cls = &ia32_reg_classes[CLASS_ia32_gp];
304 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
305 panic("multiple register classes not supported");
306 if (immediate_type != '\0')
307 panic("multiple immediate types not supported");
308 cls = &ia32_reg_classes[CLASS_ia32_gp];
309 immediate_type = 'i';
314 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
315 panic("multiple register classes not supported");
316 if (immediate_type != '\0')
317 panic("multiple immediate types not supported");
318 immediate_type = 'i';
319 cls = &ia32_reg_classes[CLASS_ia32_gp];
320 all_registers_allowed = 1;
335 panic("can only specify same constraint on input");
337 sscanf(c, "%d%n", &same_as, &p);
347 /* memory constraint no need to do anything in backend about it
348 * (the dependencies are already respected by the memory edge of
353 case 'E': /* no float consts yet */
354 case 'F': /* no float consts yet */
355 case 's': /* makes no sense on x86 */
356 case '<': /* no autodecrement on x86 */
357 case '>': /* no autoincrement on x86 */
358 case 'C': /* sse constant not supported yet */
359 case 'G': /* 80387 constant not supported yet */
360 case 'y': /* we don't support mmx registers yet */
361 case 'Z': /* not available in 32 bit mode */
362 case 'e': /* not available in 32 bit mode */
363 panic("unsupported asm constraint '%c' found in (%+F)",
364 *c, current_ir_graph);
366 panic("unknown asm constraint '%c' found in (%+F)", *c,
374 panic("same as and register constraint not supported");
375 if (immediate_type != '\0')
376 panic("same as and immediate constraint not supported");
379 if (cls == NULL && same_as < 0) {
380 if (!memory_possible)
381 panic("no constraint specified for assembler input");
384 constraint->same_as = same_as;
385 constraint->cls = cls;
386 constraint->allowed_registers = limited;
387 constraint->all_registers_allowed = all_registers_allowed;
388 constraint->memory_possible = memory_possible;
389 constraint->immediate_type = immediate_type;
392 static bool can_match(const arch_register_req_t *in,
393 const arch_register_req_t *out)
395 if (in->cls != out->cls)
397 if ( (in->type & arch_register_req_type_limited) == 0
398 || (out->type & arch_register_req_type_limited) == 0 )
401 return (*in->limited & *out->limited) != 0;
404 static inline ir_node *get_new_node(ir_node *node)
407 if (be_transformer == TRANSFORMER_DEFAULT) {
408 return be_transform_node(node);
413 return be_transform_node(node);
417 ir_node *ia32_gen_ASM(ir_node *node)
419 ir_node *block = get_nodes_block(node);
420 ir_node *new_block = get_new_node(block);
421 dbg_info *dbgi = get_irn_dbg_info(node);
422 int n_inputs = get_ASM_n_inputs(node);
423 int n_ins = n_inputs+1;
424 ir_node **in = ALLOCANZ(ir_node*, n_ins);
425 size_t n_clobbers = 0;
426 ident **clobbers = get_ASM_clobbers(node);
427 unsigned reg_map_size = 0;
428 ir_graph *irg = get_irn_irg(node);
429 struct obstack *obst = get_irg_obstack(irg);
430 unsigned clobber_bits[N_IA32_CLASSES];
431 memset(&clobber_bits, 0, sizeof(clobber_bits));
433 for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
434 const char *clobber = get_id_str(clobbers[c]);
435 const arch_register_req_t *req = ia32_parse_clobber(clobber);
439 clobber_bits[req->cls->index] |= *req->limited;
440 assert(req->cls->n_regs <= sizeof(unsigned)*8);
443 size_t n_out_constraints = get_ASM_n_output_constraints(node);
444 size_t out_arity = n_out_constraints + n_clobbers;
446 const ir_asm_constraint *in_constraints = get_ASM_input_constraints(node);
447 const ir_asm_constraint *out_constraints = get_ASM_output_constraints(node);
449 /* determine size of register_map */
450 for (size_t out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
451 const ir_asm_constraint *constraint = &out_constraints[out_idx];
452 if (constraint->pos+1 > reg_map_size)
453 reg_map_size = constraint->pos+1;
455 for (int i = 0; i < n_inputs; ++i) {
456 const ir_asm_constraint *constraint = &in_constraints[i];
457 if (constraint->pos+1 > reg_map_size)
458 reg_map_size = constraint->pos+1;
461 ia32_asm_reg_t *register_map
462 = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
463 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
465 /* construct output constraints */
466 size_t out_size = out_arity + 1;
467 const arch_register_req_t **out_reg_reqs
468 = OALLOCN(obst, const arch_register_req_t*, out_size);
471 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
472 constraint_t parsed_constraint;
473 const ir_asm_constraint *constraint = &out_constraints[out_idx];
474 const char *c = get_id_str(constraint->constraint);
475 unsigned pos = constraint->pos;
476 parse_asm_constraints(&parsed_constraint, c, true);
477 const arch_register_req_t *req
478 = ia32_make_register_req(&parsed_constraint, n_out_constraints,
479 out_reg_reqs, out_idx);
480 out_reg_reqs[out_idx] = req;
482 /* multiple constraints for same pos. This can happen for example when
483 * a =A constraint gets lowered to two constraints: =a and =d for the
485 if (register_map[pos].valid)
488 register_map[pos].use_input = 0;
489 register_map[pos].valid = 1;
490 register_map[pos].memory = 0;
491 register_map[pos].inout_pos = out_idx;
492 register_map[pos].mode = constraint->mode;
495 /* inputs + input constraints */
496 const arch_register_req_t **in_reg_reqs
497 = OALLOCN(obst, const arch_register_req_t*, n_ins);
498 for (int i = 0; i < n_inputs; ++i) {
499 constraint_t parsed_constraint;
500 ir_node *pred = get_ASM_input(node, i);
501 const ir_asm_constraint *constraint = &in_constraints[i];
502 ident *constr_id = constraint->constraint;
503 const char *c = get_id_str(constr_id);
504 unsigned pos = constraint->pos;
505 int is_memory_op = 0;
506 ir_node *input = NULL;
508 parse_asm_constraints(&parsed_constraint, c, false);
509 if (parsed_constraint.cls != NULL) {
510 unsigned r_clobber_bits
511 = clobber_bits[parsed_constraint.cls->index];
512 if (r_clobber_bits != 0) {
513 if (parsed_constraint.all_registers_allowed) {
514 parsed_constraint.all_registers_allowed = 0;
515 be_set_allocatable_regs(irg,
516 parsed_constraint.cls,
517 &parsed_constraint.allowed_registers);
519 parsed_constraint.allowed_registers &= ~r_clobber_bits;
523 const arch_register_req_t *req
524 = ia32_make_register_req(&parsed_constraint, n_out_constraints,
526 in_reg_reqs[i] = req;
528 if (parsed_constraint.immediate_type != '\0') {
529 char imm_type = parsed_constraint.immediate_type;
530 input = ia32_try_create_Immediate(pred, imm_type);
534 input = get_new_node(pred);
536 if (parsed_constraint.cls == NULL
537 && parsed_constraint.same_as < 0) {
539 in_reg_reqs[i] = ia32_reg_classes[CLASS_ia32_gp].class_req;
540 } else if (parsed_constraint.memory_possible) {
541 /* TODO: match Load or Load/Store if memory possible is set */
546 register_map[pos].use_input = 1;
547 register_map[pos].valid = 1;
548 register_map[pos].memory = is_memory_op;
549 register_map[pos].inout_pos = i;
550 register_map[pos].mode = constraint->mode;
553 assert(n_inputs == n_ins-1);
554 ir_node *mem = get_ASM_mem(node);
555 in[n_inputs] = be_transform_node(mem);
556 in_reg_reqs[n_inputs] = arch_no_register_req;
559 for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
560 const char *clobber = get_id_str(clobbers[c]);
561 const arch_register_req_t *req = ia32_parse_clobber(clobber);
564 out_reg_reqs[out_idx] = req;
568 /* Attempt to make ASM node register pressure faithful.
569 * (This does not work for complicated cases yet!)
571 * Algorithm: Check if there are fewer inputs or outputs (I will call this
572 * the smaller list). Then try to match each constraint of the smaller list
573 * to 1 of the other list. If we can't match it, then we have to add a dummy
574 * input/output to the other list
576 * FIXME: This is still broken in lots of cases. But at least better than
578 * FIXME: need to do this per register class...
580 if (out_arity <= (size_t)n_inputs) {
581 int orig_inputs = n_ins;
583 bitset_t *used_ins = bitset_alloca(n_ins);
584 for (size_t o = 0; o < out_arity; ++o) {
585 const arch_register_req_t *outreq = out_reg_reqs[o];
587 if (outreq->cls == NULL) {
592 for (i = 0; i < orig_inputs; ++i) {
593 if (bitset_is_set(used_ins, i))
595 const arch_register_req_t *inreq = in_reg_reqs[i];
596 if (!can_match(outreq, inreq))
598 bitset_set(used_ins, i);
601 /* did we find any match? */
605 /* we might need more space in the input arrays */
606 if (n_ins >= in_size) {
608 const arch_register_req_t **new_in_reg_reqs
609 = OALLOCN(obst, const arch_register_req_t*,
611 memcpy(new_in_reg_reqs, in_reg_reqs,
612 n_ins*sizeof(new_in_reg_reqs[0]));
613 ir_node **new_in = ALLOCANZ(ir_node*, in_size);
614 memcpy(new_in, in, n_ins*sizeof(new_in[0]));
616 in_reg_reqs = new_in_reg_reqs;
620 /* add a new (dummy) input which occupies the register */
621 assert(outreq->type & arch_register_req_type_limited);
622 in_reg_reqs[n_ins] = outreq;
623 in[n_ins] = new_bd_ia32_ProduceVal(NULL, block);
627 bitset_t *used_outs = bitset_alloca(out_arity);
628 size_t orig_out_arity = out_arity;
629 for (int i = 0; i < n_inputs; ++i) {
630 const arch_register_req_t *inreq = in_reg_reqs[i];
632 if (inreq->cls == NULL)
636 for (o = 0; o < orig_out_arity; ++o) {
637 const arch_register_req_t *outreq;
638 if (bitset_is_set(used_outs, o))
640 outreq = out_reg_reqs[o];
641 if (!can_match(outreq, inreq))
643 bitset_set(used_outs, i);
646 /* did we find any match? */
647 if (o < orig_out_arity)
650 /* we might need more space in the output arrays */
651 if (out_arity >= out_size) {
652 const arch_register_req_t **new_out_reg_reqs;
656 = OALLOCN(obst, const arch_register_req_t*, out_size);
657 memcpy(new_out_reg_reqs, out_reg_reqs,
658 out_arity * sizeof(new_out_reg_reqs[0]));
659 out_reg_reqs = new_out_reg_reqs;
662 /* add a new (dummy) output which occupies the register */
663 assert(inreq->type & arch_register_req_type_limited);
664 out_reg_reqs[out_arity] = inreq;
669 /* append none register requirement for the memory output */
670 if (out_arity + 1 >= out_size) {
671 const arch_register_req_t **new_out_reg_reqs;
673 out_size = out_arity + 1;
675 = OALLOCN(obst, const arch_register_req_t*, out_size);
676 memcpy(new_out_reg_reqs, out_reg_reqs,
677 out_arity * sizeof(new_out_reg_reqs[0]));
678 out_reg_reqs = new_out_reg_reqs;
681 /* add a new (dummy) output which occupies the register */
682 out_reg_reqs[out_arity] = arch_no_register_req;
685 ir_node *new_node = new_bd_ia32_Asm(dbgi, new_block, n_ins, in, out_arity,
686 get_ASM_text(node), register_map);
688 backend_info_t *info = be_get_info(new_node);
689 for (size_t o = 0; o < out_arity; ++o) {
690 info->out_infos[o].req = out_reg_reqs[o];
692 arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
694 SET_IA32_ORIG_NODE(new_node, node);
699 ir_node *ia32_gen_CopyB(ir_node *node)
701 ir_node *block = get_new_node(get_nodes_block(node));
702 ir_node *src = get_CopyB_src(node);
703 ir_node *new_src = get_new_node(src);
704 ir_node *dst = get_CopyB_dst(node);
705 ir_node *new_dst = get_new_node(dst);
706 ir_node *mem = get_CopyB_mem(node);
707 ir_node *new_mem = get_new_node(mem);
709 dbg_info *dbgi = get_irn_dbg_info(node);
710 int size = get_type_size_bytes(get_CopyB_type(node));
711 int throws_exception = ir_throws_exception(node);
714 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
715 /* then we need the size explicitly in ECX. */
716 if (size >= 32 * 4) {
717 rem = size & 0x3; /* size % 4 */
720 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
722 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
725 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
728 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
730 ir_set_throws_exception(res, throws_exception);
732 SET_IA32_ORIG_NODE(res, node);
737 ir_node *ia32_gen_Proj_tls(ir_node *node)
739 ir_node *block = get_new_node(get_nodes_block(node));
740 ir_node *res = new_bd_ia32_LdTls(NULL, block);
744 ir_node *ia32_gen_Unknown(ir_node *node)
746 ir_mode *mode = get_irn_mode(node);
747 ir_graph *irg = current_ir_graph;
748 dbg_info *dbgi = get_irn_dbg_info(node);
749 ir_node *block = get_irg_start_block(irg);
752 if (mode_is_float(mode)) {
753 if (ia32_cg_config.use_sse2) {
754 res = new_bd_ia32_xUnknown(dbgi, block);
756 res = new_bd_ia32_fldz(dbgi, block);
758 } else if (ia32_mode_needs_gp_reg(mode)) {
759 res = new_bd_ia32_Unknown(dbgi, block);
761 panic("unsupported Unknown-Mode");
767 const arch_register_req_t *ia32_make_register_req(
768 const constraint_t *constraint, int n_outs,
769 const arch_register_req_t **out_reqs, int pos)
771 struct obstack *obst = get_irg_obstack(current_ir_graph);
772 int same_as = constraint->same_as;
773 arch_register_req_t *req;
776 const arch_register_req_t *other_constr;
778 if (same_as >= n_outs)
779 panic("invalid output number in same_as constraint");
781 other_constr = out_reqs[same_as];
783 req = OALLOC(obst, arch_register_req_t);
784 *req = *other_constr;
785 req->type |= arch_register_req_type_should_be_same;
786 req->other_same = 1U << pos;
789 /* switch constraints. This is because in firm we have same_as
790 * constraints on the output constraints while in the gcc asm syntax
791 * they are specified on the input constraints */
792 out_reqs[same_as] = req;
796 /* pure memory ops */
797 if (constraint->cls == NULL) {
798 return arch_no_register_req;
801 if (constraint->allowed_registers != 0
802 && !constraint->all_registers_allowed) {
803 unsigned *limited_ptr;
805 req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
806 memset(req, 0, sizeof(req[0]));
807 limited_ptr = (unsigned*) (req+1);
809 req->type = arch_register_req_type_limited;
810 *limited_ptr = constraint->allowed_registers;
811 req->limited = limited_ptr;
813 req = OALLOCZ(obst, arch_register_req_t);
814 req->type = arch_register_req_type_normal;
816 req->cls = constraint->cls;
822 const arch_register_req_t *ia32_parse_clobber(const char *clobber)
824 if (strcmp(clobber, "memory") == 0 || strcmp(clobber, "cc") == 0)
827 struct obstack *obst = get_irg_obstack(current_ir_graph);
828 const arch_register_t *reg = ia32_get_clobber_register(clobber);
829 arch_register_req_t *req;
833 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
836 assert(reg->index < 32);
838 limited = OALLOC(obst, unsigned);
839 *limited = 1 << reg->index;
841 req = OALLOCZ(obst, arch_register_req_t);
842 req->type = arch_register_req_type_limited;
843 req->cls = reg->reg_class;
844 req->limited = limited;
851 int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
852 ir_node *const other)
854 if (get_nodes_block(other) != block)
857 if (is_Sync(other)) {
860 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
861 ir_node *const pred = get_Sync_pred(other, i);
863 if (get_nodes_block(pred) != block)
866 /* Do not block ourselves from getting eaten */
867 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
870 if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
878 /* Do not block ourselves from getting eaten */
879 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
882 if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
889 ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
892 ir_entity *symconst_ent = NULL;
894 ir_node *cnst = NULL;
895 ir_node *symconst = NULL;
898 mode = get_irn_mode(node);
899 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
903 if (is_Const(node)) {
906 } else if (is_SymConst_addr_ent(node)
907 && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
910 } else if (is_Add(node)) {
911 ir_node *left = get_Add_left(node);
912 ir_node *right = get_Add_right(node);
913 if (is_Const(left) && is_SymConst_addr_ent(right)) {
916 } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
925 ir_tarval *offset = get_Const_tarval(cnst);
926 if (!tarval_is_long(offset)) {
927 ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
931 val = get_tarval_long(offset);
932 if (!check_immediate_constraint(val, immediate_constraint_type))
935 if (symconst != NULL) {
936 if (immediate_constraint_type != 0) {
937 /* we need full 32bits for symconsts */
941 symconst_ent = get_SymConst_entity(symconst);
943 if (cnst == NULL && symconst == NULL)
946 new_node = ia32_create_Immediate(symconst_ent, 0, val);