2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
36 #include "ia32_architecture.h"
37 #include "ia32_common_transform.h"
38 #include "ia32_new_nodes.h"
40 #include "gen_ia32_new_nodes.h"
41 #include "gen_ia32_regalloc_if.h"
43 /** hold the current code generator during transformation */
44 ia32_code_gen_t *env_cg = NULL;
46 static const arch_register_req_t no_register_req = {
47 arch_register_req_type_none,
49 NULL, /* limit bitset */
54 static int check_immediate_constraint(long val, char immediate_constraint_type)
56 switch (immediate_constraint_type) {
61 return val >= 0 && val <= 32;
63 return val >= 0 && val <= 63;
65 return val >= -128 && val <= 127;
67 return val == 0xff || val == 0xffff;
69 return val >= 0 && val <= 3;
71 return val >= 0 && val <= 255;
73 return val >= 0 && val <= 127;
77 panic("Invalid immediate constraint found");
82 * creates a unique ident by adding a number to a tag
84 * @param tag the tag string, must contain a %d if a number
87 static ident *unique_id(const char *tag)
89 static unsigned id = 0;
92 snprintf(str, sizeof(str), tag, ++id);
93 return new_id_from_str(str);
97 * Get a primitive type for a mode.
99 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
101 pmap_entry *e = pmap_find(types, mode);
106 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
107 res = new_type_primitive(new_id_from_str(buf), mode);
108 set_type_alignment_bytes(res, 16);
109 pmap_insert(types, mode, res);
116 ir_entity *create_float_const_entity(ir_node *cnst)
118 ia32_isa_t *isa = env_cg->isa;
119 tarval *key = get_Const_tarval(cnst);
120 pmap_entry *e = pmap_find(isa->tv_ent, key);
126 ir_mode *mode = get_tarval_mode(tv);
129 if (! ia32_cg_config.use_sse2) {
130 /* try to reduce the mode to produce smaller sized entities */
131 if (mode != mode_F) {
132 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
134 tv = tarval_convert_to(tv, mode);
135 } else if (mode != mode_D) {
136 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
138 tv = tarval_convert_to(tv, mode);
144 if (mode == get_irn_mode(cnst)) {
145 /* mode was not changed */
146 tp = get_Const_type(cnst);
147 if (tp == firm_unknown_type)
148 tp = ia32_get_prim_type(isa->types, mode);
150 tp = ia32_get_prim_type(isa->types, mode);
152 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
154 set_entity_ld_ident(res, get_entity_ident(res));
155 set_entity_visibility(res, visibility_local);
156 set_entity_variability(res, variability_constant);
157 set_entity_allocation(res, allocation_static);
159 /* we create a new entity here: It's initialization must resist on the
161 rem = current_ir_graph;
162 current_ir_graph = get_const_code_irg();
163 set_atomic_ent_value(res, new_Const_type(tv, tp));
164 current_ir_graph = rem;
166 pmap_insert(isa->tv_ent, key, res);
174 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
176 ir_graph *irg = current_ir_graph;
177 ir_node *start_block = get_irg_start_block(irg);
178 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
179 symconst, symconst_sign, val);
180 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
185 const arch_register_t *ia32_get_clobber_register(const char *clobber)
187 const arch_register_t *reg = NULL;
190 const arch_register_class_t *cls;
192 /* TODO: construct a hashmap instead of doing linear search for clobber
194 for(c = 0; c < N_CLASSES; ++c) {
195 cls = & ia32_reg_classes[c];
196 for(r = 0; r < cls->n_regs; ++r) {
197 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
198 if(strcmp(temp_reg->name, clobber) == 0
199 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
212 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
213 ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
215 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
216 obstack_1grow(isa->name_obst, 0);
217 return obstack_finish(isa->name_obst);
221 int ia32_mode_needs_gp_reg(ir_mode *mode) {
222 if(mode == mode_fpcw)
224 if(get_mode_size_bits(mode) > 32)
226 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
229 static void parse_asm_constraints(constraint_t *constraint, const char *c,
232 asm_constraint_flags_t flags = 0;
233 char immediate_type = '\0';
234 unsigned limited = 0;
235 const arch_register_class_t *cls = NULL;
236 int memory_possible = 0;
237 int all_registers_allowed = 0;
241 memset(constraint, 0, sizeof(constraint[0]));
242 constraint->same_as = -1;
245 /* a memory constraint: no need to do anything in backend about it
246 * (the dependencies are already respected by the memory edge of
251 /* TODO: improve error messages with node and source info. (As users can
252 * easily hit these) */
261 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
262 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
266 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
267 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
274 while(*c != 0 && *c != ',')
279 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
280 cls = &ia32_reg_classes[CLASS_ia32_gp];
281 limited |= 1 << REG_EAX;
284 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
285 cls = &ia32_reg_classes[CLASS_ia32_gp];
286 limited |= 1 << REG_EBX;
289 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
290 cls = &ia32_reg_classes[CLASS_ia32_gp];
291 limited |= 1 << REG_ECX;
294 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
295 cls = &ia32_reg_classes[CLASS_ia32_gp];
296 limited |= 1 << REG_EDX;
299 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
300 cls = &ia32_reg_classes[CLASS_ia32_gp];
301 limited |= 1 << REG_EDI;
304 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
305 cls = &ia32_reg_classes[CLASS_ia32_gp];
306 limited |= 1 << REG_ESI;
310 /* q means lower part of the regs only, this makes no
311 * difference to Q for us (we only assign whole registers) */
312 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
313 cls = &ia32_reg_classes[CLASS_ia32_gp];
314 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
318 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
319 cls = &ia32_reg_classes[CLASS_ia32_gp];
320 limited |= 1 << REG_EAX | 1 << REG_EDX;
323 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
324 cls = &ia32_reg_classes[CLASS_ia32_gp];
325 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
326 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
333 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
334 panic("multiple register classes not supported");
335 cls = &ia32_reg_classes[CLASS_ia32_gp];
336 all_registers_allowed = 1;
342 /* TODO: mark values so the x87 simulator knows about t and u */
343 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
344 panic("multiple register classes not supported");
345 cls = &ia32_reg_classes[CLASS_ia32_vfp];
346 all_registers_allowed = 1;
351 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
352 panic("multiple register classes not supproted");
353 cls = &ia32_reg_classes[CLASS_ia32_xmm];
354 all_registers_allowed = 1;
364 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
365 panic("multiple register classes not supported");
366 if (immediate_type != '\0')
367 panic("multiple immediate types not supported");
368 cls = &ia32_reg_classes[CLASS_ia32_gp];
373 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
374 panic("multiple register classes not supported");
375 if (immediate_type != '\0')
376 panic("multiple immediate types not supported");
377 cls = &ia32_reg_classes[CLASS_ia32_gp];
378 immediate_type = 'i';
383 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
384 panic("multiple register classes not supported");
385 if (immediate_type != '\0')
386 panic("multiple immediate types not supported");
387 immediate_type = 'i';
388 cls = &ia32_reg_classes[CLASS_ia32_gp];
389 all_registers_allowed = 1;
404 panic("can only specify same constraint on input");
406 sscanf(c, "%d%n", &same_as, &p);
416 /* memory constraint no need to do anything in backend about it
417 * (the dependencies are already respected by the memory edge of
422 case 'E': /* no float consts yet */
423 case 'F': /* no float consts yet */
424 case 's': /* makes no sense on x86 */
425 case '<': /* no autodecrement on x86 */
426 case '>': /* no autoincrement on x86 */
427 case 'C': /* sse constant not supported yet */
428 case 'G': /* 80387 constant not supported yet */
429 case 'y': /* we don't support mmx registers yet */
430 case 'Z': /* not available in 32 bit mode */
431 case 'e': /* not available in 32 bit mode */
432 panic("unsupported asm constraint '%c' found in (%+F)",
433 *c, current_ir_graph);
436 panic("unknown asm constraint '%c' found in (%+F)", *c,
445 panic("same as and register constraint not supported");
446 if (immediate_type != '\0')
447 panic("same as and immediate constraint not supported");
450 if (cls == NULL && same_as < 0) {
451 if (!memory_possible)
452 panic("no constraint specified for assembler input");
455 constraint->same_as = same_as;
456 constraint->cls = cls;
457 constraint->allowed_registers = limited;
458 constraint->all_registers_allowed = all_registers_allowed;
459 constraint->memory_possible = memory_possible;
460 constraint->immediate_type = immediate_type;
463 ir_node *gen_ASM(ir_node *node)
465 ir_graph *irg = current_ir_graph;
466 ir_node *block = get_nodes_block(node);
467 ir_node *new_block = be_transform_node(block);
468 dbg_info *dbgi = get_irn_dbg_info(node);
474 int n_out_constraints;
476 const arch_register_req_t **out_reg_reqs;
477 const arch_register_req_t **in_reg_reqs;
478 ia32_asm_reg_t *register_map;
479 unsigned reg_map_size = 0;
480 struct obstack *obst;
481 const ir_asm_constraint *in_constraints;
482 const ir_asm_constraint *out_constraints;
484 int clobbers_flags = 0;
486 /* workaround for lots of buggy code out there as most people think volatile
487 * asm is enough for everything and forget the flags (linux kernel, etc.)
489 if (get_irn_pinned(node) == op_pin_state_pinned) {
493 arity = get_irn_arity(node);
494 in = alloca(arity * sizeof(in[0]));
495 memset(in, 0, arity * sizeof(in[0]));
497 clobbers = get_ASM_clobbers(node);
499 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
500 const char *c = get_id_str(clobbers[i]);
501 if (strcmp(c, "memory") == 0)
503 if (strcmp(c, "cc") == 0) {
509 n_out_constraints = get_ASM_n_output_constraints(node);
510 out_arity = n_out_constraints + n_clobbers;
512 in_constraints = get_ASM_input_constraints(node);
513 out_constraints = get_ASM_output_constraints(node);
515 /* determine size of register_map */
516 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
517 const ir_asm_constraint *constraint = &out_constraints[out_idx];
518 if (constraint->pos > reg_map_size)
519 reg_map_size = constraint->pos;
521 for(i = 0; i < arity; ++i) {
522 const ir_asm_constraint *constraint = &in_constraints[i];
523 if(constraint->pos > reg_map_size)
524 reg_map_size = constraint->pos;
528 obst = get_irg_obstack(irg);
529 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
530 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
532 /* construct output constraints */
533 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
535 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
536 const ir_asm_constraint *constraint = &out_constraints[out_idx];
537 const char *c = get_id_str(constraint->constraint);
538 unsigned pos = constraint->pos;
539 constraint_t parsed_constraint;
540 const arch_register_req_t *req;
542 parse_asm_constraints(&parsed_constraint, c, 1);
543 req = make_register_req(&parsed_constraint, n_out_constraints,
544 out_reg_reqs, out_idx);
545 out_reg_reqs[out_idx] = req;
547 register_map[pos].use_input = 0;
548 register_map[pos].valid = 1;
549 register_map[pos].memory = 0;
550 register_map[pos].inout_pos = out_idx;
551 register_map[pos].mode = constraint->mode;
554 /* inputs + input constraints */
555 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
556 for(i = 0; i < arity; ++i) {
557 ir_node *pred = get_irn_n(node, i);
558 const ir_asm_constraint *constraint = &in_constraints[i];
559 ident *constr_id = constraint->constraint;
560 const char *c = get_id_str(constr_id);
561 unsigned pos = constraint->pos;
562 int is_memory_op = 0;
563 ir_node *input = NULL;
564 constraint_t parsed_constraint;
565 const arch_register_req_t *req;
567 parse_asm_constraints(&parsed_constraint, c, 0);
568 req = make_register_req(&parsed_constraint, n_out_constraints,
570 in_reg_reqs[i] = req;
572 if (parsed_constraint.immediate_type != '\0') {
573 char imm_type = parsed_constraint.immediate_type;
574 input = try_create_Immediate(pred, imm_type);
578 ir_node *pred = get_irn_n(node, i);
579 input = be_transform_node(pred);
581 if (parsed_constraint.cls == NULL
582 && parsed_constraint.same_as < 0) {
584 } else if(parsed_constraint.memory_possible) {
585 /* TODO: match Load or Load/Store if memory possible is set */
590 register_map[pos].use_input = 1;
591 register_map[pos].valid = 1;
592 register_map[pos].memory = is_memory_op;
593 register_map[pos].inout_pos = i;
594 register_map[pos].mode = constraint->mode;
598 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
599 const char *c = get_id_str(clobbers[i]);
600 const arch_register_req_t *req;
602 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
605 req = parse_clobber(c);
606 out_reg_reqs[out_idx] = req;
610 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
611 get_ASM_text(node), register_map);
613 set_ia32_out_req_all(new_node, out_reg_reqs);
614 set_ia32_in_req_all(new_node, in_reg_reqs);
616 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
621 ir_node *gen_Unknown(ir_node *node)
623 ir_mode *mode = get_irn_mode(node);
625 if (mode_is_float(mode)) {
626 if (ia32_cg_config.use_sse2) {
627 return ia32_new_Unknown_xmm(env_cg);
629 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
630 ir_graph *irg = current_ir_graph;
631 dbg_info *dbgi = get_irn_dbg_info(node);
632 ir_node *block = get_irg_start_block(irg);
633 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
635 /* Const Nodes before the initial IncSP are a bad idea, because
636 * they could be spilled and we have no SP ready at that point yet.
637 * So add a dependency to the initial frame pointer calculation to
638 * avoid that situation.
640 add_irn_dep(ret, get_irg_frame(irg));
643 } else if (ia32_mode_needs_gp_reg(mode)) {
644 return ia32_new_Unknown_gp(env_cg);
646 panic("unsupported Unknown-Mode");
651 const arch_register_req_t *make_register_req(const constraint_t *constraint,
652 int n_outs, const arch_register_req_t **out_reqs, int pos)
654 struct obstack *obst = get_irg_obstack(current_ir_graph);
655 int same_as = constraint->same_as;
656 arch_register_req_t *req;
659 const arch_register_req_t *other_constr;
661 if (same_as >= n_outs)
662 panic("invalid output number in same_as constraint");
664 other_constr = out_reqs[same_as];
666 req = obstack_alloc(obst, sizeof(req[0]));
667 req->cls = other_constr->cls;
668 req->type = arch_register_req_type_should_be_same;
670 req->other_same = 1U << pos;
671 req->other_different = 0;
673 /* switch constraints. This is because in firm we have same_as
674 * constraints on the output constraints while in the gcc asm syntax
675 * they are specified on the input constraints */
676 out_reqs[same_as] = req;
680 /* pure memory ops */
681 if (constraint->cls == NULL) {
682 return &no_register_req;
685 if (constraint->allowed_registers != 0
686 && !constraint->all_registers_allowed) {
687 unsigned *limited_ptr;
689 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
690 memset(req, 0, sizeof(req[0]));
691 limited_ptr = (unsigned*) (req+1);
693 req->type = arch_register_req_type_limited;
694 *limited_ptr = constraint->allowed_registers;
695 req->limited = limited_ptr;
697 req = obstack_alloc(obst, sizeof(req[0]));
698 memset(req, 0, sizeof(req[0]));
699 req->type = arch_register_req_type_normal;
701 req->cls = constraint->cls;
706 const arch_register_req_t *parse_clobber(const char *clobber)
708 struct obstack *obst = get_irg_obstack(current_ir_graph);
709 const arch_register_t *reg = ia32_get_clobber_register(clobber);
710 arch_register_req_t *req;
714 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
717 assert(reg->index < 32);
719 limited = obstack_alloc(obst, sizeof(limited[0]));
720 *limited = 1 << reg->index;
722 req = obstack_alloc(obst, sizeof(req[0]));
723 memset(req, 0, sizeof(req[0]));
724 req->type = arch_register_req_type_limited;
725 req->cls = arch_register_get_class(reg);
726 req->limited = limited;
731 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
734 tarval *offset = NULL;
737 ir_entity *symconst_ent = NULL;
738 int symconst_sign = 0;
740 ir_node *cnst = NULL;
741 ir_node *symconst = NULL;
744 mode = get_irn_mode(node);
745 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
751 node = get_Minus_op(node);
758 } else if(is_SymConst(node)) {
761 symconst_sign = minus;
762 } else if(is_Add(node)) {
763 ir_node *left = get_Add_left(node);
764 ir_node *right = get_Add_right(node);
765 if(is_Const(left) && is_SymConst(right)) {
768 symconst_sign = minus;
770 } else if(is_SymConst(left) && is_Const(right)) {
773 symconst_sign = minus;
776 } else if(is_Sub(node)) {
777 ir_node *left = get_Sub_left(node);
778 ir_node *right = get_Sub_right(node);
779 if(is_Const(left) && is_SymConst(right)) {
782 symconst_sign = !minus;
784 } else if(is_SymConst(left) && is_Const(right)) {
787 symconst_sign = minus;
788 offset_sign = !minus;
795 offset = get_Const_tarval(cnst);
796 if(tarval_is_long(offset)) {
797 val = get_tarval_long(offset);
799 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
804 if(!check_immediate_constraint(val, immediate_constraint_type))
807 if(symconst != NULL) {
808 if(immediate_constraint_type != 0) {
809 /* we need full 32bits for symconsts */
813 /* unfortunately the assembler/linker doesn't support -symconst */
817 if(get_SymConst_kind(symconst) != symconst_addr_ent)
819 symconst_ent = get_SymConst_entity(symconst);
821 if(cnst == NULL && symconst == NULL)
824 if(offset_sign && offset != NULL) {
825 offset = tarval_neg(offset);
828 new_node = create_Immediate(symconst_ent, symconst_sign, val);