2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
35 #include "betranshlp.h"
38 #include "ia32_architecture.h"
39 #include "ia32_common_transform.h"
40 #include "ia32_new_nodes.h"
42 #include "gen_ia32_new_nodes.h"
43 #include "gen_ia32_regalloc_if.h"
45 ir_heights_t *ia32_heights = NULL;
47 static int check_immediate_constraint(long val, char immediate_constraint_type)
49 switch (immediate_constraint_type) {
52 case 'I': return 0 <= val && val <= 31;
53 case 'J': return 0 <= val && val <= 63;
54 case 'K': return -128 <= val && val <= 127;
55 case 'L': return val == 0xff || val == 0xffff;
56 case 'M': return 0 <= val && val <= 3;
57 case 'N': return 0 <= val && val <= 255;
58 case 'O': return 0 <= val && val <= 127;
60 default: panic("Invalid immediate constraint found");
64 ir_type *ia32_get_prim_type(const ir_mode *mode)
66 if (mode == ia32_mode_E) {
69 return get_type_for_mode(mode);
73 ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
76 ir_entity *res = pmap_get(ir_entity, isa->tv_ent, tv);
77 ir_initializer_t *initializer;
84 mode = get_tarval_mode(tv);
86 if (! ia32_cg_config.use_sse2) {
87 /* try to reduce the mode to produce smaller sized entities */
89 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
91 tv = tarval_convert_to(tv, mode);
92 } else if (mode != mode_D) {
93 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
95 tv = tarval_convert_to(tv, mode);
102 name = id_unique("C%u");
104 tp = ia32_get_prim_type(mode);
105 res = new_entity(get_glob_type(), name, tp);
106 set_entity_ld_ident(res, get_entity_ident(res));
107 set_entity_visibility(res, ir_visibility_private);
108 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
110 initializer = create_initializer_tarval(tv);
111 set_entity_initializer(res, initializer);
113 pmap_insert(isa->tv_ent, tv, res);
117 ir_node *ia32_create_Immediate(ir_graph *const irg, ir_entity *const symconst, int const symconst_sign, long const val)
119 ir_node *start_block = get_irg_start_block(irg);
120 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
121 symconst_sign, ia32_no_pic_adjust, val);
122 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
127 const arch_register_t *ia32_get_clobber_register(const char *clobber)
129 const arch_register_t *reg = NULL;
132 const arch_register_class_t *cls;
134 /* TODO: construct a hashmap instead of doing linear search for clobber
136 for (c = 0; c < N_IA32_CLASSES; ++c) {
137 cls = & ia32_reg_classes[c];
138 for (r = 0; r < cls->n_regs; ++r) {
139 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
140 if (strcmp(temp_reg->name, clobber) == 0
141 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
153 int ia32_mode_needs_gp_reg(ir_mode *mode)
155 if (mode == ia32_mode_fpcw)
157 if (get_mode_size_bits(mode) > 32)
159 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
162 static void parse_asm_constraints(constraint_t *constraint, const char *c,
165 char immediate_type = '\0';
166 unsigned limited = 0;
167 const arch_register_class_t *cls = NULL;
168 int memory_possible = 0;
169 int all_registers_allowed = 0;
173 memset(constraint, 0, sizeof(constraint[0]));
174 constraint->same_as = -1;
177 /* a memory constraint: no need to do anything in backend about it
178 * (the dependencies are already respected by the memory edge of
183 /* TODO: improve error messages with node and source info. (As users can
184 * easily hit these) */
192 /* Skip out/in-out marker */
202 while (*c != 0 && *c != ',')
207 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
208 cls = &ia32_reg_classes[CLASS_ia32_gp];
209 limited |= 1 << REG_GP_EAX;
212 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
213 cls = &ia32_reg_classes[CLASS_ia32_gp];
214 limited |= 1 << REG_GP_EBX;
217 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
218 cls = &ia32_reg_classes[CLASS_ia32_gp];
219 limited |= 1 << REG_GP_ECX;
222 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
223 cls = &ia32_reg_classes[CLASS_ia32_gp];
224 limited |= 1 << REG_GP_EDX;
227 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
228 cls = &ia32_reg_classes[CLASS_ia32_gp];
229 limited |= 1 << REG_GP_EDI;
232 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
233 cls = &ia32_reg_classes[CLASS_ia32_gp];
234 limited |= 1 << REG_GP_ESI;
238 /* q means lower part of the regs only, this makes no
239 * difference to Q for us (we only assign whole registers) */
240 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
241 cls = &ia32_reg_classes[CLASS_ia32_gp];
242 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
246 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
247 cls = &ia32_reg_classes[CLASS_ia32_gp];
248 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
251 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
252 cls = &ia32_reg_classes[CLASS_ia32_gp];
253 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
254 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
261 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
262 panic("multiple register classes not supported");
263 cls = &ia32_reg_classes[CLASS_ia32_gp];
264 all_registers_allowed = 1;
270 /* TODO: mark values so the x87 simulator knows about t and u */
271 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_fp])
272 panic("multiple register classes not supported");
273 cls = &ia32_reg_classes[CLASS_ia32_fp];
274 all_registers_allowed = 1;
279 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
280 panic("multiple register classes not supproted");
281 cls = &ia32_reg_classes[CLASS_ia32_xmm];
282 all_registers_allowed = 1;
292 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
293 panic("multiple register classes not supported");
294 if (immediate_type != '\0')
295 panic("multiple immediate types not supported");
296 cls = &ia32_reg_classes[CLASS_ia32_gp];
301 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
302 panic("multiple register classes not supported");
303 if (immediate_type != '\0')
304 panic("multiple immediate types not supported");
305 cls = &ia32_reg_classes[CLASS_ia32_gp];
306 immediate_type = 'i';
311 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
312 panic("multiple register classes not supported");
313 if (immediate_type != '\0')
314 panic("multiple immediate types not supported");
315 immediate_type = 'i';
316 cls = &ia32_reg_classes[CLASS_ia32_gp];
317 all_registers_allowed = 1;
332 panic("can only specify same constraint on input");
334 sscanf(c, "%d%n", &same_as, &p);
344 /* memory constraint no need to do anything in backend about it
345 * (the dependencies are already respected by the memory edge of
350 case 'E': /* no float consts yet */
351 case 'F': /* no float consts yet */
352 case 's': /* makes no sense on x86 */
353 case '<': /* no autodecrement on x86 */
354 case '>': /* no autoincrement on x86 */
355 case 'C': /* sse constant not supported yet */
356 case 'G': /* 80387 constant not supported yet */
357 case 'y': /* we don't support mmx registers yet */
358 case 'Z': /* not available in 32 bit mode */
359 case 'e': /* not available in 32 bit mode */
360 panic("unsupported asm constraint '%c' found in (%+F)",
361 *c, current_ir_graph);
363 panic("unknown asm constraint '%c' found in (%+F)", *c,
371 panic("same as and register constraint not supported");
372 if (immediate_type != '\0')
373 panic("same as and immediate constraint not supported");
376 if (cls == NULL && same_as < 0) {
377 if (!memory_possible)
378 panic("no constraint specified for assembler input");
381 constraint->same_as = same_as;
382 constraint->cls = cls;
383 constraint->allowed_registers = limited;
384 constraint->all_registers_allowed = all_registers_allowed;
385 constraint->memory_possible = memory_possible;
386 constraint->immediate_type = immediate_type;
389 static bool can_match(const arch_register_req_t *in,
390 const arch_register_req_t *out)
392 if (in->cls != out->cls)
394 if (!arch_register_req_is(in, limited) ||
395 !arch_register_req_is(out, limited))
398 return (*in->limited & *out->limited) != 0;
401 static inline ir_node *get_new_node(ir_node *node)
404 if (be_transformer == TRANSFORMER_DEFAULT) {
405 return be_transform_node(node);
410 return be_transform_node(node);
414 static arch_register_req_t const *ia32_make_register_req(ir_graph *irg, constraint_t const *constraint, int n_outs, arch_register_req_t const **out_reqs, int pos);
416 ir_node *ia32_gen_ASM(ir_node *node)
418 ir_node *block = get_nodes_block(node);
419 ir_node *new_block = get_new_node(block);
420 dbg_info *dbgi = get_irn_dbg_info(node);
421 int n_inputs = get_ASM_n_inputs(node);
422 int n_ins = n_inputs+1;
423 ir_node **in = ALLOCANZ(ir_node*, n_ins);
424 size_t n_clobbers = 0;
425 ident **clobbers = get_ASM_clobbers(node);
426 unsigned reg_map_size = 0;
427 ir_graph *irg = get_irn_irg(node);
428 struct obstack *obst = get_irg_obstack(irg);
429 unsigned clobber_bits[N_IA32_CLASSES];
430 memset(&clobber_bits, 0, sizeof(clobber_bits));
432 for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
433 const char *clobber = get_id_str(clobbers[c]);
434 const arch_register_req_t *req = ia32_parse_clobber(clobber);
438 clobber_bits[req->cls->index] |= *req->limited;
439 assert(req->cls->n_regs <= sizeof(unsigned)*8);
442 size_t n_out_constraints = get_ASM_n_output_constraints(node);
443 size_t out_arity = n_out_constraints + n_clobbers;
445 const ir_asm_constraint *in_constraints = get_ASM_input_constraints(node);
446 const ir_asm_constraint *out_constraints = get_ASM_output_constraints(node);
448 /* determine size of register_map */
449 for (size_t out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
450 const ir_asm_constraint *constraint = &out_constraints[out_idx];
451 if (constraint->pos+1 > reg_map_size)
452 reg_map_size = constraint->pos+1;
454 for (int i = 0; i < n_inputs; ++i) {
455 const ir_asm_constraint *constraint = &in_constraints[i];
456 if (constraint->pos+1 > reg_map_size)
457 reg_map_size = constraint->pos+1;
460 ia32_asm_reg_t *register_map
461 = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
462 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
464 /* construct output constraints */
465 size_t out_size = out_arity + 1;
466 const arch_register_req_t **out_reg_reqs
467 = OALLOCN(obst, const arch_register_req_t*, out_size);
470 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
471 constraint_t parsed_constraint;
472 const ir_asm_constraint *constraint = &out_constraints[out_idx];
473 const char *c = get_id_str(constraint->constraint);
474 unsigned pos = constraint->pos;
475 parse_asm_constraints(&parsed_constraint, c, true);
476 arch_register_req_t const *const req = ia32_make_register_req(irg, &parsed_constraint, n_out_constraints, out_reg_reqs, out_idx);
477 out_reg_reqs[out_idx] = req;
479 /* multiple constraints for same pos. This can happen for example when
480 * a =A constraint gets lowered to two constraints: =a and =d for the
482 if (register_map[pos].valid)
485 register_map[pos].use_input = 0;
486 register_map[pos].valid = 1;
487 register_map[pos].memory = 0;
488 register_map[pos].inout_pos = out_idx;
489 register_map[pos].mode = constraint->mode;
492 /* inputs + input constraints */
493 const arch_register_req_t **in_reg_reqs
494 = OALLOCN(obst, const arch_register_req_t*, n_ins);
495 for (int i = 0; i < n_inputs; ++i) {
496 constraint_t parsed_constraint;
497 ir_node *pred = get_ASM_input(node, i);
498 const ir_asm_constraint *constraint = &in_constraints[i];
499 ident *constr_id = constraint->constraint;
500 const char *c = get_id_str(constr_id);
501 unsigned pos = constraint->pos;
502 int is_memory_op = 0;
503 ir_node *input = NULL;
505 parse_asm_constraints(&parsed_constraint, c, false);
506 if (parsed_constraint.cls != NULL) {
507 unsigned r_clobber_bits
508 = clobber_bits[parsed_constraint.cls->index];
509 if (r_clobber_bits != 0) {
510 if (parsed_constraint.all_registers_allowed) {
511 parsed_constraint.all_registers_allowed = 0;
512 be_set_allocatable_regs(irg,
513 parsed_constraint.cls,
514 &parsed_constraint.allowed_registers);
516 parsed_constraint.allowed_registers &= ~r_clobber_bits;
520 arch_register_req_t const *const req = ia32_make_register_req(irg, &parsed_constraint, n_out_constraints, out_reg_reqs, i);
521 in_reg_reqs[i] = req;
523 if (parsed_constraint.immediate_type != '\0') {
524 char imm_type = parsed_constraint.immediate_type;
525 input = ia32_try_create_Immediate(pred, imm_type);
529 input = get_new_node(pred);
531 if (parsed_constraint.cls == NULL
532 && parsed_constraint.same_as < 0) {
534 in_reg_reqs[i] = ia32_reg_classes[CLASS_ia32_gp].class_req;
535 } else if (parsed_constraint.memory_possible) {
536 /* TODO: match Load or Load/Store if memory possible is set */
541 register_map[pos].use_input = 1;
542 register_map[pos].valid = 1;
543 register_map[pos].memory = is_memory_op;
544 register_map[pos].inout_pos = i;
545 register_map[pos].mode = constraint->mode;
548 assert(n_inputs == n_ins-1);
549 ir_node *mem = get_ASM_mem(node);
550 in[n_inputs] = be_transform_node(mem);
551 in_reg_reqs[n_inputs] = arch_no_register_req;
554 for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
555 const char *clobber = get_id_str(clobbers[c]);
556 const arch_register_req_t *req = ia32_parse_clobber(clobber);
559 out_reg_reqs[out_idx] = req;
563 /* Attempt to make ASM node register pressure faithful.
564 * (This does not work for complicated cases yet!)
566 * Algorithm: Check if there are fewer inputs or outputs (I will call this
567 * the smaller list). Then try to match each constraint of the smaller list
568 * to 1 of the other list. If we can't match it, then we have to add a dummy
569 * input/output to the other list
571 * FIXME: This is still broken in lots of cases. But at least better than
573 * FIXME: need to do this per register class...
575 if (out_arity <= (size_t)n_inputs) {
576 int orig_inputs = n_ins;
578 bitset_t *used_ins = bitset_alloca(n_ins);
579 for (size_t o = 0; o < out_arity; ++o) {
580 const arch_register_req_t *outreq = out_reg_reqs[o];
582 if (outreq->cls == NULL) {
587 for (i = 0; i < orig_inputs; ++i) {
588 if (bitset_is_set(used_ins, i))
590 const arch_register_req_t *inreq = in_reg_reqs[i];
591 if (!can_match(outreq, inreq))
593 bitset_set(used_ins, i);
596 /* did we find any match? */
600 /* we might need more space in the input arrays */
601 if (n_ins >= in_size) {
603 const arch_register_req_t **new_in_reg_reqs
604 = OALLOCN(obst, const arch_register_req_t*,
606 memcpy(new_in_reg_reqs, in_reg_reqs,
607 n_ins*sizeof(new_in_reg_reqs[0]));
608 ir_node **new_in = ALLOCANZ(ir_node*, in_size);
609 memcpy(new_in, in, n_ins*sizeof(new_in[0]));
611 in_reg_reqs = new_in_reg_reqs;
615 /* add a new (dummy) input which occupies the register */
616 assert(arch_register_req_is(outreq, limited));
617 in_reg_reqs[n_ins] = outreq;
618 in[n_ins] = new_bd_ia32_ProduceVal(NULL, block);
622 bitset_t *used_outs = bitset_alloca(out_arity);
623 size_t orig_out_arity = out_arity;
624 for (int i = 0; i < n_inputs; ++i) {
625 const arch_register_req_t *inreq = in_reg_reqs[i];
627 if (inreq->cls == NULL)
631 for (o = 0; o < orig_out_arity; ++o) {
632 const arch_register_req_t *outreq;
633 if (bitset_is_set(used_outs, o))
635 outreq = out_reg_reqs[o];
636 if (!can_match(outreq, inreq))
638 bitset_set(used_outs, i);
641 /* did we find any match? */
642 if (o < orig_out_arity)
645 /* we might need more space in the output arrays */
646 if (out_arity >= out_size) {
647 const arch_register_req_t **new_out_reg_reqs;
651 = OALLOCN(obst, const arch_register_req_t*, out_size);
652 memcpy(new_out_reg_reqs, out_reg_reqs,
653 out_arity * sizeof(new_out_reg_reqs[0]));
654 out_reg_reqs = new_out_reg_reqs;
657 /* add a new (dummy) output which occupies the register */
658 assert(arch_register_req_is(inreq, limited));
659 out_reg_reqs[out_arity] = inreq;
664 /* append none register requirement for the memory output */
665 if (out_arity + 1 >= out_size) {
666 const arch_register_req_t **new_out_reg_reqs;
668 out_size = out_arity + 1;
670 = OALLOCN(obst, const arch_register_req_t*, out_size);
671 memcpy(new_out_reg_reqs, out_reg_reqs,
672 out_arity * sizeof(new_out_reg_reqs[0]));
673 out_reg_reqs = new_out_reg_reqs;
676 /* add a new (dummy) output which occupies the register */
677 out_reg_reqs[out_arity] = arch_no_register_req;
680 ir_node *new_node = new_bd_ia32_Asm(dbgi, new_block, n_ins, in, out_arity,
681 get_ASM_text(node), register_map);
683 backend_info_t *info = be_get_info(new_node);
684 for (size_t o = 0; o < out_arity; ++o) {
685 info->out_infos[o].req = out_reg_reqs[o];
687 arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
689 SET_IA32_ORIG_NODE(new_node, node);
694 ir_node *ia32_gen_CopyB(ir_node *node)
696 ir_node *block = get_new_node(get_nodes_block(node));
697 ir_node *src = get_CopyB_src(node);
698 ir_node *new_src = get_new_node(src);
699 ir_node *dst = get_CopyB_dst(node);
700 ir_node *new_dst = get_new_node(dst);
701 ir_node *mem = get_CopyB_mem(node);
702 ir_node *new_mem = get_new_node(mem);
704 dbg_info *dbgi = get_irn_dbg_info(node);
705 int size = get_type_size_bytes(get_CopyB_type(node));
706 int throws_exception = ir_throws_exception(node);
709 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
710 /* then we need the size explicitly in ECX. */
711 if (size >= 32 * 4) {
712 rem = size & 0x3; /* size % 4 */
715 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
717 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
720 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
723 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
725 ir_set_throws_exception(res, throws_exception);
727 SET_IA32_ORIG_NODE(res, node);
732 ir_node *ia32_gen_Proj_tls(ir_node *node)
734 ir_node *block = get_new_node(get_nodes_block(node));
735 ir_node *res = new_bd_ia32_LdTls(NULL, block);
739 ir_node *ia32_gen_Unknown(ir_node *node)
741 ir_mode *mode = get_irn_mode(node);
742 ir_graph *irg = current_ir_graph;
743 dbg_info *dbgi = get_irn_dbg_info(node);
744 ir_node *block = get_irg_start_block(irg);
747 if (mode_is_float(mode)) {
748 if (ia32_cg_config.use_sse2) {
749 res = new_bd_ia32_xUnknown(dbgi, block);
751 res = new_bd_ia32_fldz(dbgi, block);
753 } else if (ia32_mode_needs_gp_reg(mode)) {
754 res = new_bd_ia32_Unknown(dbgi, block);
756 panic("unsupported Unknown-Mode");
762 static arch_register_req_t const *ia32_make_register_req(ir_graph *const irg, constraint_t const *const c, int const n_outs, arch_register_req_t const **const out_reqs, int const pos)
764 int const same_as = c->same_as;
766 if (same_as >= n_outs)
767 panic("invalid output number in same_as constraint");
769 struct obstack *const obst = get_irg_obstack(irg);
770 arch_register_req_t *const req = OALLOC(obst, arch_register_req_t);
771 arch_register_req_t const *const other = out_reqs[same_as];
773 req->type |= arch_register_req_type_should_be_same;
774 req->other_same = 1U << pos;
776 /* Switch constraints. This is because in firm we have same_as
777 * constraints on the output constraints while in the gcc asm syntax
778 * they are specified on the input constraints. */
779 out_reqs[same_as] = req;
783 /* Pure memory ops. */
785 return arch_no_register_req;
787 if (c->allowed_registers == 0 || c->all_registers_allowed)
788 return c->cls->class_req;
790 struct obstack *const obst = get_irg_obstack(irg);
791 arch_register_req_t *const req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
792 unsigned *const limited = (unsigned*)(req + 1);
793 *limited = c->allowed_registers;
795 memset(req, 0, sizeof(req[0]));
796 req->type = arch_register_req_type_limited;
798 req->limited = limited;
803 const arch_register_req_t *ia32_parse_clobber(const char *clobber)
805 if (strcmp(clobber, "memory") == 0 || strcmp(clobber, "cc") == 0)
808 arch_register_t const *const reg = ia32_get_clobber_register(clobber);
810 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
812 return reg->single_req;
816 int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
817 ir_node *const other)
819 if (get_nodes_block(other) != block)
822 if (is_Sync(other)) {
825 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
826 ir_node *const pred = get_Sync_pred(other, i);
828 if (get_nodes_block(pred) != block)
831 /* Do not block ourselves from getting eaten */
832 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
835 if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
843 /* Do not block ourselves from getting eaten */
844 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
847 if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
854 ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
856 ir_mode *const mode = get_irn_mode(node);
857 if (!mode_is_int(mode) && !mode_is_reference(mode))
862 if (is_Const(node)) {
865 } else if (is_SymConst_addr_ent(node)
866 && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
869 } else if (is_Add(node)) {
870 ir_node *left = get_Add_left(node);
871 ir_node *right = get_Add_right(node);
872 if (is_Const(left) && is_SymConst_addr_ent(right)) {
875 } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
887 ir_tarval *offset = get_Const_tarval(cnst);
888 if (!tarval_is_long(offset)) {
889 ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
893 val = get_tarval_long(offset);
894 if (!check_immediate_constraint(val, immediate_constraint_type))
898 ir_entity *symconst_ent = NULL;
899 if (symconst != NULL) {
900 /* we need full 32bits for symconsts */
901 if (immediate_constraint_type != 'i')
904 symconst_ent = get_SymConst_entity(symconst);
907 ir_graph *const irg = get_irn_irg(node);
908 return ia32_create_Immediate(irg, symconst_ent, 0, val);