nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27
  28 #include "error.h"
  29 #include "irargs_t.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33
  34 #include "../betranshlp.h"
  35 #include "../beirg_t.h"
  36
  37 #include "ia32_architecture.h"
  38 #include "ia32_common_transform.h"
  39 #include "ia32_new_nodes.h"
  40
  41 #include "gen_ia32_new_nodes.h"
  42 #include "gen_ia32_regalloc_if.h"
  43
  44 /** hold the current code generator during transformation */
  45 ia32_code_gen_t *env_cg = NULL;
  46
  47 heights_t *heights = NULL;
  48
  49 static const arch_register_req_t no_register_req = {
  50         arch_register_req_type_none,
  51         NULL,                         /* regclass */
  52         NULL,                         /* limit bitset */
  53         0,                            /* same pos */
  54         0                             /* different pos */
  55 };
  56
  57 static int check_immediate_constraint(long val, char immediate_constraint_type)
  58 {
  59         switch (immediate_constraint_type) {
  60                 case 0:
  61                 case 'i': return 1;
  62
  63                 case 'I': return    0 <= val && val <=  31;
  64                 case 'J': return    0 <= val && val <=  63;
  65                 case 'K': return -128 <= val && val <= 127;
  66                 case 'L': return val == 0xff || val == 0xffff;
  67                 case 'M': return    0 <= val && val <=   3;
  68                 case 'N': return    0 <= val && val <= 255;
  69                 case 'O': return    0 <= val && val <= 127;
  70
  71                 default: panic("Invalid immediate constraint found");
  72         }
  73 }
  74
  75 /**
  76  * creates a unique ident by adding a number to a tag
  77  *
  78  * @param tag   the tag string, must contain a %d if a number
  79  *              should be added
  80  */
  81 static ident *unique_id(const char *tag)
  82 {
  83         static unsigned id = 0;
  84         char str[256];
  85
  86         snprintf(str, sizeof(str), tag, ++id);
  87         return new_id_from_str(str);
  88 }
  89
  90 /**
  91  * Get a primitive type for a mode.
  92  */
  93 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  94 {
  95         pmap_entry *e = pmap_find(types, mode);
  96         ir_type *res;
  97
  98         if (! e) {
  99                 char buf[64];
 100                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
 101                 res = new_type_primitive(new_id_from_str(buf), mode);
 102                 set_type_alignment_bytes(res, 16);
 103                 pmap_insert(types, mode, res);
 104         }
 105         else
 106                 res = e->value;
 107         return res;
 108 }
 109
 110 ir_entity *create_float_const_entity(ir_node *cnst)
 111 {
 112         ia32_isa_t *isa = env_cg->isa;
 113         tarval *key     = get_Const_tarval(cnst);
 114         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 115         ir_entity *res;
 116         ir_graph *rem;
 117
 118         if (e == NULL) {
 119                 tarval  *tv   = key;
 120                 ir_mode *mode = get_tarval_mode(tv);
 121                 ir_type *tp;
 122
 123                 if (! ia32_cg_config.use_sse2) {
 124                         /* try to reduce the mode to produce smaller sized entities */
 125                         if (mode != mode_F) {
 126                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 127                                         mode = mode_F;
 128                                         tv = tarval_convert_to(tv, mode);
 129                                 } else if (mode != mode_D) {
 130                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 131                                                 mode = mode_D;
 132                                                 tv = tarval_convert_to(tv, mode);
 133                                         }
 134                                 }
 135                         }
 136                 }
 137
 138                 if (mode == get_irn_mode(cnst)) {
 139                         /* mode was not changed */
 140                         tp = get_Const_type(cnst);
 141                         if (tp == firm_unknown_type)
 142                                 tp = ia32_get_prim_type(isa->types, mode);
 143                 } else
 144                         tp = ia32_get_prim_type(isa->types, mode);
 145
 146                 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
 147
 148                 set_entity_ld_ident(res, get_entity_ident(res));
 149                 set_entity_visibility(res, visibility_local);
 150                 set_entity_variability(res, variability_constant);
 151                 set_entity_allocation(res, allocation_static);
 152
 153                  /* we create a new entity here: It's initialization must resist on the
 154                     const code irg */
 155                 rem = current_ir_graph;
 156                 current_ir_graph = get_const_code_irg();
 157                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 158                 current_ir_graph = rem;
 159
 160                 pmap_insert(isa->tv_ent, key, res);
 161         } else {
 162                 res = e->value;
 163         }
 164
 165         return res;
 166 }
 167
 168 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 169 {
 170         ir_graph *irg         = current_ir_graph;
 171         ir_node  *start_block = get_irg_start_block(irg);
 172         ir_node  *immediate   = new_rd_ia32_Immediate(NULL, irg, start_block,
 173                                                       symconst, symconst_sign, val);
 174         arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
 175
 176         return immediate;
 177 }
 178
 179 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 180 {
 181         const arch_register_t       *reg = NULL;
 182         int                          c;
 183         size_t                       r;
 184         const arch_register_class_t *cls;
 185
 186         /* TODO: construct a hashmap instead of doing linear search for clobber
 187          * register */
 188         for(c = 0; c < N_CLASSES; ++c) {
 189                 cls = & ia32_reg_classes[c];
 190                 for(r = 0; r < cls->n_regs; ++r) {
 191                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 192                         if(strcmp(temp_reg->name, clobber) == 0
 193                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 194                                 reg = temp_reg;
 195                                 break;
 196                         }
 197                 }
 198                 if(reg != NULL)
 199                         break;
 200         }
 201
 202         return reg;
 203 }
 204
 205 #ifndef NDEBUG
 206 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
 207         ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
 208
 209         lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
 210         obstack_1grow(isa->name_obst, 0);
 211         return obstack_finish(isa->name_obst);
 212 }
 213 #endif /* NDEBUG */
 214
 215 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 216         if(mode == mode_fpcw)
 217                 return 0;
 218         if(get_mode_size_bits(mode) > 32)
 219                 return 0;
 220         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 221 }
 222
 223 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 224                            int is_output)
 225 {
 226         asm_constraint_flags_t       flags              = 0;
 227         char                         immediate_type     = '\0';
 228         unsigned                     limited            = 0;
 229         const arch_register_class_t *cls                = NULL;
 230         int                          memory_possible       = 0;
 231         int                          all_registers_allowed = 0;
 232         int                          p;
 233         int                          same_as = -1;
 234
 235         memset(constraint, 0, sizeof(constraint[0]));
 236         constraint->same_as = -1;
 237
 238         if(*c == 0) {
 239                 /* a memory constraint: no need to do anything in backend about it
 240                  * (the dependencies are already respected by the memory edge of
 241                  * the node) */
 242                 return;
 243         }
 244
 245         /* TODO: improve error messages with node and source info. (As users can
 246          * easily hit these) */
 247         while(*c != 0) {
 248                 switch(*c) {
 249                 case ' ':
 250                 case '\t':
 251                 case '\n':
 252                         break;
 253
 254                 case '=':
 255                         flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
 256                                 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
 257                         break;
 258
 259                 case '+':
 260                         flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
 261                                 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
 262                         break;
 263
 264                 case '*':
 265                         ++c;
 266                         break;
 267                 case '#':
 268                         while(*c != 0 && *c != ',')
 269                                 ++c;
 270                         break;
 271
 272                 case 'a':
 273                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 274                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 275                         limited |= 1 << REG_EAX;
 276                         break;
 277                 case 'b':
 278                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 279                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 280                         limited |= 1 << REG_EBX;
 281                         break;
 282                 case 'c':
 283                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 284                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 285                         limited |= 1 << REG_ECX;
 286                         break;
 287                 case 'd':
 288                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 289                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 290                         limited |= 1 << REG_EDX;
 291                         break;
 292                 case 'D':
 293                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 294                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 295                         limited |= 1 << REG_EDI;
 296                         break;
 297                 case 'S':
 298                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 299                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 300                         limited |= 1 << REG_ESI;
 301                         break;
 302                 case 'Q':
 303                 case 'q':
 304                         /* q means lower part of the regs only, this makes no
 305                          * difference to Q for us (we only assign whole registers) */
 306                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 307                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 308                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 309                                    1 << REG_EDX;
 310                         break;
 311                 case 'A':
 312                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 313                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 314                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 315                         break;
 316                 case 'l':
 317                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 318                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 319                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 320                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 321                                    1 << REG_EBP;
 322                         break;
 323
 324                 case 'R':
 325                 case 'r':
 326                 case 'p':
 327                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 328                                 panic("multiple register classes not supported");
 329                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 330                         all_registers_allowed = 1;
 331                         break;
 332
 333                 case 'f':
 334                 case 't':
 335                 case 'u':
 336                         /* TODO: mark values so the x87 simulator knows about t and u */
 337                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 338                                 panic("multiple register classes not supported");
 339                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 340                         all_registers_allowed = 1;
 341                         break;
 342
 343                 case 'Y':
 344                 case 'x':
 345                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 346                                 panic("multiple register classes not supproted");
 347                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 348                         all_registers_allowed = 1;
 349                         break;
 350
 351                 case 'I':
 352                 case 'J':
 353                 case 'K':
 354                 case 'L':
 355                 case 'M':
 356                 case 'N':
 357                 case 'O':
 358                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 359                                 panic("multiple register classes not supported");
 360                         if (immediate_type != '\0')
 361                                 panic("multiple immediate types not supported");
 362                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 363                         immediate_type = *c;
 364                         break;
 365                 case 'n':
 366                 case 'i':
 367                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 368                                 panic("multiple register classes not supported");
 369                         if (immediate_type != '\0')
 370                                 panic("multiple immediate types not supported");
 371                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 372                         immediate_type = 'i';
 373                         break;
 374
 375                 case 'X':
 376                 case 'g':
 377                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 378                                 panic("multiple register classes not supported");
 379                         if (immediate_type != '\0')
 380                                 panic("multiple immediate types not supported");
 381                         immediate_type        = 'i';
 382                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 383                         all_registers_allowed = 1;
 384                         memory_possible       = 1;
 385                         break;
 386
 387                 case '0':
 388                 case '1':
 389                 case '2':
 390                 case '3':
 391                 case '4':
 392                 case '5':
 393                 case '6':
 394                 case '7':
 395                 case '8':
 396                 case '9':
 397                         if (is_output)
 398                                 panic("can only specify same constraint on input");
 399
 400                         sscanf(c, "%d%n", &same_as, &p);
 401                         if(same_as >= 0) {
 402                                 c += p;
 403                                 continue;
 404                         }
 405                         break;
 406
 407                 case 'm':
 408                 case 'o':
 409                 case 'V':
 410                         /* memory constraint no need to do anything in backend about it
 411                          * (the dependencies are already respected by the memory edge of
 412                          * the node) */
 413                         memory_possible = 1;
 414                         break;
 415
 416                 case 'E': /* no float consts yet */
 417                 case 'F': /* no float consts yet */
 418                 case 's': /* makes no sense on x86 */
 419                 case '<': /* no autodecrement on x86 */
 420                 case '>': /* no autoincrement on x86 */
 421                 case 'C': /* sse constant not supported yet */
 422                 case 'G': /* 80387 constant not supported yet */
 423                 case 'y': /* we don't support mmx registers yet */
 424                 case 'Z': /* not available in 32 bit mode */
 425                 case 'e': /* not available in 32 bit mode */
 426                         panic("unsupported asm constraint '%c' found in (%+F)",
 427                               *c, current_ir_graph);
 428                         break;
 429                 default:
 430                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 431                               current_ir_graph);
 432                         break;
 433                 }
 434                 ++c;
 435         }
 436
 437         if(same_as >= 0) {
 438                 if (cls != NULL)
 439                         panic("same as and register constraint not supported");
 440                 if (immediate_type != '\0')
 441                         panic("same as and immediate constraint not supported");
 442         }
 443
 444         if (cls == NULL && same_as < 0) {
 445                 if (!memory_possible)
 446                         panic("no constraint specified for assembler input");
 447         }
 448
 449         constraint->same_as               = same_as;
 450         constraint->cls                   = cls;
 451         constraint->allowed_registers     = limited;
 452         constraint->all_registers_allowed = all_registers_allowed;
 453         constraint->memory_possible       = memory_possible;
 454         constraint->immediate_type        = immediate_type;
 455 }
 456
 457 ir_node *gen_ASM(ir_node *node)
 458 {
 459         ir_graph                   *irg       = current_ir_graph;
 460 #ifdef FIRM_GRGEN_BE
 461         ir_node                    *new_block = get_nodes_block(node);
 462 #else
 463         ir_node                    *block     = get_nodes_block(node);
 464         ir_node                    *new_block = be_transform_node(block);
 465 #endif
 466         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 467         int                         i, arity;
 468         int                         out_idx;
 469         ir_node                   **in;
 470         ir_node                    *new_node;
 471         int                         out_arity;
 472         int                         n_out_constraints;
 473         int                         n_clobbers;
 474         const arch_register_req_t **out_reg_reqs;
 475         const arch_register_req_t **in_reg_reqs;
 476         ia32_asm_reg_t             *register_map;
 477         unsigned                    reg_map_size = 0;
 478         struct obstack             *obst;
 479         const ir_asm_constraint    *in_constraints;
 480         const ir_asm_constraint    *out_constraints;
 481         ident                     **clobbers;
 482         int                         clobbers_flags = 0;
 483         unsigned                    clobber_bits[N_CLASSES];
 484
 485         memset(&clobber_bits, 0, sizeof(clobber_bits));
 486
 487         /* workaround for lots of buggy code out there as most people think volatile
 488          * asm is enough for everything and forget the flags (linux kernel, etc.)
 489          */
 490         if (get_irn_pinned(node) == op_pin_state_pinned) {
 491                 clobbers_flags = 1;
 492         }
 493
 494         arity = get_irn_arity(node);
 495         in    = alloca(arity * sizeof(in[0]));
 496         memset(in, 0, arity * sizeof(in[0]));
 497
 498         clobbers   = get_ASM_clobbers(node);
 499         n_clobbers = 0;
 500         for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
 501                 const arch_register_req_t *req;
 502                 const char                *c = get_id_str(clobbers[i]);
 503
 504                 if (strcmp(c, "memory") == 0)
 505                         continue;
 506                 if (strcmp(c, "cc") == 0) {
 507                         clobbers_flags = 1;
 508                         continue;
 509                 }
 510
 511                 req = parse_clobber(c);
 512                 clobber_bits[req->cls->index] |= *req->limited;
 513
 514                 n_clobbers++;
 515         }
 516         n_out_constraints = get_ASM_n_output_constraints(node);
 517         out_arity         = n_out_constraints + n_clobbers;
 518
 519         in_constraints  = get_ASM_input_constraints(node);
 520         out_constraints = get_ASM_output_constraints(node);
 521
 522         /* determine size of register_map */
 523         for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 524                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 525                 if (constraint->pos > reg_map_size)
 526                         reg_map_size = constraint->pos;
 527         }
 528         for(i = 0; i < arity; ++i) {
 529                 const ir_asm_constraint   *constraint = &in_constraints[i];
 530                 if(constraint->pos > reg_map_size)
 531                         reg_map_size = constraint->pos;
 532         }
 533         ++reg_map_size;
 534
 535         obst         = get_irg_obstack(irg);
 536         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 537         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 538
 539         /* construct output constraints */
 540         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 541
 542         for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 543                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 544                 const char                *c       = get_id_str(constraint->constraint);
 545                 unsigned                   pos        = constraint->pos;
 546                 constraint_t               parsed_constraint;
 547                 const arch_register_req_t *req;
 548
 549                 parse_asm_constraints(&parsed_constraint, c, 1);
 550                 req = make_register_req(&parsed_constraint, n_out_constraints,
 551                                         out_reg_reqs, out_idx);
 552                 out_reg_reqs[out_idx] = req;
 553
 554                 register_map[pos].use_input = 0;
 555                 register_map[pos].valid     = 1;
 556                 register_map[pos].memory    = 0;
 557                 register_map[pos].inout_pos = out_idx;
 558                 register_map[pos].mode      = constraint->mode;
 559         }
 560
 561         /* inputs + input constraints */
 562         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 563         for(i = 0; i < arity; ++i) {
 564                 ir_node                   *pred         = get_irn_n(node, i);
 565                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 566                 ident                     *constr_id    = constraint->constraint;
 567                 const char                *c            = get_id_str(constr_id);
 568                 unsigned                   pos          = constraint->pos;
 569                 int                        is_memory_op = 0;
 570                 ir_node                   *input        = NULL;
 571                 unsigned                   r_clobber_bits;
 572                 constraint_t               parsed_constraint;
 573                 const arch_register_req_t *req;
 574
 575                 parse_asm_constraints(&parsed_constraint, c, 0);
 576                 if (parsed_constraint.cls != NULL) {
 577                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 578                         if (r_clobber_bits != 0) {
 579                                 if (parsed_constraint.all_registers_allowed) {
 580                                         parsed_constraint.all_registers_allowed = 0;
 581                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 582                                                         parsed_constraint.cls,
 583                                                         &parsed_constraint.allowed_registers);
 584                                 }
 585                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 586                         }
 587                 }
 588
 589                 req = make_register_req(&parsed_constraint, n_out_constraints,
 590                                         out_reg_reqs, i);
 591                 in_reg_reqs[i] = req;
 592
 593                 if (parsed_constraint.immediate_type != '\0') {
 594                         char imm_type = parsed_constraint.immediate_type;
 595                         input = try_create_Immediate(pred, imm_type);
 596                 }
 597
 598                 if (input == NULL) {
 599                         ir_node *pred = get_irn_n(node, i);
 600                         input         = be_transform_node(pred);
 601
 602                         if (parsed_constraint.cls == NULL
 603                                         && parsed_constraint.same_as < 0) {
 604                                 is_memory_op = 1;
 605                         } else if(parsed_constraint.memory_possible) {
 606                                 /* TODO: match Load or Load/Store if memory possible is set */
 607                         }
 608                 }
 609                 in[i] = input;
 610
 611                 register_map[pos].use_input = 1;
 612                 register_map[pos].valid     = 1;
 613                 register_map[pos].memory    = is_memory_op;
 614                 register_map[pos].inout_pos = i;
 615                 register_map[pos].mode      = constraint->mode;
 616         }
 617
 618         /* parse clobbers */
 619         for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
 620                 const char                *c = get_id_str(clobbers[i]);
 621                 const arch_register_req_t *req;
 622
 623                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 624                         continue;
 625
 626                 req = parse_clobber(c);
 627                 out_reg_reqs[out_idx] = req;
 628                 ++out_idx;
 629         }
 630
 631         new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
 632                                    get_ASM_text(node), register_map);
 633
 634         set_ia32_out_req_all(new_node, out_reg_reqs);
 635         set_ia32_in_req_all(new_node, in_reg_reqs);
 636
 637         SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
 638
 639         return new_node;
 640 }
 641
 642 ir_node *gen_Unknown(ir_node *node)
 643 {
 644         ir_mode *mode = get_irn_mode(node);
 645
 646         if (mode_is_float(mode)) {
 647                 if (ia32_cg_config.use_sse2) {
 648                         return ia32_new_Unknown_xmm(env_cg);
 649                 } else {
 650                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 651                         ir_graph *irg   = current_ir_graph;
 652                         dbg_info *dbgi  = get_irn_dbg_info(node);
 653                         ir_node  *block = get_irg_start_block(irg);
 654                         ir_node  *ret   = new_rd_ia32_vfldz(dbgi, irg, block);
 655
 656                         /* Const Nodes before the initial IncSP are a bad idea, because
 657                          * they could be spilled and we have no SP ready at that point yet.
 658                          * So add a dependency to the initial frame pointer calculation to
 659                          * avoid that situation.
 660                          */
 661                         add_irn_dep(ret, get_irg_frame(irg));
 662                         return ret;
 663                 }
 664         } else if (ia32_mode_needs_gp_reg(mode)) {
 665                 return ia32_new_Unknown_gp(env_cg);
 666         } else {
 667                 panic("unsupported Unknown-Mode");
 668         }
 669         return NULL;
 670 }
 671
 672 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 673                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 674 {
 675         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 676         int                  same_as = constraint->same_as;
 677         arch_register_req_t *req;
 678
 679         if (same_as >= 0) {
 680                 const arch_register_req_t *other_constr;
 681
 682                 if (same_as >= n_outs)
 683                         panic("invalid output number in same_as constraint");
 684
 685                 other_constr         = out_reqs[same_as];
 686
 687                 req                  = obstack_alloc(obst, sizeof(req[0]));
 688                 req->cls             = other_constr->cls;
 689                 req->type            = arch_register_req_type_should_be_same;
 690                 req->limited         = NULL;
 691                 req->other_same      = 1U << pos;
 692                 req->other_different = 0;
 693
 694                 /* switch constraints. This is because in firm we have same_as
 695                  * constraints on the output constraints while in the gcc asm syntax
 696                  * they are specified on the input constraints */
 697                 out_reqs[same_as] = req;
 698                 return other_constr;
 699         }
 700
 701         /* pure memory ops */
 702         if (constraint->cls == NULL) {
 703                 return &no_register_req;
 704         }
 705
 706         if (constraint->allowed_registers != 0
 707                         && !constraint->all_registers_allowed) {
 708                 unsigned *limited_ptr;
 709
 710                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 711                 memset(req, 0, sizeof(req[0]));
 712                 limited_ptr = (unsigned*) (req+1);
 713
 714                 req->type    = arch_register_req_type_limited;
 715                 *limited_ptr = constraint->allowed_registers;
 716                 req->limited = limited_ptr;
 717         } else {
 718                 req       = obstack_alloc(obst, sizeof(req[0]));
 719                 memset(req, 0, sizeof(req[0]));
 720                 req->type = arch_register_req_type_normal;
 721         }
 722         req->cls = constraint->cls;
 723
 724         return req;
 725 }
 726
 727 const arch_register_req_t *parse_clobber(const char *clobber)
 728 {
 729         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 730         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 731         arch_register_req_t   *req;
 732         unsigned              *limited;
 733
 734         if(reg == NULL) {
 735                 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
 736         }
 737
 738         assert(reg->index < 32);
 739
 740         limited  = obstack_alloc(obst, sizeof(limited[0]));
 741         *limited = 1 << reg->index;
 742
 743         req          = obstack_alloc(obst, sizeof(req[0]));
 744         memset(req, 0, sizeof(req[0]));
 745         req->type    = arch_register_req_type_limited;
 746         req->cls     = arch_register_get_class(reg);
 747         req->limited = limited;
 748
 749         return req;
 750 }
 751
 752 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
 753 {
 754         int          minus         = 0;
 755         tarval      *offset        = NULL;
 756         int          offset_sign   = 0;
 757         long         val = 0;
 758         ir_entity   *symconst_ent  = NULL;
 759         int          symconst_sign = 0;
 760         ir_mode     *mode;
 761         ir_node     *cnst          = NULL;
 762         ir_node     *symconst      = NULL;
 763         ir_node     *new_node;
 764
 765         mode = get_irn_mode(node);
 766         if(!mode_is_int(mode) && !mode_is_reference(mode)) {
 767                 return NULL;
 768         }
 769
 770         if(is_Minus(node)) {
 771                 minus = 1;
 772                 node  = get_Minus_op(node);
 773         }
 774
 775         if(is_Const(node)) {
 776                 cnst        = node;
 777                 symconst    = NULL;
 778                 offset_sign = minus;
 779         } else if(is_SymConst(node)) {
 780                 cnst          = NULL;
 781                 symconst      = node;
 782                 symconst_sign = minus;
 783         } else if(is_Add(node)) {
 784                 ir_node *left  = get_Add_left(node);
 785                 ir_node *right = get_Add_right(node);
 786                 if(is_Const(left) && is_SymConst(right)) {
 787                         cnst          = left;
 788                         symconst      = right;
 789                         symconst_sign = minus;
 790                         offset_sign   = minus;
 791                 } else if(is_SymConst(left) && is_Const(right)) {
 792                         cnst          = right;
 793                         symconst      = left;
 794                         symconst_sign = minus;
 795                         offset_sign   = minus;
 796                 }
 797         } else if(is_Sub(node)) {
 798                 ir_node *left  = get_Sub_left(node);
 799                 ir_node *right = get_Sub_right(node);
 800                 if(is_Const(left) && is_SymConst(right)) {
 801                         cnst          = left;
 802                         symconst      = right;
 803                         symconst_sign = !minus;
 804                         offset_sign   = minus;
 805                 } else if(is_SymConst(left) && is_Const(right)) {
 806                         cnst          = right;
 807                         symconst      = left;
 808                         symconst_sign = minus;
 809                         offset_sign   = !minus;
 810                 }
 811         } else {
 812                 return NULL;
 813         }
 814
 815         if(cnst != NULL) {
 816                 offset = get_Const_tarval(cnst);
 817                 if(tarval_is_long(offset)) {
 818                         val = get_tarval_long(offset);
 819                 } else {
 820                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
 821                                    "long?\n", cnst);
 822                         return NULL;
 823                 }
 824
 825                 if(!check_immediate_constraint(val, immediate_constraint_type))
 826                         return NULL;
 827         }
 828         if(symconst != NULL) {
 829                 if(immediate_constraint_type != 0) {
 830                         /* we need full 32bits for symconsts */
 831                         return NULL;
 832                 }
 833
 834                 /* unfortunately the assembler/linker doesn't support -symconst */
 835                 if(symconst_sign)
 836                         return NULL;
 837
 838                 if(get_SymConst_kind(symconst) != symconst_addr_ent)
 839                         return NULL;
 840                 symconst_ent = get_SymConst_entity(symconst);
 841         }
 842         if(cnst == NULL && symconst == NULL)
 843                 return NULL;
 844
 845         if(offset_sign && offset != NULL) {
 846                 offset = tarval_neg(offset);
 847         }
 848
 849         new_node = create_Immediate(symconst_ent, symconst_sign, val);
 850
 851         return new_node;
 852 }