nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33
  34 #include "../betranshlp.h"
  35 #include "../beirg_t.h"
  36
  37 #include "ia32_architecture.h"
  38 #include "ia32_common_transform.h"
  39 #include "ia32_new_nodes.h"
  40
  41 #include "gen_ia32_new_nodes.h"
  42 #include "gen_ia32_regalloc_if.h"
  43
  44 /** hold the current code generator during transformation */
  45 ia32_code_gen_t *env_cg = NULL;
  46
  47 heights_t *heights = NULL;
  48
  49 static const arch_register_req_t no_register_req = {
  50         arch_register_req_type_none,
  51         NULL,                         /* regclass */
  52         NULL,                         /* limit bitset */
  53         0,                            /* same pos */
  54         0                             /* different pos */
  55 };
  56
  57 static int check_immediate_constraint(long val, char immediate_constraint_type)
  58 {
  59         switch (immediate_constraint_type) {
  60                 case 0:
  61                 case 'i': return 1;
  62
  63                 case 'I': return    0 <= val && val <=  31;
  64                 case 'J': return    0 <= val && val <=  63;
  65                 case 'K': return -128 <= val && val <= 127;
  66                 case 'L': return val == 0xff || val == 0xffff;
  67                 case 'M': return    0 <= val && val <=   3;
  68                 case 'N': return    0 <= val && val <= 255;
  69                 case 'O': return    0 <= val && val <= 127;
  70
  71                 default: panic("Invalid immediate constraint found");
  72         }
  73 }
  74
  75 /**
  76  * creates a unique ident by adding a number to a tag
  77  *
  78  * @param tag   the tag string, must contain a %d if a number
  79  *              should be added
  80  */
  81 static ident *unique_id(const char *tag)
  82 {
  83         static unsigned id = 0;
  84         char str[256];
  85
  86         snprintf(str, sizeof(str), tag, ++id);
  87         return new_id_from_str(str);
  88 }
  89
  90 /**
  91  * Get a primitive type for a mode.
  92  */
  93 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  94 {
  95         pmap_entry *e = pmap_find(types, mode);
  96         ir_type *res;
  97
  98         if (! e) {
  99                 char buf[64];
 100                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
 101                 res = new_type_primitive(new_id_from_str(buf), mode);
 102                 set_type_alignment_bytes(res, 16);
 103                 pmap_insert(types, mode, res);
 104         }
 105         else
 106                 res = e->value;
 107         return res;
 108 }
 109
 110 ir_entity *create_float_const_entity(ir_node *cnst)
 111 {
 112         ia32_isa_t *isa = env_cg->isa;
 113         tarval *key     = get_Const_tarval(cnst);
 114         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 115         ir_entity *res;
 116         ir_graph *rem;
 117
 118         if (e == NULL) {
 119                 tarval  *tv   = key;
 120                 ir_mode *mode = get_tarval_mode(tv);
 121                 ir_type *tp;
 122
 123                 if (! ia32_cg_config.use_sse2) {
 124                         /* try to reduce the mode to produce smaller sized entities */
 125                         if (mode != mode_F) {
 126                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 127                                         mode = mode_F;
 128                                         tv = tarval_convert_to(tv, mode);
 129                                 } else if (mode != mode_D) {
 130                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 131                                                 mode = mode_D;
 132                                                 tv = tarval_convert_to(tv, mode);
 133                                         }
 134                                 }
 135                         }
 136                 }
 137
 138                 if (mode == get_irn_mode(cnst)) {
 139                         /* mode was not changed */
 140                         tp = get_Const_type(cnst);
 141                         if (tp == firm_unknown_type)
 142                                 tp = ia32_get_prim_type(isa->types, mode);
 143                 } else
 144                         tp = ia32_get_prim_type(isa->types, mode);
 145
 146                 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
 147
 148                 set_entity_ld_ident(res, get_entity_ident(res));
 149                 set_entity_visibility(res, visibility_local);
 150                 set_entity_variability(res, variability_constant);
 151                 set_entity_allocation(res, allocation_static);
 152
 153                  /* we create a new entity here: It's initialization must resist on the
 154                     const code irg */
 155                 rem = current_ir_graph;
 156                 current_ir_graph = get_const_code_irg();
 157                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 158                 current_ir_graph = rem;
 159
 160                 pmap_insert(isa->tv_ent, key, res);
 161         } else {
 162                 res = e->value;
 163         }
 164
 165         return res;
 166 }
 167
 168 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 169 {
 170         ir_graph *irg         = current_ir_graph;
 171         ir_node  *start_block = get_irg_start_block(irg);
 172         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 173                         symconst_sign, val);
 174         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 175
 176         return immediate;
 177 }
 178
 179 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 180 {
 181         const arch_register_t       *reg = NULL;
 182         int                          c;
 183         size_t                       r;
 184         const arch_register_class_t *cls;
 185
 186         /* TODO: construct a hashmap instead of doing linear search for clobber
 187          * register */
 188         for(c = 0; c < N_CLASSES; ++c) {
 189                 cls = & ia32_reg_classes[c];
 190                 for(r = 0; r < cls->n_regs; ++r) {
 191                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 192                         if(strcmp(temp_reg->name, clobber) == 0
 193                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 194                                 reg = temp_reg;
 195                                 break;
 196                         }
 197                 }
 198                 if(reg != NULL)
 199                         break;
 200         }
 201
 202         return reg;
 203 }
 204
 205 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 206         if(mode == mode_fpcw)
 207                 return 0;
 208         if(get_mode_size_bits(mode) > 32)
 209                 return 0;
 210         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 211 }
 212
 213 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 214                            int is_output)
 215 {
 216         char                         immediate_type     = '\0';
 217         unsigned                     limited            = 0;
 218         const arch_register_class_t *cls                = NULL;
 219         int                          memory_possible       = 0;
 220         int                          all_registers_allowed = 0;
 221         int                          p;
 222         int                          same_as = -1;
 223
 224         memset(constraint, 0, sizeof(constraint[0]));
 225         constraint->same_as = -1;
 226
 227         if(*c == 0) {
 228                 /* a memory constraint: no need to do anything in backend about it
 229                  * (the dependencies are already respected by the memory edge of
 230                  * the node) */
 231                 return;
 232         }
 233
 234         /* TODO: improve error messages with node and source info. (As users can
 235          * easily hit these) */
 236         while(*c != 0) {
 237                 switch(*c) {
 238                 case ' ':
 239                 case '\t':
 240                 case '\n':
 241                         break;
 242
 243                 /* Skip out/in-out marker */
 244                 case '=': break;
 245                 case '+': break;
 246
 247                 case '*':
 248                         ++c;
 249                         break;
 250                 case '#':
 251                         while(*c != 0 && *c != ',')
 252                                 ++c;
 253                         break;
 254
 255                 case 'a':
 256                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 257                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 258                         limited |= 1 << REG_EAX;
 259                         break;
 260                 case 'b':
 261                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 262                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 263                         limited |= 1 << REG_EBX;
 264                         break;
 265                 case 'c':
 266                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 267                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 268                         limited |= 1 << REG_ECX;
 269                         break;
 270                 case 'd':
 271                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 272                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 273                         limited |= 1 << REG_EDX;
 274                         break;
 275                 case 'D':
 276                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 277                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 278                         limited |= 1 << REG_EDI;
 279                         break;
 280                 case 'S':
 281                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 282                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 283                         limited |= 1 << REG_ESI;
 284                         break;
 285                 case 'Q':
 286                 case 'q':
 287                         /* q means lower part of the regs only, this makes no
 288                          * difference to Q for us (we only assign whole registers) */
 289                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 290                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 291                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 292                                    1 << REG_EDX;
 293                         break;
 294                 case 'A':
 295                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 296                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 297                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 298                         break;
 299                 case 'l':
 300                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 301                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 302                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 303                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 304                                    1 << REG_EBP;
 305                         break;
 306
 307                 case 'R':
 308                 case 'r':
 309                 case 'p':
 310                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 311                                 panic("multiple register classes not supported");
 312                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 313                         all_registers_allowed = 1;
 314                         break;
 315
 316                 case 'f':
 317                 case 't':
 318                 case 'u':
 319                         /* TODO: mark values so the x87 simulator knows about t and u */
 320                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 321                                 panic("multiple register classes not supported");
 322                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 323                         all_registers_allowed = 1;
 324                         break;
 325
 326                 case 'Y':
 327                 case 'x':
 328                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 329                                 panic("multiple register classes not supproted");
 330                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 331                         all_registers_allowed = 1;
 332                         break;
 333
 334                 case 'I':
 335                 case 'J':
 336                 case 'K':
 337                 case 'L':
 338                 case 'M':
 339                 case 'N':
 340                 case 'O':
 341                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 342                                 panic("multiple register classes not supported");
 343                         if (immediate_type != '\0')
 344                                 panic("multiple immediate types not supported");
 345                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 346                         immediate_type = *c;
 347                         break;
 348                 case 'n':
 349                 case 'i':
 350                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 351                                 panic("multiple register classes not supported");
 352                         if (immediate_type != '\0')
 353                                 panic("multiple immediate types not supported");
 354                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 355                         immediate_type = 'i';
 356                         break;
 357
 358                 case 'X':
 359                 case 'g':
 360                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 361                                 panic("multiple register classes not supported");
 362                         if (immediate_type != '\0')
 363                                 panic("multiple immediate types not supported");
 364                         immediate_type        = 'i';
 365                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 366                         all_registers_allowed = 1;
 367                         memory_possible       = 1;
 368                         break;
 369
 370                 case '0':
 371                 case '1':
 372                 case '2':
 373                 case '3':
 374                 case '4':
 375                 case '5':
 376                 case '6':
 377                 case '7':
 378                 case '8':
 379                 case '9':
 380                         if (is_output)
 381                                 panic("can only specify same constraint on input");
 382
 383                         sscanf(c, "%d%n", &same_as, &p);
 384                         if(same_as >= 0) {
 385                                 c += p;
 386                                 continue;
 387                         }
 388                         break;
 389
 390                 case 'm':
 391                 case 'o':
 392                 case 'V':
 393                         /* memory constraint no need to do anything in backend about it
 394                          * (the dependencies are already respected by the memory edge of
 395                          * the node) */
 396                         memory_possible = 1;
 397                         break;
 398
 399                 case 'E': /* no float consts yet */
 400                 case 'F': /* no float consts yet */
 401                 case 's': /* makes no sense on x86 */
 402                 case '<': /* no autodecrement on x86 */
 403                 case '>': /* no autoincrement on x86 */
 404                 case 'C': /* sse constant not supported yet */
 405                 case 'G': /* 80387 constant not supported yet */
 406                 case 'y': /* we don't support mmx registers yet */
 407                 case 'Z': /* not available in 32 bit mode */
 408                 case 'e': /* not available in 32 bit mode */
 409                         panic("unsupported asm constraint '%c' found in (%+F)",
 410                               *c, current_ir_graph);
 411                         break;
 412                 default:
 413                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 414                               current_ir_graph);
 415                         break;
 416                 }
 417                 ++c;
 418         }
 419
 420         if(same_as >= 0) {
 421                 if (cls != NULL)
 422                         panic("same as and register constraint not supported");
 423                 if (immediate_type != '\0')
 424                         panic("same as and immediate constraint not supported");
 425         }
 426
 427         if (cls == NULL && same_as < 0) {
 428                 if (!memory_possible)
 429                         panic("no constraint specified for assembler input");
 430         }
 431
 432         constraint->same_as               = same_as;
 433         constraint->cls                   = cls;
 434         constraint->allowed_registers     = limited;
 435         constraint->all_registers_allowed = all_registers_allowed;
 436         constraint->memory_possible       = memory_possible;
 437         constraint->immediate_type        = immediate_type;
 438 }
 439
 440 ir_node *gen_ASM(ir_node *node)
 441 {
 442         ir_node                    *block = NULL;
 443         ir_node                    *new_block = NULL;
 444         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 445         int                         i, arity;
 446         int                         out_idx;
 447         ir_node                   **in;
 448         ir_node                    *new_node;
 449         int                         out_arity;
 450         int                         n_out_constraints;
 451         int                         n_clobbers;
 452         const arch_register_req_t **out_reg_reqs;
 453         const arch_register_req_t **in_reg_reqs;
 454         ia32_asm_reg_t             *register_map;
 455         unsigned                    reg_map_size = 0;
 456         struct obstack             *obst;
 457         const ir_asm_constraint    *in_constraints;
 458         const ir_asm_constraint    *out_constraints;
 459         ident                     **clobbers;
 460         int                         clobbers_flags = 0;
 461         unsigned                    clobber_bits[N_CLASSES];
 462
 463         memset(&clobber_bits, 0, sizeof(clobber_bits));
 464
 465         switch (be_transformer) {
 466         case TRANSFORMER_DEFAULT:
 467                 block     = get_nodes_block(node);
 468                 new_block = be_transform_node(block);
 469                 break;
 470
 471 #ifdef FIRM_GRGEN_BE
 472         case TRANSFORMER_PBQP:
 473         case TRANSFORMER_RAND:
 474                 new_block = get_nodes_block(node);
 475                 break;
 476 #endif
 477
 478         default:
 479                 panic("invalid transformer");
 480         }
 481
 482         /* workaround for lots of buggy code out there as most people think volatile
 483          * asm is enough for everything and forget the flags (linux kernel, etc.)
 484          */
 485         if (get_irn_pinned(node) == op_pin_state_pinned) {
 486                 clobbers_flags = 1;
 487         }
 488
 489         arity = get_irn_arity(node);
 490         in    = ALLOCANZ(ir_node*, arity);
 491
 492         clobbers   = get_ASM_clobbers(node);
 493         n_clobbers = 0;
 494         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 495                 const arch_register_req_t *req;
 496                 const char                *c = get_id_str(clobbers[i]);
 497
 498                 if (strcmp(c, "memory") == 0)
 499                         continue;
 500                 if (strcmp(c, "cc") == 0) {
 501                         clobbers_flags = 1;
 502                         continue;
 503                 }
 504
 505                 req = parse_clobber(c);
 506                 clobber_bits[req->cls->index] |= *req->limited;
 507
 508                 n_clobbers++;
 509         }
 510         n_out_constraints = get_ASM_n_output_constraints(node);
 511         out_arity         = n_out_constraints + n_clobbers;
 512
 513         in_constraints  = get_ASM_input_constraints(node);
 514         out_constraints = get_ASM_output_constraints(node);
 515
 516         /* determine size of register_map */
 517         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 518                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 519                 if (constraint->pos > reg_map_size)
 520                         reg_map_size = constraint->pos;
 521         }
 522         for (i = 0; i < arity; ++i) {
 523                 const ir_asm_constraint   *constraint = &in_constraints[i];
 524                 if(constraint->pos > reg_map_size)
 525                         reg_map_size = constraint->pos;
 526         }
 527         ++reg_map_size;
 528
 529         obst         = get_irg_obstack(current_ir_graph);
 530         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 531         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 532
 533         /* construct output constraints */
 534         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 535
 536         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 537                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 538                 const char                *c       = get_id_str(constraint->constraint);
 539                 unsigned                   pos        = constraint->pos;
 540                 constraint_t               parsed_constraint;
 541                 const arch_register_req_t *req;
 542
 543                 parse_asm_constraints(&parsed_constraint, c, 1);
 544                 req = make_register_req(&parsed_constraint, n_out_constraints,
 545                                         out_reg_reqs, out_idx);
 546                 out_reg_reqs[out_idx] = req;
 547
 548                 register_map[pos].use_input = 0;
 549                 register_map[pos].valid     = 1;
 550                 register_map[pos].memory    = 0;
 551                 register_map[pos].inout_pos = out_idx;
 552                 register_map[pos].mode      = constraint->mode;
 553         }
 554
 555         /* inputs + input constraints */
 556         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 557         for (i = 0; i < arity; ++i) {
 558                 ir_node                   *pred         = get_irn_n(node, i);
 559                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 560                 ident                     *constr_id    = constraint->constraint;
 561                 const char                *c            = get_id_str(constr_id);
 562                 unsigned                   pos          = constraint->pos;
 563                 int                        is_memory_op = 0;
 564                 ir_node                   *input        = NULL;
 565                 unsigned                   r_clobber_bits;
 566                 constraint_t               parsed_constraint;
 567                 const arch_register_req_t *req;
 568
 569                 parse_asm_constraints(&parsed_constraint, c, 0);
 570                 if (parsed_constraint.cls != NULL) {
 571                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 572                         if (r_clobber_bits != 0) {
 573                                 if (parsed_constraint.all_registers_allowed) {
 574                                         parsed_constraint.all_registers_allowed = 0;
 575                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 576                                                         parsed_constraint.cls,
 577                                                         &parsed_constraint.allowed_registers);
 578                                 }
 579                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 580                         }
 581                 }
 582
 583                 req = make_register_req(&parsed_constraint, n_out_constraints,
 584                                         out_reg_reqs, i);
 585                 in_reg_reqs[i] = req;
 586
 587                 if (parsed_constraint.immediate_type != '\0') {
 588                         char imm_type = parsed_constraint.immediate_type;
 589                         input = try_create_Immediate(pred, imm_type);
 590                 }
 591
 592                 if (input == NULL) {
 593                         ir_node *pred = NULL;
 594                         switch (be_transformer) {
 595                         case TRANSFORMER_DEFAULT:
 596                                 pred  = get_irn_n(node, i);
 597                                 input = be_transform_node(pred);
 598                                 break;
 599
 600 #ifdef FIRM_GRGEN_BE
 601                         case TRANSFORMER_PBQP:
 602                         case TRANSFORMER_RAND:
 603                                 input = get_irn_n(node, i);
 604                                 break;
 605 #endif
 606
 607                         default: panic("invalid transformer");
 608                         }
 609
 610                         if (parsed_constraint.cls == NULL
 611                                         && parsed_constraint.same_as < 0) {
 612                                 is_memory_op = 1;
 613                         } else if(parsed_constraint.memory_possible) {
 614                                 /* TODO: match Load or Load/Store if memory possible is set */
 615                         }
 616                 }
 617                 in[i] = input;
 618
 619                 register_map[pos].use_input = 1;
 620                 register_map[pos].valid     = 1;
 621                 register_map[pos].memory    = is_memory_op;
 622                 register_map[pos].inout_pos = i;
 623                 register_map[pos].mode      = constraint->mode;
 624         }
 625
 626         /* parse clobbers */
 627         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 628                 const char                *c = get_id_str(clobbers[i]);
 629                 const arch_register_req_t *req;
 630
 631                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 632                         continue;
 633
 634                 req = parse_clobber(c);
 635                 out_reg_reqs[out_idx] = req;
 636                 ++out_idx;
 637         }
 638
 639         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 640                                    get_ASM_text(node), register_map);
 641
 642         if (arity == 0)
 643                 be_dep_on_frame(new_node);
 644
 645         set_ia32_out_req_all(new_node, out_reg_reqs);
 646         set_ia32_in_req_all(new_node, in_reg_reqs);
 647
 648         SET_IA32_ORIG_NODE(new_node, node);
 649
 650         return new_node;
 651 }
 652
 653 ir_node *gen_CopyB(ir_node *node) {
 654         ir_node  *block    = NULL;
 655         ir_node  *src      = NULL;
 656         ir_node  *new_src  = NULL;
 657         ir_node  *dst      = NULL;
 658         ir_node  *new_dst  = NULL;
 659         ir_node  *mem      = NULL;
 660         ir_node  *new_mem  = NULL;
 661         ir_node  *res      = NULL;
 662         dbg_info *dbgi     = get_irn_dbg_info(node);
 663         int      size      = get_type_size_bytes(get_CopyB_type(node));
 664         int      rem;
 665
 666         switch (be_transformer) {
 667                 case TRANSFORMER_DEFAULT:
 668                         block    = be_transform_node(get_nodes_block(node));
 669                         src      = get_CopyB_src(node);
 670                         new_src  = be_transform_node(src);
 671                         dst      = get_CopyB_dst(node);
 672                         new_dst  = be_transform_node(dst);
 673                         mem      = get_CopyB_mem(node);
 674                         new_mem  = be_transform_node(mem);
 675                         break;
 676
 677 #ifdef FIRM_GRGEN_BE
 678                 case TRANSFORMER_PBQP:
 679                 case TRANSFORMER_RAND:
 680                         block    = get_nodes_block(node);
 681                         new_src  = get_CopyB_src(node);
 682                         new_dst  = get_CopyB_dst(node);
 683                         new_mem  = get_CopyB_mem(node);
 684                         break;
 685 #endif
 686
 687                 default: panic("invalid transformer");
 688         }
 689
 690         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 691         /* then we need the size explicitly in ECX.                    */
 692         if (size >= 32 * 4) {
 693                 rem = size & 0x3; /* size % 4 */
 694                 size >>= 2;
 695
 696                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, size);
 697                 be_dep_on_frame(res);
 698
 699                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 700         } else {
 701                 if(size == 0) {
 702                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 703                                    node);
 704                 }
 705                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 706         }
 707
 708         SET_IA32_ORIG_NODE(res, node);
 709
 710         return res;
 711 }
 712
 713 ir_node *gen_Proj_tls(ir_node *node) {
 714         ir_node  *block = NULL;
 715         dbg_info *dbgi  = NULL;
 716         ir_node  *res   = NULL;
 717
 718         switch (be_transformer) {
 719                 case TRANSFORMER_DEFAULT:
 720                         block = be_transform_node(get_nodes_block(node));
 721                         break;
 722
 723 #ifdef FIRM_GRGEN_BE
 724                 case TRANSFORMER_PBQP:
 725                 case TRANSFORMER_RAND:
 726                         block = get_nodes_block(node);
 727                         break;
 728 #endif
 729
 730                 default: panic("invalid transformer");
 731         }
 732
 733         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 734
 735         return res;
 736 }
 737
 738 ir_node *gen_Unknown(ir_node *node)
 739 {
 740         ir_mode *mode = get_irn_mode(node);
 741
 742         if (mode_is_float(mode)) {
 743                 if (ia32_cg_config.use_sse2) {
 744                         return ia32_new_Unknown_xmm(env_cg);
 745                 } else {
 746                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 747                         ir_graph *irg   = current_ir_graph;
 748                         dbg_info *dbgi  = get_irn_dbg_info(node);
 749                         ir_node  *block = get_irg_start_block(irg);
 750                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 751
 752                         be_dep_on_frame(ret);
 753                         return ret;
 754                 }
 755         } else if (ia32_mode_needs_gp_reg(mode)) {
 756                 return ia32_new_Unknown_gp(env_cg);
 757         } else {
 758                 panic("unsupported Unknown-Mode");
 759         }
 760         return NULL;
 761 }
 762
 763 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 764                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 765 {
 766         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 767         int                  same_as = constraint->same_as;
 768         arch_register_req_t *req;
 769
 770         if (same_as >= 0) {
 771                 const arch_register_req_t *other_constr;
 772
 773                 if (same_as >= n_outs)
 774                         panic("invalid output number in same_as constraint");
 775
 776                 other_constr     = out_reqs[same_as];
 777
 778                 req              = obstack_alloc(obst, sizeof(req[0]));
 779                 *req             = *other_constr;
 780                 req->type       |= arch_register_req_type_should_be_same;
 781                 req->other_same  = 1U << pos;
 782
 783                 /* switch constraints. This is because in firm we have same_as
 784                  * constraints on the output constraints while in the gcc asm syntax
 785                  * they are specified on the input constraints */
 786                 out_reqs[same_as] = req;
 787                 return other_constr;
 788         }
 789
 790         /* pure memory ops */
 791         if (constraint->cls == NULL) {
 792                 return &no_register_req;
 793         }
 794
 795         if (constraint->allowed_registers != 0
 796                         && !constraint->all_registers_allowed) {
 797                 unsigned *limited_ptr;
 798
 799                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 800                 memset(req, 0, sizeof(req[0]));
 801                 limited_ptr = (unsigned*) (req+1);
 802
 803                 req->type    = arch_register_req_type_limited;
 804                 *limited_ptr = constraint->allowed_registers;
 805                 req->limited = limited_ptr;
 806         } else {
 807                 req       = obstack_alloc(obst, sizeof(req[0]));
 808                 memset(req, 0, sizeof(req[0]));
 809                 req->type = arch_register_req_type_normal;
 810         }
 811         req->cls = constraint->cls;
 812
 813         return req;
 814 }
 815
 816 const arch_register_req_t *parse_clobber(const char *clobber)
 817 {
 818         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 819         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 820         arch_register_req_t   *req;
 821         unsigned              *limited;
 822
 823         if(reg == NULL) {
 824                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 825         }
 826
 827         assert(reg->index < 32);
 828
 829         limited  = obstack_alloc(obst, sizeof(limited[0]));
 830         *limited = 1 << reg->index;
 831
 832         req          = obstack_alloc(obst, sizeof(req[0]));
 833         memset(req, 0, sizeof(req[0]));
 834         req->type    = arch_register_req_type_limited;
 835         req->cls     = arch_register_get_class(reg);
 836         req->limited = limited;
 837
 838         return req;
 839 }
 840
 841
 842 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 843                        ir_node *const other)
 844 {
 845         if (get_nodes_block(other) != block)
 846                 return 0;
 847
 848         if (is_Sync(other)) {
 849                 int i;
 850
 851                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 852                         ir_node *const pred = get_Sync_pred(other, i);
 853
 854                         if (get_nodes_block(pred) != block)
 855                                 continue;
 856
 857                         /* Do not block ourselves from getting eaten */
 858                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 859                                 continue;
 860
 861                         if (!heights_reachable_in_block(heights, pred, am_candidate))
 862                                 continue;
 863
 864                         return 1;
 865                 }
 866
 867                 return 0;
 868         } else {
 869                 /* Do not block ourselves from getting eaten */
 870                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
 871                         return 0;
 872
 873                 if (!heights_reachable_in_block(heights, other, am_candidate))
 874                         return 0;
 875
 876                 return 1;
 877         }
 878 }
 879
 880 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
 881 {
 882         int          minus         = 0;
 883         tarval      *offset        = NULL;
 884         int          offset_sign   = 0;
 885         long         val = 0;
 886         ir_entity   *symconst_ent  = NULL;
 887         int          symconst_sign = 0;
 888         ir_mode     *mode;
 889         ir_node     *cnst          = NULL;
 890         ir_node     *symconst      = NULL;
 891         ir_node     *new_node;
 892
 893         mode = get_irn_mode(node);
 894         if(!mode_is_int(mode) && !mode_is_reference(mode)) {
 895                 return NULL;
 896         }
 897
 898         if(is_Minus(node)) {
 899                 minus = 1;
 900                 node  = get_Minus_op(node);
 901         }
 902
 903         if(is_Const(node)) {
 904                 cnst        = node;
 905                 symconst    = NULL;
 906                 offset_sign = minus;
 907         } else if(is_SymConst(node)) {
 908                 cnst          = NULL;
 909                 symconst      = node;
 910                 symconst_sign = minus;
 911         } else if(is_Add(node)) {
 912                 ir_node *left  = get_Add_left(node);
 913                 ir_node *right = get_Add_right(node);
 914                 if(is_Const(left) && is_SymConst(right)) {
 915                         cnst          = left;
 916                         symconst      = right;
 917                         symconst_sign = minus;
 918                         offset_sign   = minus;
 919                 } else if(is_SymConst(left) && is_Const(right)) {
 920                         cnst          = right;
 921                         symconst      = left;
 922                         symconst_sign = minus;
 923                         offset_sign   = minus;
 924                 }
 925         } else if(is_Sub(node)) {
 926                 ir_node *left  = get_Sub_left(node);
 927                 ir_node *right = get_Sub_right(node);
 928                 if(is_Const(left) && is_SymConst(right)) {
 929                         cnst          = left;
 930                         symconst      = right;
 931                         symconst_sign = !minus;
 932                         offset_sign   = minus;
 933                 } else if(is_SymConst(left) && is_Const(right)) {
 934                         cnst          = right;
 935                         symconst      = left;
 936                         symconst_sign = minus;
 937                         offset_sign   = !minus;
 938                 }
 939         } else {
 940                 return NULL;
 941         }
 942
 943         if(cnst != NULL) {
 944                 offset = get_Const_tarval(cnst);
 945                 if(tarval_is_long(offset)) {
 946                         val = get_tarval_long(offset);
 947                 } else {
 948                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
 949                                    "long?\n", cnst);
 950                         return NULL;
 951                 }
 952
 953                 if(!check_immediate_constraint(val, immediate_constraint_type))
 954                         return NULL;
 955         }
 956         if(symconst != NULL) {
 957                 if(immediate_constraint_type != 0) {
 958                         /* we need full 32bits for symconsts */
 959                         return NULL;
 960                 }
 961
 962                 /* unfortunately the assembler/linker doesn't support -symconst */
 963                 if(symconst_sign)
 964                         return NULL;
 965
 966                 if(get_SymConst_kind(symconst) != symconst_addr_ent)
 967                         return NULL;
 968                 symconst_ent = get_SymConst_entity(symconst);
 969         }
 970         if(cnst == NULL && symconst == NULL)
 971                 return NULL;
 972
 973         if(offset_sign && offset != NULL) {
 974                 offset = tarval_neg(offset);
 975         }
 976
 977         new_node = create_Immediate(symconst_ent, symconst_sign, val);
 978
 979         return new_node;
 980 }