nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33 #include "bitset.h"
  34
  35 #include "../betranshlp.h"
  36 #include "../beirg_t.h"
  37
  38 #include "ia32_architecture.h"
  39 #include "ia32_common_transform.h"
  40 #include "ia32_new_nodes.h"
  41
  42 #include "gen_ia32_new_nodes.h"
  43 #include "gen_ia32_regalloc_if.h"
  44
  45 /** hold the current code generator during transformation */
  46 ia32_code_gen_t *env_cg = NULL;
  47
  48 heights_t *heights = NULL;
  49
  50 static const arch_register_req_t no_register_req = {
  51         arch_register_req_type_none,
  52         NULL,                         /* regclass */
  53         NULL,                         /* limit bitset */
  54         0,                            /* same pos */
  55         0                             /* different pos */
  56 };
  57
  58 static int check_immediate_constraint(long val, char immediate_constraint_type)
  59 {
  60         switch (immediate_constraint_type) {
  61                 case 0:
  62                 case 'i': return 1;
  63
  64                 case 'I': return    0 <= val && val <=  31;
  65                 case 'J': return    0 <= val && val <=  63;
  66                 case 'K': return -128 <= val && val <= 127;
  67                 case 'L': return val == 0xff || val == 0xffff;
  68                 case 'M': return    0 <= val && val <=   3;
  69                 case 'N': return    0 <= val && val <= 255;
  70                 case 'O': return    0 <= val && val <= 127;
  71
  72                 default: panic("Invalid immediate constraint found");
  73         }
  74 }
  75
  76 /* creates a unique ident by adding a number to a tag */
  77 ident *ia32_unique_id(const char *tag)
  78 {
  79         static unsigned id = 0;
  80         char str[256];
  81
  82         snprintf(str, sizeof(str), tag, ++id);
  83         return new_id_from_str(str);
  84 }
  85
  86 /**
  87  * Get a primitive type for a mode with alignment 16.
  88  */
  89 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  90 {
  91         pmap_entry *e = pmap_find(types, mode);
  92         ir_type *res;
  93
  94         if (! e) {
  95                 char buf[64];
  96                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
  97                 res = new_type_primitive(new_id_from_str(buf), mode);
  98                 if (get_mode_size_bits(mode) >= 80) {
  99                         set_type_alignment_bytes(res, 16);
 100                 }
 101                 pmap_insert(types, mode, res);
 102         }
 103         else
 104                 res = e->value;
 105         return res;
 106 }
 107
 108 ir_entity *create_float_const_entity(ir_node *cnst)
 109 {
 110         ia32_isa_t *isa = env_cg->isa;
 111         tarval *key     = get_Const_tarval(cnst);
 112         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 113         ir_entity *res;
 114         ir_graph *rem;
 115
 116         if (e == NULL) {
 117                 tarval  *tv   = key;
 118                 ir_mode *mode = get_tarval_mode(tv);
 119                 ir_type *tp;
 120
 121                 if (! ia32_cg_config.use_sse2) {
 122                         /* try to reduce the mode to produce smaller sized entities */
 123                         if (mode != mode_F) {
 124                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 125                                         mode = mode_F;
 126                                         tv = tarval_convert_to(tv, mode);
 127                                 } else if (mode != mode_D) {
 128                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 129                                                 mode = mode_D;
 130                                                 tv = tarval_convert_to(tv, mode);
 131                                         }
 132                                 }
 133                         }
 134                 }
 135
 136                 if (mode == get_irn_mode(cnst)) {
 137                         /* mode was not changed */
 138                         tp = get_Const_type(cnst);
 139                         if (tp == firm_unknown_type)
 140                                 tp = ia32_get_prim_type(isa->types, mode);
 141                 } else
 142                         tp = ia32_get_prim_type(isa->types, mode);
 143
 144                 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
 145
 146                 set_entity_ld_ident(res, get_entity_ident(res));
 147                 set_entity_visibility(res, visibility_local);
 148                 set_entity_variability(res, variability_constant);
 149                 set_entity_allocation(res, allocation_static);
 150
 151                  /* we create a new entity here: It's initialization must resist on the
 152                     const code irg */
 153                 rem = current_ir_graph;
 154                 current_ir_graph = get_const_code_irg();
 155                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 156                 current_ir_graph = rem;
 157
 158                 pmap_insert(isa->tv_ent, key, res);
 159         } else {
 160                 res = e->value;
 161         }
 162
 163         return res;
 164 }
 165
 166 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 167 {
 168         ir_graph *irg         = current_ir_graph;
 169         ir_node  *start_block = get_irg_start_block(irg);
 170         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 171                         symconst_sign, no_pic_adjust, val);
 172         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 173
 174         return immediate;
 175 }
 176
 177 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 178 {
 179         const arch_register_t       *reg = NULL;
 180         int                          c;
 181         size_t                       r;
 182         const arch_register_class_t *cls;
 183
 184         /* TODO: construct a hashmap instead of doing linear search for clobber
 185          * register */
 186         for(c = 0; c < N_CLASSES; ++c) {
 187                 cls = & ia32_reg_classes[c];
 188                 for(r = 0; r < cls->n_regs; ++r) {
 189                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 190                         if (strcmp(temp_reg->name, clobber) == 0
 191                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 192                                 reg = temp_reg;
 193                                 break;
 194                         }
 195                 }
 196                 if (reg != NULL)
 197                         break;
 198         }
 199
 200         return reg;
 201 }
 202
 203 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 204         if (mode == mode_fpcw)
 205                 return 0;
 206         if (get_mode_size_bits(mode) > 32)
 207                 return 0;
 208         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 209 }
 210
 211 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 212                            int is_output)
 213 {
 214         char                         immediate_type     = '\0';
 215         unsigned                     limited            = 0;
 216         const arch_register_class_t *cls                = NULL;
 217         int                          memory_possible       = 0;
 218         int                          all_registers_allowed = 0;
 219         int                          p;
 220         int                          same_as = -1;
 221
 222         memset(constraint, 0, sizeof(constraint[0]));
 223         constraint->same_as = -1;
 224
 225         if (*c == 0) {
 226                 /* a memory constraint: no need to do anything in backend about it
 227                  * (the dependencies are already respected by the memory edge of
 228                  * the node) */
 229                 return;
 230         }
 231
 232         /* TODO: improve error messages with node and source info. (As users can
 233          * easily hit these) */
 234         while(*c != 0) {
 235                 switch(*c) {
 236                 case ' ':
 237                 case '\t':
 238                 case '\n':
 239                         break;
 240
 241                 /* Skip out/in-out marker */
 242                 case '=': break;
 243                 case '+': break;
 244
 245                 case '&': break;
 246
 247                 case '*':
 248                         ++c;
 249                         break;
 250                 case '#':
 251                         while(*c != 0 && *c != ',')
 252                                 ++c;
 253                         break;
 254
 255                 case 'a':
 256                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 257                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 258                         limited |= 1 << REG_EAX;
 259                         break;
 260                 case 'b':
 261                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 262                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 263                         limited |= 1 << REG_EBX;
 264                         break;
 265                 case 'c':
 266                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 267                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 268                         limited |= 1 << REG_ECX;
 269                         break;
 270                 case 'd':
 271                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 272                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 273                         limited |= 1 << REG_EDX;
 274                         break;
 275                 case 'D':
 276                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 277                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 278                         limited |= 1 << REG_EDI;
 279                         break;
 280                 case 'S':
 281                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 282                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 283                         limited |= 1 << REG_ESI;
 284                         break;
 285                 case 'Q':
 286                 case 'q':
 287                         /* q means lower part of the regs only, this makes no
 288                          * difference to Q for us (we only assign whole registers) */
 289                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 290                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 291                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 292                                    1 << REG_EDX;
 293                         break;
 294                 case 'A':
 295                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 296                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 297                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 298                         break;
 299                 case 'l':
 300                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 301                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 302                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 303                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 304                                    1 << REG_EBP;
 305                         break;
 306
 307                 case 'R':
 308                 case 'r':
 309                 case 'p':
 310                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 311                                 panic("multiple register classes not supported");
 312                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 313                         all_registers_allowed = 1;
 314                         break;
 315
 316                 case 'f':
 317                 case 't':
 318                 case 'u':
 319                         /* TODO: mark values so the x87 simulator knows about t and u */
 320                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 321                                 panic("multiple register classes not supported");
 322                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 323                         all_registers_allowed = 1;
 324                         break;
 325
 326                 case 'Y':
 327                 case 'x':
 328                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 329                                 panic("multiple register classes not supproted");
 330                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 331                         all_registers_allowed = 1;
 332                         break;
 333
 334                 case 'I':
 335                 case 'J':
 336                 case 'K':
 337                 case 'L':
 338                 case 'M':
 339                 case 'N':
 340                 case 'O':
 341                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 342                                 panic("multiple register classes not supported");
 343                         if (immediate_type != '\0')
 344                                 panic("multiple immediate types not supported");
 345                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 346                         immediate_type = *c;
 347                         break;
 348                 case 'n':
 349                 case 'i':
 350                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 351                                 panic("multiple register classes not supported");
 352                         if (immediate_type != '\0')
 353                                 panic("multiple immediate types not supported");
 354                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 355                         immediate_type = 'i';
 356                         break;
 357
 358                 case 'X':
 359                 case 'g':
 360                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 361                                 panic("multiple register classes not supported");
 362                         if (immediate_type != '\0')
 363                                 panic("multiple immediate types not supported");
 364                         immediate_type        = 'i';
 365                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 366                         all_registers_allowed = 1;
 367                         memory_possible       = 1;
 368                         break;
 369
 370                 case '0':
 371                 case '1':
 372                 case '2':
 373                 case '3':
 374                 case '4':
 375                 case '5':
 376                 case '6':
 377                 case '7':
 378                 case '8':
 379                 case '9':
 380                         if (is_output)
 381                                 panic("can only specify same constraint on input");
 382
 383                         sscanf(c, "%d%n", &same_as, &p);
 384                         if (same_as >= 0) {
 385                                 c += p;
 386                                 continue;
 387                         }
 388                         break;
 389
 390                 case 'm':
 391                 case 'o':
 392                 case 'V':
 393                         /* memory constraint no need to do anything in backend about it
 394                          * (the dependencies are already respected by the memory edge of
 395                          * the node) */
 396                         memory_possible = 1;
 397                         break;
 398
 399                 case 'E': /* no float consts yet */
 400                 case 'F': /* no float consts yet */
 401                 case 's': /* makes no sense on x86 */
 402                 case '<': /* no autodecrement on x86 */
 403                 case '>': /* no autoincrement on x86 */
 404                 case 'C': /* sse constant not supported yet */
 405                 case 'G': /* 80387 constant not supported yet */
 406                 case 'y': /* we don't support mmx registers yet */
 407                 case 'Z': /* not available in 32 bit mode */
 408                 case 'e': /* not available in 32 bit mode */
 409                         panic("unsupported asm constraint '%c' found in (%+F)",
 410                               *c, current_ir_graph);
 411                         break;
 412                 default:
 413                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 414                               current_ir_graph);
 415                         break;
 416                 }
 417                 ++c;
 418         }
 419
 420         if (same_as >= 0) {
 421                 if (cls != NULL)
 422                         panic("same as and register constraint not supported");
 423                 if (immediate_type != '\0')
 424                         panic("same as and immediate constraint not supported");
 425         }
 426
 427         if (cls == NULL && same_as < 0) {
 428                 if (!memory_possible)
 429                         panic("no constraint specified for assembler input");
 430         }
 431
 432         constraint->same_as               = same_as;
 433         constraint->cls                   = cls;
 434         constraint->allowed_registers     = limited;
 435         constraint->all_registers_allowed = all_registers_allowed;
 436         constraint->memory_possible       = memory_possible;
 437         constraint->immediate_type        = immediate_type;
 438 }
 439
 440 static bool can_match(const arch_register_req_t *in,
 441                       const arch_register_req_t *out)
 442 {
 443         if (in->cls != out->cls)
 444                 return false;
 445         if ( (in->type & arch_register_req_type_limited) == 0
 446                 || (out->type & arch_register_req_type_limited) == 0 )
 447                 return true;
 448
 449         return (*in->limited & *out->limited) != 0;
 450 }
 451
 452 ir_node *gen_ASM(ir_node *node)
 453 {
 454         ir_node                    *block = NULL;
 455         ir_node                    *new_block = NULL;
 456         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 457         int                         i, arity;
 458         int                         out_idx;
 459         ir_node                   **in;
 460         ir_node                    *new_node;
 461         int                         out_arity;
 462         int                         n_out_constraints;
 463         int                         n_clobbers;
 464         const arch_register_req_t **out_reg_reqs;
 465         const arch_register_req_t **in_reg_reqs;
 466         ia32_asm_reg_t             *register_map;
 467         unsigned                    reg_map_size = 0;
 468         struct obstack             *obst;
 469         const ir_asm_constraint    *in_constraints;
 470         const ir_asm_constraint    *out_constraints;
 471         ident                     **clobbers;
 472         int                         clobbers_flags = 0;
 473         unsigned                    clobber_bits[N_CLASSES];
 474
 475         memset(&clobber_bits, 0, sizeof(clobber_bits));
 476
 477         switch (be_transformer) {
 478         case TRANSFORMER_DEFAULT:
 479                 block     = get_nodes_block(node);
 480                 new_block = be_transform_node(block);
 481                 break;
 482
 483 #ifdef FIRM_GRGEN_BE
 484         case TRANSFORMER_PBQP:
 485         case TRANSFORMER_RAND:
 486                 new_block = get_nodes_block(node);
 487                 break;
 488 #endif
 489
 490         default:
 491                 panic("invalid transformer");
 492         }
 493
 494         /* workaround for lots of buggy code out there as most people think volatile
 495          * asm is enough for everything and forget the flags (linux kernel, etc.)
 496          */
 497         if (get_irn_pinned(node) == op_pin_state_pinned) {
 498                 clobbers_flags = 1;
 499         }
 500
 501         arity = get_irn_arity(node);
 502         in    = ALLOCANZ(ir_node*, arity);
 503
 504         clobbers   = get_ASM_clobbers(node);
 505         n_clobbers = 0;
 506         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 507                 const arch_register_req_t *req;
 508                 const char                *c = get_id_str(clobbers[i]);
 509
 510                 if (strcmp(c, "memory") == 0)
 511                         continue;
 512                 if (strcmp(c, "cc") == 0) {
 513                         clobbers_flags = 1;
 514                         continue;
 515                 }
 516
 517                 req = parse_clobber(c);
 518                 clobber_bits[req->cls->index] |= *req->limited;
 519
 520                 n_clobbers++;
 521         }
 522         n_out_constraints = get_ASM_n_output_constraints(node);
 523         out_arity         = n_out_constraints + n_clobbers;
 524
 525         in_constraints  = get_ASM_input_constraints(node);
 526         out_constraints = get_ASM_output_constraints(node);
 527
 528         /* determine size of register_map */
 529         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 530                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 531                 if (constraint->pos > reg_map_size)
 532                         reg_map_size = constraint->pos;
 533         }
 534         for (i = 0; i < arity; ++i) {
 535                 const ir_asm_constraint   *constraint = &in_constraints[i];
 536                 if (constraint->pos > reg_map_size)
 537                         reg_map_size = constraint->pos;
 538         }
 539         ++reg_map_size;
 540
 541         obst         = get_irg_obstack(current_ir_graph);
 542         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 543         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 544
 545         /* construct output constraints */
 546         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 547
 548         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 549                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 550                 const char                *c       = get_id_str(constraint->constraint);
 551                 unsigned                   pos        = constraint->pos;
 552                 constraint_t               parsed_constraint;
 553                 const arch_register_req_t *req;
 554
 555                 parse_asm_constraints(&parsed_constraint, c, 1);
 556                 req = make_register_req(&parsed_constraint, n_out_constraints,
 557                                         out_reg_reqs, out_idx);
 558                 out_reg_reqs[out_idx] = req;
 559
 560                 register_map[pos].use_input = 0;
 561                 register_map[pos].valid     = 1;
 562                 register_map[pos].memory    = 0;
 563                 register_map[pos].inout_pos = out_idx;
 564                 register_map[pos].mode      = constraint->mode;
 565         }
 566
 567         /* inputs + input constraints */
 568         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 569         for (i = 0; i < arity; ++i) {
 570                 ir_node                   *pred         = get_irn_n(node, i);
 571                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 572                 ident                     *constr_id    = constraint->constraint;
 573                 const char                *c            = get_id_str(constr_id);
 574                 unsigned                   pos          = constraint->pos;
 575                 int                        is_memory_op = 0;
 576                 ir_node                   *input        = NULL;
 577                 unsigned                   r_clobber_bits;
 578                 constraint_t               parsed_constraint;
 579                 const arch_register_req_t *req;
 580
 581                 parse_asm_constraints(&parsed_constraint, c, 0);
 582                 if (parsed_constraint.cls != NULL) {
 583                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 584                         if (r_clobber_bits != 0) {
 585                                 if (parsed_constraint.all_registers_allowed) {
 586                                         parsed_constraint.all_registers_allowed = 0;
 587                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 588                                                         parsed_constraint.cls,
 589                                                         &parsed_constraint.allowed_registers);
 590                                 }
 591                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 592                         }
 593                 }
 594
 595                 req = make_register_req(&parsed_constraint, n_out_constraints,
 596                                         out_reg_reqs, i);
 597                 in_reg_reqs[i] = req;
 598
 599                 if (parsed_constraint.immediate_type != '\0') {
 600                         char imm_type = parsed_constraint.immediate_type;
 601                         input = try_create_Immediate(pred, imm_type);
 602                 }
 603
 604                 if (input == NULL) {
 605                         ir_node *pred = NULL;
 606                         switch (be_transformer) {
 607                         case TRANSFORMER_DEFAULT:
 608                                 pred  = get_irn_n(node, i);
 609                                 input = be_transform_node(pred);
 610                                 break;
 611
 612 #ifdef FIRM_GRGEN_BE
 613                         case TRANSFORMER_PBQP:
 614                         case TRANSFORMER_RAND:
 615                                 input = get_irn_n(node, i);
 616                                 break;
 617 #endif
 618
 619                         default: panic("invalid transformer");
 620                         }
 621
 622                         if (parsed_constraint.cls == NULL
 623                                         && parsed_constraint.same_as < 0) {
 624                                 is_memory_op = 1;
 625                         } else if (parsed_constraint.memory_possible) {
 626                                 /* TODO: match Load or Load/Store if memory possible is set */
 627                         }
 628                 }
 629                 in[i] = input;
 630
 631                 register_map[pos].use_input = 1;
 632                 register_map[pos].valid     = 1;
 633                 register_map[pos].memory    = is_memory_op;
 634                 register_map[pos].inout_pos = i;
 635                 register_map[pos].mode      = constraint->mode;
 636         }
 637
 638         /* parse clobbers */
 639         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 640                 const char                *c = get_id_str(clobbers[i]);
 641                 const arch_register_req_t *req;
 642
 643                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 644                         continue;
 645
 646                 req = parse_clobber(c);
 647                 out_reg_reqs[out_idx] = req;
 648                 ++out_idx;
 649         }
 650
 651         /* Attempt to make ASM node register pressure faithfull.
 652          * (This does not work for complicated cases yet!)
 653          *
 654          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 655          * the smaller list). Then try to match each constraint of the smaller list
 656          * to 1 of the other list. If we can't match it, then we have to add a dummy
 657          * input/output to the other list
 658          *
 659          * FIXME: This is still broken in lots of cases. But at least better than
 660          *        before...
 661          * FIXME: need to do this per register class...
 662          */
 663         if (out_arity <= arity) {
 664                 int       orig_arity = arity;
 665                 int       in_size    = arity;
 666                 int       o;
 667                 bitset_t *used_ins = bitset_alloca(arity);
 668                 for (o = 0; o < out_arity; ++o) {
 669                         int   i;
 670                         const arch_register_req_t *outreq = out_reg_reqs[o];
 671
 672                         if (outreq->cls == NULL) {
 673                                 continue;
 674                         }
 675
 676                         for (i = 0; i < orig_arity; ++i) {
 677                                 const arch_register_req_t *inreq;
 678                                 if (bitset_is_set(used_ins, i))
 679                                         continue;
 680                                 inreq = in_reg_reqs[i];
 681                                 if (!can_match(outreq, inreq))
 682                                         continue;
 683                                 bitset_set(used_ins, i);
 684                                 break;
 685                         }
 686                         /* did we find any match? */
 687                         if (i < orig_arity)
 688                                 continue;
 689
 690                         /* we might need more space in the input arrays */
 691                         if (arity >= in_size) {
 692                                 const arch_register_req_t **new_in_reg_reqs;
 693                                 ir_node             **new_in;
 694
 695                                 in_size *= 2;
 696                                 new_in_reg_reqs
 697                                         = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
 698                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 699                                 new_in = ALLOCANZ(ir_node*, in_size);
 700                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 701
 702                                 in_reg_reqs = new_in_reg_reqs;
 703                                 in          = new_in;
 704                         }
 705
 706                         /* add a new (dummy) input which occupies the register */
 707                         assert(outreq->type & arch_register_req_type_limited);
 708                         in_reg_reqs[arity] = outreq;
 709                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 710                         be_dep_on_frame(in[arity]);
 711                         ++arity;
 712                 }
 713         } else {
 714                 int       i;
 715                 bitset_t *used_outs = bitset_alloca(out_arity);
 716                 int       orig_out_arity = out_arity;
 717                 int       out_size       = out_arity;
 718                 for (i = 0; i < arity; ++i) {
 719                         int   o;
 720                         const arch_register_req_t *inreq = in_reg_reqs[i];
 721
 722                         if (inreq->cls == NULL) {
 723                                 continue;
 724                         }
 725
 726                         for (o = 0; o < orig_out_arity; ++o) {
 727                                 const arch_register_req_t *outreq;
 728                                 if (bitset_is_set(used_outs, o))
 729                                         continue;
 730                                 outreq = out_reg_reqs[o];
 731                                 if (!can_match(outreq, inreq))
 732                                         continue;
 733                                 bitset_set(used_outs, i);
 734                                 break;
 735                         }
 736                         /* did we find any match? */
 737                         if (o < orig_out_arity)
 738                                 continue;
 739
 740                         /* we might need more space in the output arrays */
 741                         if (out_arity >= out_size) {
 742                                 const arch_register_req_t **new_out_reg_reqs;
 743
 744                                 out_size *= 2;
 745                                 new_out_reg_reqs
 746                                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 747                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 748                                        out_arity * sizeof(new_out_reg_reqs[0]));
 749                                 out_reg_reqs = new_out_reg_reqs;
 750                         }
 751
 752                         /* add a new (dummy) output which occupies the register */
 753                         assert(inreq->type & arch_register_req_type_limited);
 754                         out_reg_reqs[out_arity] = inreq;
 755                         ++out_arity;
 756                 }
 757         }
 758
 759         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 760                                    get_ASM_text(node), register_map);
 761
 762         if (arity == 0)
 763                 be_dep_on_frame(new_node);
 764
 765         set_ia32_out_req_all(new_node, out_reg_reqs);
 766         set_ia32_in_req_all(new_node, in_reg_reqs);
 767
 768         SET_IA32_ORIG_NODE(new_node, node);
 769
 770         return new_node;
 771 }
 772
 773 ir_node *gen_CopyB(ir_node *node) {
 774         ir_node  *block    = NULL;
 775         ir_node  *src      = NULL;
 776         ir_node  *new_src  = NULL;
 777         ir_node  *dst      = NULL;
 778         ir_node  *new_dst  = NULL;
 779         ir_node  *mem      = NULL;
 780         ir_node  *new_mem  = NULL;
 781         ir_node  *res      = NULL;
 782         dbg_info *dbgi     = get_irn_dbg_info(node);
 783         int      size      = get_type_size_bytes(get_CopyB_type(node));
 784         int      rem;
 785
 786         switch (be_transformer) {
 787                 case TRANSFORMER_DEFAULT:
 788                         block    = be_transform_node(get_nodes_block(node));
 789                         src      = get_CopyB_src(node);
 790                         new_src  = be_transform_node(src);
 791                         dst      = get_CopyB_dst(node);
 792                         new_dst  = be_transform_node(dst);
 793                         mem      = get_CopyB_mem(node);
 794                         new_mem  = be_transform_node(mem);
 795                         break;
 796
 797 #ifdef FIRM_GRGEN_BE
 798                 case TRANSFORMER_PBQP:
 799                 case TRANSFORMER_RAND:
 800                         block    = get_nodes_block(node);
 801                         new_src  = get_CopyB_src(node);
 802                         new_dst  = get_CopyB_dst(node);
 803                         new_mem  = get_CopyB_mem(node);
 804                         break;
 805 #endif
 806
 807                 default: panic("invalid transformer");
 808         }
 809
 810         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 811         /* then we need the size explicitly in ECX.                    */
 812         if (size >= 32 * 4) {
 813                 rem = size & 0x3; /* size % 4 */
 814                 size >>= 2;
 815
 816                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 817                 be_dep_on_frame(res);
 818
 819                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 820         } else {
 821                 if (size == 0) {
 822                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 823                                    node);
 824                 }
 825                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 826         }
 827
 828         SET_IA32_ORIG_NODE(res, node);
 829
 830         return res;
 831 }
 832
 833 ir_node *gen_Proj_tls(ir_node *node) {
 834         ir_node  *block = NULL;
 835         dbg_info *dbgi  = NULL;
 836         ir_node  *res   = NULL;
 837
 838         switch (be_transformer) {
 839                 case TRANSFORMER_DEFAULT:
 840                         block = be_transform_node(get_nodes_block(node));
 841                         break;
 842
 843 #ifdef FIRM_GRGEN_BE
 844                 case TRANSFORMER_PBQP:
 845                 case TRANSFORMER_RAND:
 846                         block = get_nodes_block(node);
 847                         break;
 848 #endif
 849
 850                 default: panic("invalid transformer");
 851         }
 852
 853         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 854
 855         return res;
 856 }
 857
 858 ir_node *gen_Unknown(ir_node *node)
 859 {
 860         ir_mode *mode = get_irn_mode(node);
 861
 862         if (mode_is_float(mode)) {
 863                 if (ia32_cg_config.use_sse2) {
 864                         return ia32_new_Unknown_xmm(env_cg);
 865                 } else {
 866                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 867                         ir_graph *irg   = current_ir_graph;
 868                         dbg_info *dbgi  = get_irn_dbg_info(node);
 869                         ir_node  *block = get_irg_start_block(irg);
 870                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 871
 872                         be_dep_on_frame(ret);
 873                         return ret;
 874                 }
 875         } else if (ia32_mode_needs_gp_reg(mode)) {
 876                 return ia32_new_Unknown_gp(env_cg);
 877         } else {
 878                 panic("unsupported Unknown-Mode");
 879         }
 880         return NULL;
 881 }
 882
 883 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 884                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 885 {
 886         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 887         int                  same_as = constraint->same_as;
 888         arch_register_req_t *req;
 889
 890         if (same_as >= 0) {
 891                 const arch_register_req_t *other_constr;
 892
 893                 if (same_as >= n_outs)
 894                         panic("invalid output number in same_as constraint");
 895
 896                 other_constr     = out_reqs[same_as];
 897
 898                 req              = obstack_alloc(obst, sizeof(req[0]));
 899                 *req             = *other_constr;
 900                 req->type       |= arch_register_req_type_should_be_same;
 901                 req->other_same  = 1U << pos;
 902
 903                 /* switch constraints. This is because in firm we have same_as
 904                  * constraints on the output constraints while in the gcc asm syntax
 905                  * they are specified on the input constraints */
 906                 out_reqs[same_as] = req;
 907                 return other_constr;
 908         }
 909
 910         /* pure memory ops */
 911         if (constraint->cls == NULL) {
 912                 return &no_register_req;
 913         }
 914
 915         if (constraint->allowed_registers != 0
 916                         && !constraint->all_registers_allowed) {
 917                 unsigned *limited_ptr;
 918
 919                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 920                 memset(req, 0, sizeof(req[0]));
 921                 limited_ptr = (unsigned*) (req+1);
 922
 923                 req->type    = arch_register_req_type_limited;
 924                 *limited_ptr = constraint->allowed_registers;
 925                 req->limited = limited_ptr;
 926         } else {
 927                 req       = obstack_alloc(obst, sizeof(req[0]));
 928                 memset(req, 0, sizeof(req[0]));
 929                 req->type = arch_register_req_type_normal;
 930         }
 931         req->cls = constraint->cls;
 932
 933         return req;
 934 }
 935
 936 const arch_register_req_t *parse_clobber(const char *clobber)
 937 {
 938         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 939         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 940         arch_register_req_t   *req;
 941         unsigned              *limited;
 942
 943         if (reg == NULL) {
 944                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 945         }
 946
 947         assert(reg->index < 32);
 948
 949         limited  = obstack_alloc(obst, sizeof(limited[0]));
 950         *limited = 1 << reg->index;
 951
 952         req          = obstack_alloc(obst, sizeof(req[0]));
 953         memset(req, 0, sizeof(req[0]));
 954         req->type    = arch_register_req_type_limited;
 955         req->cls     = arch_register_get_class(reg);
 956         req->limited = limited;
 957
 958         return req;
 959 }
 960
 961
 962 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 963                        ir_node *const other)
 964 {
 965         if (get_nodes_block(other) != block)
 966                 return 0;
 967
 968         if (is_Sync(other)) {
 969                 int i;
 970
 971                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 972                         ir_node *const pred = get_Sync_pred(other, i);
 973
 974                         if (get_nodes_block(pred) != block)
 975                                 continue;
 976
 977                         /* Do not block ourselves from getting eaten */
 978                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 979                                 continue;
 980
 981                         if (!heights_reachable_in_block(heights, pred, am_candidate))
 982                                 continue;
 983
 984                         return 1;
 985                 }
 986
 987                 return 0;
 988         } else {
 989                 /* Do not block ourselves from getting eaten */
 990                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
 991                         return 0;
 992
 993                 if (!heights_reachable_in_block(heights, other, am_candidate))
 994                         return 0;
 995
 996                 return 1;
 997         }
 998 }
 999
1000 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
1001 {
1002         int          minus         = 0;
1003         tarval      *offset        = NULL;
1004         int          offset_sign   = 0;
1005         long         val = 0;
1006         ir_entity   *symconst_ent  = NULL;
1007         int          symconst_sign = 0;
1008         ir_mode     *mode;
1009         ir_node     *cnst          = NULL;
1010         ir_node     *symconst      = NULL;
1011         ir_node     *new_node;
1012
1013         mode = get_irn_mode(node);
1014         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
1015                 return NULL;
1016         }
1017
1018         if (is_Minus(node)) {
1019                 minus = 1;
1020                 node  = get_Minus_op(node);
1021         }
1022
1023         if (is_Const(node)) {
1024                 cnst        = node;
1025                 symconst    = NULL;
1026                 offset_sign = minus;
1027         } else if (is_SymConst(node)) {
1028                 cnst          = NULL;
1029                 symconst      = node;
1030                 symconst_sign = minus;
1031         } else if (is_Add(node)) {
1032                 ir_node *left  = get_Add_left(node);
1033                 ir_node *right = get_Add_right(node);
1034                 if (is_Const(left) && is_SymConst(right)) {
1035                         cnst          = left;
1036                         symconst      = right;
1037                         symconst_sign = minus;
1038                         offset_sign   = minus;
1039                 } else if (is_SymConst(left) && is_Const(right)) {
1040                         cnst          = right;
1041                         symconst      = left;
1042                         symconst_sign = minus;
1043                         offset_sign   = minus;
1044                 }
1045         } else if (is_Sub(node)) {
1046                 ir_node *left  = get_Sub_left(node);
1047                 ir_node *right = get_Sub_right(node);
1048                 if (is_Const(left) && is_SymConst(right)) {
1049                         cnst          = left;
1050                         symconst      = right;
1051                         symconst_sign = !minus;
1052                         offset_sign   = minus;
1053                 } else if (is_SymConst(left) && is_Const(right)) {
1054                         cnst          = right;
1055                         symconst      = left;
1056                         symconst_sign = minus;
1057                         offset_sign   = !minus;
1058                 }
1059         } else {
1060                 return NULL;
1061         }
1062
1063         if (cnst != NULL) {
1064                 offset = get_Const_tarval(cnst);
1065                 if (tarval_is_long(offset)) {
1066                         val = get_tarval_long(offset);
1067                 } else {
1068                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
1069                                    "long?\n", cnst);
1070                         return NULL;
1071                 }
1072
1073                 if (!check_immediate_constraint(val, immediate_constraint_type))
1074                         return NULL;
1075         }
1076         if (symconst != NULL) {
1077                 if (immediate_constraint_type != 0) {
1078                         /* we need full 32bits for symconsts */
1079                         return NULL;
1080                 }
1081
1082                 /* unfortunately the assembler/linker doesn't support -symconst */
1083                 if (symconst_sign)
1084                         return NULL;
1085
1086                 if (get_SymConst_kind(symconst) != symconst_addr_ent)
1087                         return NULL;
1088                 symconst_ent = get_SymConst_entity(symconst);
1089         }
1090         if (cnst == NULL && symconst == NULL)
1091                 return NULL;
1092
1093         if (offset_sign && offset != NULL) {
1094                 offset = tarval_neg(offset);
1095         }
1096
1097         new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val);
1098
1099         return new_node;
1100 }