nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "error.h"
  32 #include "irargs_t.h"
  33 #include "ircons.h"
  34 #include "irprintf.h"
  35 #include "typerep.h"
  36
  37 #include "../betranshlp.h"
  38 #include "../beirg_t.h"
  39
  40 #include "ia32_architecture.h"
  41 #include "ia32_common_transform.h"
  42 #include "ia32_new_nodes.h"
  43
  44 #include "gen_ia32_new_nodes.h"
  45 #include "gen_ia32_regalloc_if.h"
  46
  47 /** hold the current code generator during transformation */
  48 ia32_code_gen_t *env_cg = NULL;
  49
  50 heights_t *heights = NULL;
  51
  52 static const arch_register_req_t no_register_req = {
  53         arch_register_req_type_none,
  54         NULL,                         /* regclass */
  55         NULL,                         /* limit bitset */
  56         0,                            /* same pos */
  57         0                             /* different pos */
  58 };
  59
  60 static int check_immediate_constraint(long val, char immediate_constraint_type)
  61 {
  62         switch (immediate_constraint_type) {
  63                 case 0:
  64                 case 'i': return 1;
  65
  66                 case 'I': return    0 <= val && val <=  31;
  67                 case 'J': return    0 <= val && val <=  63;
  68                 case 'K': return -128 <= val && val <= 127;
  69                 case 'L': return val == 0xff || val == 0xffff;
  70                 case 'M': return    0 <= val && val <=   3;
  71                 case 'N': return    0 <= val && val <= 255;
  72                 case 'O': return    0 <= val && val <= 127;
  73
  74                 default: panic("Invalid immediate constraint found");
  75         }
  76 }
  77
  78 /**
  79  * creates a unique ident by adding a number to a tag
  80  *
  81  * @param tag   the tag string, must contain a %d if a number
  82  *              should be added
  83  */
  84 static ident *unique_id(const char *tag)
  85 {
  86         static unsigned id = 0;
  87         char str[256];
  88
  89         snprintf(str, sizeof(str), tag, ++id);
  90         return new_id_from_str(str);
  91 }
  92
  93 /**
  94  * Get a primitive type for a mode.
  95  */
  96 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  97 {
  98         pmap_entry *e = pmap_find(types, mode);
  99         ir_type *res;
 100
 101         if (! e) {
 102                 char buf[64];
 103                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
 104                 res = new_type_primitive(new_id_from_str(buf), mode);
 105                 set_type_alignment_bytes(res, 16);
 106                 pmap_insert(types, mode, res);
 107         }
 108         else
 109                 res = e->value;
 110         return res;
 111 }
 112
 113 ir_entity *create_float_const_entity(ir_node *cnst)
 114 {
 115         ia32_isa_t *isa = env_cg->isa;
 116         tarval *key     = get_Const_tarval(cnst);
 117         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 118         ir_entity *res;
 119         ir_graph *rem;
 120
 121         if (e == NULL) {
 122                 tarval  *tv   = key;
 123                 ir_mode *mode = get_tarval_mode(tv);
 124                 ir_type *tp;
 125
 126                 if (! ia32_cg_config.use_sse2) {
 127                         /* try to reduce the mode to produce smaller sized entities */
 128                         if (mode != mode_F) {
 129                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 130                                         mode = mode_F;
 131                                         tv = tarval_convert_to(tv, mode);
 132                                 } else if (mode != mode_D) {
 133                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 134                                                 mode = mode_D;
 135                                                 tv = tarval_convert_to(tv, mode);
 136                                         }
 137                                 }
 138                         }
 139                 }
 140
 141                 if (mode == get_irn_mode(cnst)) {
 142                         /* mode was not changed */
 143                         tp = get_Const_type(cnst);
 144                         if (tp == firm_unknown_type)
 145                                 tp = ia32_get_prim_type(isa->types, mode);
 146                 } else
 147                         tp = ia32_get_prim_type(isa->types, mode);
 148
 149                 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
 150
 151                 set_entity_ld_ident(res, get_entity_ident(res));
 152                 set_entity_visibility(res, visibility_local);
 153                 set_entity_variability(res, variability_constant);
 154                 set_entity_allocation(res, allocation_static);
 155
 156                  /* we create a new entity here: It's initialization must resist on the
 157                     const code irg */
 158                 rem = current_ir_graph;
 159                 current_ir_graph = get_const_code_irg();
 160                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 161                 current_ir_graph = rem;
 162
 163                 pmap_insert(isa->tv_ent, key, res);
 164         } else {
 165                 res = e->value;
 166         }
 167
 168         return res;
 169 }
 170
 171 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 172 {
 173         ir_graph *irg         = current_ir_graph;
 174         ir_node  *start_block = get_irg_start_block(irg);
 175         ir_node  *immediate   = new_rd_ia32_Immediate(NULL, irg, start_block,
 176                                                       symconst, symconst_sign, val);
 177         arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
 178
 179         return immediate;
 180 }
 181
 182 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 183 {
 184         const arch_register_t       *reg = NULL;
 185         int                          c;
 186         size_t                       r;
 187         const arch_register_class_t *cls;
 188
 189         /* TODO: construct a hashmap instead of doing linear search for clobber
 190          * register */
 191         for(c = 0; c < N_CLASSES; ++c) {
 192                 cls = & ia32_reg_classes[c];
 193                 for(r = 0; r < cls->n_regs; ++r) {
 194                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 195                         if(strcmp(temp_reg->name, clobber) == 0
 196                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 197                                 reg = temp_reg;
 198                                 break;
 199                         }
 200                 }
 201                 if(reg != NULL)
 202                         break;
 203         }
 204
 205         return reg;
 206 }
 207
 208 #ifndef NDEBUG
 209 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
 210         ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
 211
 212         lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
 213         obstack_1grow(isa->name_obst, 0);
 214         return obstack_finish(isa->name_obst);
 215 }
 216 #endif /* NDEBUG */
 217
 218 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 219         if(mode == mode_fpcw)
 220                 return 0;
 221         if(get_mode_size_bits(mode) > 32)
 222                 return 0;
 223         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 224 }
 225
 226 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 227                            int is_output)
 228 {
 229         char                         immediate_type     = '\0';
 230         unsigned                     limited            = 0;
 231         const arch_register_class_t *cls                = NULL;
 232         int                          memory_possible       = 0;
 233         int                          all_registers_allowed = 0;
 234         int                          p;
 235         int                          same_as = -1;
 236
 237         memset(constraint, 0, sizeof(constraint[0]));
 238         constraint->same_as = -1;
 239
 240         if(*c == 0) {
 241                 /* a memory constraint: no need to do anything in backend about it
 242                  * (the dependencies are already respected by the memory edge of
 243                  * the node) */
 244                 return;
 245         }
 246
 247         /* TODO: improve error messages with node and source info. (As users can
 248          * easily hit these) */
 249         while(*c != 0) {
 250                 switch(*c) {
 251                 case ' ':
 252                 case '\t':
 253                 case '\n':
 254                         break;
 255
 256                 /* Skip out/in-out marker */
 257                 case '=': break;
 258                 case '+': break;
 259
 260                 case '*':
 261                         ++c;
 262                         break;
 263                 case '#':
 264                         while(*c != 0 && *c != ',')
 265                                 ++c;
 266                         break;
 267
 268                 case 'a':
 269                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 270                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 271                         limited |= 1 << REG_EAX;
 272                         break;
 273                 case 'b':
 274                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 275                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 276                         limited |= 1 << REG_EBX;
 277                         break;
 278                 case 'c':
 279                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 280                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 281                         limited |= 1 << REG_ECX;
 282                         break;
 283                 case 'd':
 284                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 285                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 286                         limited |= 1 << REG_EDX;
 287                         break;
 288                 case 'D':
 289                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 290                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 291                         limited |= 1 << REG_EDI;
 292                         break;
 293                 case 'S':
 294                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 295                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 296                         limited |= 1 << REG_ESI;
 297                         break;
 298                 case 'Q':
 299                 case 'q':
 300                         /* q means lower part of the regs only, this makes no
 301                          * difference to Q for us (we only assign whole registers) */
 302                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 303                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 304                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 305                                    1 << REG_EDX;
 306                         break;
 307                 case 'A':
 308                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 309                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 310                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 311                         break;
 312                 case 'l':
 313                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 314                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 315                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 316                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 317                                    1 << REG_EBP;
 318                         break;
 319
 320                 case 'R':
 321                 case 'r':
 322                 case 'p':
 323                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 324                                 panic("multiple register classes not supported");
 325                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 326                         all_registers_allowed = 1;
 327                         break;
 328
 329                 case 'f':
 330                 case 't':
 331                 case 'u':
 332                         /* TODO: mark values so the x87 simulator knows about t and u */
 333                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 334                                 panic("multiple register classes not supported");
 335                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 336                         all_registers_allowed = 1;
 337                         break;
 338
 339                 case 'Y':
 340                 case 'x':
 341                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 342                                 panic("multiple register classes not supproted");
 343                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 344                         all_registers_allowed = 1;
 345                         break;
 346
 347                 case 'I':
 348                 case 'J':
 349                 case 'K':
 350                 case 'L':
 351                 case 'M':
 352                 case 'N':
 353                 case 'O':
 354                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 355                                 panic("multiple register classes not supported");
 356                         if (immediate_type != '\0')
 357                                 panic("multiple immediate types not supported");
 358                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 359                         immediate_type = *c;
 360                         break;
 361                 case 'n':
 362                 case 'i':
 363                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 364                                 panic("multiple register classes not supported");
 365                         if (immediate_type != '\0')
 366                                 panic("multiple immediate types not supported");
 367                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 368                         immediate_type = 'i';
 369                         break;
 370
 371                 case 'X':
 372                 case 'g':
 373                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 374                                 panic("multiple register classes not supported");
 375                         if (immediate_type != '\0')
 376                                 panic("multiple immediate types not supported");
 377                         immediate_type        = 'i';
 378                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 379                         all_registers_allowed = 1;
 380                         memory_possible       = 1;
 381                         break;
 382
 383                 case '0':
 384                 case '1':
 385                 case '2':
 386                 case '3':
 387                 case '4':
 388                 case '5':
 389                 case '6':
 390                 case '7':
 391                 case '8':
 392                 case '9':
 393                         if (is_output)
 394                                 panic("can only specify same constraint on input");
 395
 396                         sscanf(c, "%d%n", &same_as, &p);
 397                         if(same_as >= 0) {
 398                                 c += p;
 399                                 continue;
 400                         }
 401                         break;
 402
 403                 case 'm':
 404                 case 'o':
 405                 case 'V':
 406                         /* memory constraint no need to do anything in backend about it
 407                          * (the dependencies are already respected by the memory edge of
 408                          * the node) */
 409                         memory_possible = 1;
 410                         break;
 411
 412                 case 'E': /* no float consts yet */
 413                 case 'F': /* no float consts yet */
 414                 case 's': /* makes no sense on x86 */
 415                 case '<': /* no autodecrement on x86 */
 416                 case '>': /* no autoincrement on x86 */
 417                 case 'C': /* sse constant not supported yet */
 418                 case 'G': /* 80387 constant not supported yet */
 419                 case 'y': /* we don't support mmx registers yet */
 420                 case 'Z': /* not available in 32 bit mode */
 421                 case 'e': /* not available in 32 bit mode */
 422                         panic("unsupported asm constraint '%c' found in (%+F)",
 423                               *c, current_ir_graph);
 424                         break;
 425                 default:
 426                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 427                               current_ir_graph);
 428                         break;
 429                 }
 430                 ++c;
 431         }
 432
 433         if(same_as >= 0) {
 434                 if (cls != NULL)
 435                         panic("same as and register constraint not supported");
 436                 if (immediate_type != '\0')
 437                         panic("same as and immediate constraint not supported");
 438         }
 439
 440         if (cls == NULL && same_as < 0) {
 441                 if (!memory_possible)
 442                         panic("no constraint specified for assembler input");
 443         }
 444
 445         constraint->same_as               = same_as;
 446         constraint->cls                   = cls;
 447         constraint->allowed_registers     = limited;
 448         constraint->all_registers_allowed = all_registers_allowed;
 449         constraint->memory_possible       = memory_possible;
 450         constraint->immediate_type        = immediate_type;
 451 }
 452
 453 ir_node *gen_ASM(ir_node *node)
 454 {
 455         ir_graph                   *irg       = current_ir_graph;
 456         ir_node                    *block = NULL;
 457         ir_node                    *new_block = NULL;
 458         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 459         int                         i, arity;
 460         int                         out_idx;
 461         ir_node                   **in;
 462         ir_node                    *new_node;
 463         int                         out_arity;
 464         int                         n_out_constraints;
 465         int                         n_clobbers;
 466         const arch_register_req_t **out_reg_reqs;
 467         const arch_register_req_t **in_reg_reqs;
 468         ia32_asm_reg_t             *register_map;
 469         unsigned                    reg_map_size = 0;
 470         struct obstack             *obst;
 471         const ir_asm_constraint    *in_constraints;
 472         const ir_asm_constraint    *out_constraints;
 473         ident                     **clobbers;
 474         int                         clobbers_flags = 0;
 475         unsigned                    clobber_bits[N_CLASSES];
 476
 477         memset(&clobber_bits, 0, sizeof(clobber_bits));
 478
 479         switch (be_transformer) {
 480         case TRANSFORMER_DEFAULT:
 481                 block     = get_nodes_block(node);
 482                 new_block = be_transform_node(block);
 483                 break;
 484
 485 #ifdef FIRM_GRGEN_BE
 486         case TRANSFORMER_PBQP:
 487         case TRANSFORMER_RAND:
 488                 new_block = get_nodes_block(node);
 489                 break;
 490 #endif
 491
 492         default:
 493                 panic("invalid transformer");
 494         }
 495
 496         /* workaround for lots of buggy code out there as most people think volatile
 497          * asm is enough for everything and forget the flags (linux kernel, etc.)
 498          */
 499         if (get_irn_pinned(node) == op_pin_state_pinned) {
 500                 clobbers_flags = 1;
 501         }
 502
 503         arity = get_irn_arity(node);
 504         in    = alloca(arity * sizeof(in[0]));
 505         memset(in, 0, arity * sizeof(in[0]));
 506
 507         clobbers   = get_ASM_clobbers(node);
 508         n_clobbers = 0;
 509         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 510                 const arch_register_req_t *req;
 511                 const char                *c = get_id_str(clobbers[i]);
 512
 513                 if (strcmp(c, "memory") == 0)
 514                         continue;
 515                 if (strcmp(c, "cc") == 0) {
 516                         clobbers_flags = 1;
 517                         continue;
 518                 }
 519
 520                 req = parse_clobber(c);
 521                 clobber_bits[req->cls->index] |= *req->limited;
 522
 523                 n_clobbers++;
 524         }
 525         n_out_constraints = get_ASM_n_output_constraints(node);
 526         out_arity         = n_out_constraints + n_clobbers;
 527
 528         in_constraints  = get_ASM_input_constraints(node);
 529         out_constraints = get_ASM_output_constraints(node);
 530
 531         /* determine size of register_map */
 532         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 533                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 534                 if (constraint->pos > reg_map_size)
 535                         reg_map_size = constraint->pos;
 536         }
 537         for (i = 0; i < arity; ++i) {
 538                 const ir_asm_constraint   *constraint = &in_constraints[i];
 539                 if(constraint->pos > reg_map_size)
 540                         reg_map_size = constraint->pos;
 541         }
 542         ++reg_map_size;
 543
 544         obst         = get_irg_obstack(irg);
 545         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 546         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 547
 548         /* construct output constraints */
 549         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 550
 551         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 552                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 553                 const char                *c       = get_id_str(constraint->constraint);
 554                 unsigned                   pos        = constraint->pos;
 555                 constraint_t               parsed_constraint;
 556                 const arch_register_req_t *req;
 557
 558                 parse_asm_constraints(&parsed_constraint, c, 1);
 559                 req = make_register_req(&parsed_constraint, n_out_constraints,
 560                                         out_reg_reqs, out_idx);
 561                 out_reg_reqs[out_idx] = req;
 562
 563                 register_map[pos].use_input = 0;
 564                 register_map[pos].valid     = 1;
 565                 register_map[pos].memory    = 0;
 566                 register_map[pos].inout_pos = out_idx;
 567                 register_map[pos].mode      = constraint->mode;
 568         }
 569
 570         /* inputs + input constraints */
 571         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 572         for (i = 0; i < arity; ++i) {
 573                 ir_node                   *pred         = get_irn_n(node, i);
 574                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 575                 ident                     *constr_id    = constraint->constraint;
 576                 const char                *c            = get_id_str(constr_id);
 577                 unsigned                   pos          = constraint->pos;
 578                 int                        is_memory_op = 0;
 579                 ir_node                   *input        = NULL;
 580                 unsigned                   r_clobber_bits;
 581                 constraint_t               parsed_constraint;
 582                 const arch_register_req_t *req;
 583
 584                 parse_asm_constraints(&parsed_constraint, c, 0);
 585                 if (parsed_constraint.cls != NULL) {
 586                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 587                         if (r_clobber_bits != 0) {
 588                                 if (parsed_constraint.all_registers_allowed) {
 589                                         parsed_constraint.all_registers_allowed = 0;
 590                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 591                                                         parsed_constraint.cls,
 592                                                         &parsed_constraint.allowed_registers);
 593                                 }
 594                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 595                         }
 596                 }
 597
 598                 req = make_register_req(&parsed_constraint, n_out_constraints,
 599                                         out_reg_reqs, i);
 600                 in_reg_reqs[i] = req;
 601
 602                 if (parsed_constraint.immediate_type != '\0') {
 603                         char imm_type = parsed_constraint.immediate_type;
 604                         input = try_create_Immediate(pred, imm_type);
 605                 }
 606
 607                 if (input == NULL) {
 608                         ir_node *pred = NULL;
 609                         switch (be_transformer) {
 610                         case TRANSFORMER_DEFAULT:
 611                                 pred  = get_irn_n(node, i);
 612                                 input = be_transform_node(pred);
 613                                 break;
 614
 615 #ifdef FIRM_GRGEN_BE
 616                         case TRANSFORMER_PBQP:
 617                         case TRANSFORMER_RAND:
 618                                 input = get_irn_n(node, i);
 619                                 break;
 620 #endif
 621
 622                         default: panic("invalid transformer");
 623                         }
 624
 625                         if (parsed_constraint.cls == NULL
 626                                         && parsed_constraint.same_as < 0) {
 627                                 is_memory_op = 1;
 628                         } else if(parsed_constraint.memory_possible) {
 629                                 /* TODO: match Load or Load/Store if memory possible is set */
 630                         }
 631                 }
 632                 in[i] = input;
 633
 634                 register_map[pos].use_input = 1;
 635                 register_map[pos].valid     = 1;
 636                 register_map[pos].memory    = is_memory_op;
 637                 register_map[pos].inout_pos = i;
 638                 register_map[pos].mode      = constraint->mode;
 639         }
 640
 641         /* parse clobbers */
 642         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 643                 const char                *c = get_id_str(clobbers[i]);
 644                 const arch_register_req_t *req;
 645
 646                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 647                         continue;
 648
 649                 req = parse_clobber(c);
 650                 out_reg_reqs[out_idx] = req;
 651                 ++out_idx;
 652         }
 653
 654         new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
 655                                    get_ASM_text(node), register_map);
 656
 657         if (arity == 0)
 658                 be_dep_on_frame(new_node);
 659
 660         set_ia32_out_req_all(new_node, out_reg_reqs);
 661         set_ia32_in_req_all(new_node, in_reg_reqs);
 662
 663         SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
 664
 665         return new_node;
 666 }
 667
 668 ir_node *gen_CopyB(ir_node *node) {
 669         ir_node  *block    = NULL;
 670         ir_node  *src      = NULL;
 671         ir_node  *new_src  = NULL;
 672         ir_node  *dst      = NULL;
 673         ir_node  *new_dst  = NULL;
 674         ir_node  *mem      = NULL;
 675         ir_node  *new_mem  = NULL;
 676         ir_node  *res      = NULL;
 677         ir_graph *irg      = current_ir_graph;
 678         dbg_info *dbgi     = get_irn_dbg_info(node);
 679         int      size      = get_type_size_bytes(get_CopyB_type(node));
 680         int      rem;
 681
 682         switch (be_transformer) {
 683                 case TRANSFORMER_DEFAULT:
 684                         block    = be_transform_node(get_nodes_block(node));
 685                         src      = get_CopyB_src(node);
 686                         new_src  = be_transform_node(src);
 687                         dst      = get_CopyB_dst(node);
 688                         new_dst  = be_transform_node(dst);
 689                         mem      = get_CopyB_mem(node);
 690                         new_mem  = be_transform_node(mem);
 691                         break;
 692
 693 #ifdef FIRM_GRGEN_BE
 694                 case TRANSFORMER_PBQP:
 695                 case TRANSFORMER_RAND:
 696                         block    = get_nodes_block(node);
 697                         new_src  = get_CopyB_src(node);
 698                         new_dst  = get_CopyB_dst(node);
 699                         new_mem  = get_CopyB_mem(node);
 700                         break;
 701 #endif
 702
 703                 default: panic("invalid transformer");
 704         }
 705
 706         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 707         /* then we need the size explicitly in ECX.                    */
 708         if (size >= 32 * 4) {
 709                 rem = size & 0x3; /* size % 4 */
 710                 size >>= 2;
 711
 712                 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
 713                 be_dep_on_frame(res);
 714
 715                 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
 716         } else {
 717                 if(size == 0) {
 718                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 719                                    node);
 720                 }
 721                 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
 722         }
 723
 724         SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
 725
 726         return res;
 727 }
 728
 729 ir_node *gen_Proj_tls(ir_node *node) {
 730         ir_node  *block = NULL;
 731         ir_graph *irg   = current_ir_graph;
 732         dbg_info *dbgi  = NULL;
 733         ir_node  *res   = NULL;
 734
 735         switch (be_transformer) {
 736                 case TRANSFORMER_DEFAULT:
 737                         block = be_transform_node(get_nodes_block(node));
 738                         break;
 739
 740 #ifdef FIRM_GRGEN_BE
 741                 case TRANSFORMER_PBQP:
 742                 case TRANSFORMER_RAND:
 743                         block = get_nodes_block(node);
 744                         break;
 745 #endif
 746
 747                 default: panic("invalid transformer");
 748         }
 749
 750         res   = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
 751
 752         return res;
 753 }
 754
 755 ir_node *gen_Unknown(ir_node *node)
 756 {
 757         ir_mode *mode = get_irn_mode(node);
 758
 759         if (mode_is_float(mode)) {
 760                 if (ia32_cg_config.use_sse2) {
 761                         return ia32_new_Unknown_xmm(env_cg);
 762                 } else {
 763                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 764                         ir_graph *irg   = current_ir_graph;
 765                         dbg_info *dbgi  = get_irn_dbg_info(node);
 766                         ir_node  *block = get_irg_start_block(irg);
 767                         ir_node  *ret   = new_rd_ia32_vfldz(dbgi, irg, block);
 768
 769                         be_dep_on_frame(ret);
 770                         return ret;
 771                 }
 772         } else if (ia32_mode_needs_gp_reg(mode)) {
 773                 return ia32_new_Unknown_gp(env_cg);
 774         } else {
 775                 panic("unsupported Unknown-Mode");
 776         }
 777         return NULL;
 778 }
 779
 780 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 781                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 782 {
 783         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 784         int                  same_as = constraint->same_as;
 785         arch_register_req_t *req;
 786
 787         if (same_as >= 0) {
 788                 const arch_register_req_t *other_constr;
 789
 790                 if (same_as >= n_outs)
 791                         panic("invalid output number in same_as constraint");
 792
 793                 other_constr     = out_reqs[same_as];
 794
 795                 req              = obstack_alloc(obst, sizeof(req[0]));
 796                 *req             = *other_constr;
 797                 req->type       |= arch_register_req_type_should_be_same;
 798                 req->other_same  = 1U << pos;
 799
 800                 /* switch constraints. This is because in firm we have same_as
 801                  * constraints on the output constraints while in the gcc asm syntax
 802                  * they are specified on the input constraints */
 803                 out_reqs[same_as] = req;
 804                 return other_constr;
 805         }
 806
 807         /* pure memory ops */
 808         if (constraint->cls == NULL) {
 809                 return &no_register_req;
 810         }
 811
 812         if (constraint->allowed_registers != 0
 813                         && !constraint->all_registers_allowed) {
 814                 unsigned *limited_ptr;
 815
 816                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 817                 memset(req, 0, sizeof(req[0]));
 818                 limited_ptr = (unsigned*) (req+1);
 819
 820                 req->type    = arch_register_req_type_limited;
 821                 *limited_ptr = constraint->allowed_registers;
 822                 req->limited = limited_ptr;
 823         } else {
 824                 req       = obstack_alloc(obst, sizeof(req[0]));
 825                 memset(req, 0, sizeof(req[0]));
 826                 req->type = arch_register_req_type_normal;
 827         }
 828         req->cls = constraint->cls;
 829
 830         return req;
 831 }
 832
 833 const arch_register_req_t *parse_clobber(const char *clobber)
 834 {
 835         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 836         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 837         arch_register_req_t   *req;
 838         unsigned              *limited;
 839
 840         if(reg == NULL) {
 841                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 842         }
 843
 844         assert(reg->index < 32);
 845
 846         limited  = obstack_alloc(obst, sizeof(limited[0]));
 847         *limited = 1 << reg->index;
 848
 849         req          = obstack_alloc(obst, sizeof(req[0]));
 850         memset(req, 0, sizeof(req[0]));
 851         req->type    = arch_register_req_type_limited;
 852         req->cls     = arch_register_get_class(reg);
 853         req->limited = limited;
 854
 855         return req;
 856 }
 857
 858
 859 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 860                        ir_node *const other)
 861 {
 862         if (get_nodes_block(other) != block)
 863                 return 0;
 864
 865         if (is_Sync(other)) {
 866                 int i;
 867
 868                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 869                         ir_node *const pred = get_Sync_pred(other, i);
 870
 871                         if (get_nodes_block(pred) != block)
 872                                 continue;
 873
 874                         /* Do not block ourselves from getting eaten */
 875                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 876                                 continue;
 877
 878                         if (!heights_reachable_in_block(heights, pred, am_candidate))
 879                                 continue;
 880
 881                         return 1;
 882                 }
 883
 884                 return 0;
 885         } else {
 886                 /* Do not block ourselves from getting eaten */
 887                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
 888                         return 0;
 889
 890                 if (!heights_reachable_in_block(heights, other, am_candidate))
 891                         return 0;
 892
 893                 return 1;
 894         }
 895 }
 896
 897 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
 898 {
 899         int          minus         = 0;
 900         tarval      *offset        = NULL;
 901         int          offset_sign   = 0;
 902         long         val = 0;
 903         ir_entity   *symconst_ent  = NULL;
 904         int          symconst_sign = 0;
 905         ir_mode     *mode;
 906         ir_node     *cnst          = NULL;
 907         ir_node     *symconst      = NULL;
 908         ir_node     *new_node;
 909
 910         mode = get_irn_mode(node);
 911         if(!mode_is_int(mode) && !mode_is_reference(mode)) {
 912                 return NULL;
 913         }
 914
 915         if(is_Minus(node)) {
 916                 minus = 1;
 917                 node  = get_Minus_op(node);
 918         }
 919
 920         if(is_Const(node)) {
 921                 cnst        = node;
 922                 symconst    = NULL;
 923                 offset_sign = minus;
 924         } else if(is_SymConst(node)) {
 925                 cnst          = NULL;
 926                 symconst      = node;
 927                 symconst_sign = minus;
 928         } else if(is_Add(node)) {
 929                 ir_node *left  = get_Add_left(node);
 930                 ir_node *right = get_Add_right(node);
 931                 if(is_Const(left) && is_SymConst(right)) {
 932                         cnst          = left;
 933                         symconst      = right;
 934                         symconst_sign = minus;
 935                         offset_sign   = minus;
 936                 } else if(is_SymConst(left) && is_Const(right)) {
 937                         cnst          = right;
 938                         symconst      = left;
 939                         symconst_sign = minus;
 940                         offset_sign   = minus;
 941                 }
 942         } else if(is_Sub(node)) {
 943                 ir_node *left  = get_Sub_left(node);
 944                 ir_node *right = get_Sub_right(node);
 945                 if(is_Const(left) && is_SymConst(right)) {
 946                         cnst          = left;
 947                         symconst      = right;
 948                         symconst_sign = !minus;
 949                         offset_sign   = minus;
 950                 } else if(is_SymConst(left) && is_Const(right)) {
 951                         cnst          = right;
 952                         symconst      = left;
 953                         symconst_sign = minus;
 954                         offset_sign   = !minus;
 955                 }
 956         } else {
 957                 return NULL;
 958         }
 959
 960         if(cnst != NULL) {
 961                 offset = get_Const_tarval(cnst);
 962                 if(tarval_is_long(offset)) {
 963                         val = get_tarval_long(offset);
 964                 } else {
 965                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
 966                                    "long?\n", cnst);
 967                         return NULL;
 968                 }
 969
 970                 if(!check_immediate_constraint(val, immediate_constraint_type))
 971                         return NULL;
 972         }
 973         if(symconst != NULL) {
 974                 if(immediate_constraint_type != 0) {
 975                         /* we need full 32bits for symconsts */
 976                         return NULL;
 977                 }
 978
 979                 /* unfortunately the assembler/linker doesn't support -symconst */
 980                 if(symconst_sign)
 981                         return NULL;
 982
 983                 if(get_SymConst_kind(symconst) != symconst_addr_ent)
 984                         return NULL;
 985                 symconst_ent = get_SymConst_entity(symconst);
 986         }
 987         if(cnst == NULL && symconst == NULL)
 988                 return NULL;
 989
 990         if(offset_sign && offset != NULL) {
 991                 offset = tarval_neg(offset);
 992         }
 993
 994         new_node = create_Immediate(symconst_ent, symconst_sign, val);
 995
 996         return new_node;
 997 }