nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "error.h"
  32 #include "irargs_t.h"
  33 #include "ircons.h"
  34 #include "irprintf.h"
  35 #include "typerep.h"
  36
  37 #include "../betranshlp.h"
  38 #include "../beirg_t.h"
  39
  40 #include "ia32_architecture.h"
  41 #include "ia32_common_transform.h"
  42 #include "ia32_new_nodes.h"
  43
  44 #include "gen_ia32_new_nodes.h"
  45 #include "gen_ia32_regalloc_if.h"
  46
  47 /** hold the current code generator during transformation */
  48 ia32_code_gen_t *env_cg = NULL;
  49
  50 heights_t *heights = NULL;
  51
  52 static const arch_register_req_t no_register_req = {
  53         arch_register_req_type_none,
  54         NULL,                         /* regclass */
  55         NULL,                         /* limit bitset */
  56         0,                            /* same pos */
  57         0                             /* different pos */
  58 };
  59
  60 static int check_immediate_constraint(long val, char immediate_constraint_type)
  61 {
  62         switch (immediate_constraint_type) {
  63                 case 0:
  64                 case 'i': return 1;
  65
  66                 case 'I': return    0 <= val && val <=  31;
  67                 case 'J': return    0 <= val && val <=  63;
  68                 case 'K': return -128 <= val && val <= 127;
  69                 case 'L': return val == 0xff || val == 0xffff;
  70                 case 'M': return    0 <= val && val <=   3;
  71                 case 'N': return    0 <= val && val <= 255;
  72                 case 'O': return    0 <= val && val <= 127;
  73
  74                 default: panic("Invalid immediate constraint found");
  75         }
  76 }
  77
  78 /**
  79  * creates a unique ident by adding a number to a tag
  80  *
  81  * @param tag   the tag string, must contain a %d if a number
  82  *              should be added
  83  */
  84 static ident *unique_id(const char *tag)
  85 {
  86         static unsigned id = 0;
  87         char str[256];
  88
  89         snprintf(str, sizeof(str), tag, ++id);
  90         return new_id_from_str(str);
  91 }
  92
  93 /**
  94  * Get a primitive type for a mode.
  95  */
  96 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  97 {
  98         pmap_entry *e = pmap_find(types, mode);
  99         ir_type *res;
 100
 101         if (! e) {
 102                 char buf[64];
 103                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
 104                 res = new_type_primitive(new_id_from_str(buf), mode);
 105                 set_type_alignment_bytes(res, 16);
 106                 pmap_insert(types, mode, res);
 107         }
 108         else
 109                 res = e->value;
 110         return res;
 111 }
 112
 113 ir_entity *create_float_const_entity(ir_node *cnst)
 114 {
 115         ia32_isa_t *isa = env_cg->isa;
 116         tarval *key     = get_Const_tarval(cnst);
 117         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 118         ir_entity *res;
 119         ir_graph *rem;
 120
 121         if (e == NULL) {
 122                 tarval  *tv   = key;
 123                 ir_mode *mode = get_tarval_mode(tv);
 124                 ir_type *tp;
 125
 126                 if (! ia32_cg_config.use_sse2) {
 127                         /* try to reduce the mode to produce smaller sized entities */
 128                         if (mode != mode_F) {
 129                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 130                                         mode = mode_F;
 131                                         tv = tarval_convert_to(tv, mode);
 132                                 } else if (mode != mode_D) {
 133                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 134                                                 mode = mode_D;
 135                                                 tv = tarval_convert_to(tv, mode);
 136                                         }
 137                                 }
 138                         }
 139                 }
 140
 141                 if (mode == get_irn_mode(cnst)) {
 142                         /* mode was not changed */
 143                         tp = get_Const_type(cnst);
 144                         if (tp == firm_unknown_type)
 145                                 tp = ia32_get_prim_type(isa->types, mode);
 146                 } else
 147                         tp = ia32_get_prim_type(isa->types, mode);
 148
 149                 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
 150
 151                 set_entity_ld_ident(res, get_entity_ident(res));
 152                 set_entity_visibility(res, visibility_local);
 153                 set_entity_variability(res, variability_constant);
 154                 set_entity_allocation(res, allocation_static);
 155
 156                  /* we create a new entity here: It's initialization must resist on the
 157                     const code irg */
 158                 rem = current_ir_graph;
 159                 current_ir_graph = get_const_code_irg();
 160                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 161                 current_ir_graph = rem;
 162
 163                 pmap_insert(isa->tv_ent, key, res);
 164         } else {
 165                 res = e->value;
 166         }
 167
 168         return res;
 169 }
 170
 171 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 172 {
 173         ir_graph *irg         = current_ir_graph;
 174         ir_node  *start_block = get_irg_start_block(irg);
 175         ir_node  *immediate   = new_rd_ia32_Immediate(NULL, irg, start_block,
 176                                                       symconst, symconst_sign, val);
 177         arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
 178
 179         return immediate;
 180 }
 181
 182 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 183 {
 184         const arch_register_t       *reg = NULL;
 185         int                          c;
 186         size_t                       r;
 187         const arch_register_class_t *cls;
 188
 189         /* TODO: construct a hashmap instead of doing linear search for clobber
 190          * register */
 191         for(c = 0; c < N_CLASSES; ++c) {
 192                 cls = & ia32_reg_classes[c];
 193                 for(r = 0; r < cls->n_regs; ++r) {
 194                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 195                         if(strcmp(temp_reg->name, clobber) == 0
 196                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 197                                 reg = temp_reg;
 198                                 break;
 199                         }
 200                 }
 201                 if(reg != NULL)
 202                         break;
 203         }
 204
 205         return reg;
 206 }
 207
 208 #ifndef NDEBUG
 209 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
 210         ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
 211
 212         lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
 213         obstack_1grow(isa->name_obst, 0);
 214         return obstack_finish(isa->name_obst);
 215 }
 216 #endif /* NDEBUG */
 217
 218 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 219         if(mode == mode_fpcw)
 220                 return 0;
 221         if(get_mode_size_bits(mode) > 32)
 222                 return 0;
 223         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 224 }
 225
 226 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 227                            int is_output)
 228 {
 229         asm_constraint_flags_t       flags              = 0;
 230         char                         immediate_type     = '\0';
 231         unsigned                     limited            = 0;
 232         const arch_register_class_t *cls                = NULL;
 233         int                          memory_possible       = 0;
 234         int                          all_registers_allowed = 0;
 235         int                          p;
 236         int                          same_as = -1;
 237
 238         memset(constraint, 0, sizeof(constraint[0]));
 239         constraint->same_as = -1;
 240
 241         if(*c == 0) {
 242                 /* a memory constraint: no need to do anything in backend about it
 243                  * (the dependencies are already respected by the memory edge of
 244                  * the node) */
 245                 return;
 246         }
 247
 248         /* TODO: improve error messages with node and source info. (As users can
 249          * easily hit these) */
 250         while(*c != 0) {
 251                 switch(*c) {
 252                 case ' ':
 253                 case '\t':
 254                 case '\n':
 255                         break;
 256
 257                 case '=':
 258                         flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
 259                                 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
 260                         break;
 261
 262                 case '+':
 263                         flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
 264                                 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
 265                         break;
 266
 267                 case '*':
 268                         ++c;
 269                         break;
 270                 case '#':
 271                         while(*c != 0 && *c != ',')
 272                                 ++c;
 273                         break;
 274
 275                 case 'a':
 276                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 277                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 278                         limited |= 1 << REG_EAX;
 279                         break;
 280                 case 'b':
 281                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 282                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 283                         limited |= 1 << REG_EBX;
 284                         break;
 285                 case 'c':
 286                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 287                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 288                         limited |= 1 << REG_ECX;
 289                         break;
 290                 case 'd':
 291                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 292                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 293                         limited |= 1 << REG_EDX;
 294                         break;
 295                 case 'D':
 296                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 297                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 298                         limited |= 1 << REG_EDI;
 299                         break;
 300                 case 'S':
 301                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 302                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 303                         limited |= 1 << REG_ESI;
 304                         break;
 305                 case 'Q':
 306                 case 'q':
 307                         /* q means lower part of the regs only, this makes no
 308                          * difference to Q for us (we only assign whole registers) */
 309                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 310                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 311                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 312                                    1 << REG_EDX;
 313                         break;
 314                 case 'A':
 315                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 316                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 317                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 318                         break;
 319                 case 'l':
 320                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 321                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 322                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 323                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 324                                    1 << REG_EBP;
 325                         break;
 326
 327                 case 'R':
 328                 case 'r':
 329                 case 'p':
 330                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 331                                 panic("multiple register classes not supported");
 332                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 333                         all_registers_allowed = 1;
 334                         break;
 335
 336                 case 'f':
 337                 case 't':
 338                 case 'u':
 339                         /* TODO: mark values so the x87 simulator knows about t and u */
 340                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 341                                 panic("multiple register classes not supported");
 342                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 343                         all_registers_allowed = 1;
 344                         break;
 345
 346                 case 'Y':
 347                 case 'x':
 348                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 349                                 panic("multiple register classes not supproted");
 350                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 351                         all_registers_allowed = 1;
 352                         break;
 353
 354                 case 'I':
 355                 case 'J':
 356                 case 'K':
 357                 case 'L':
 358                 case 'M':
 359                 case 'N':
 360                 case 'O':
 361                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 362                                 panic("multiple register classes not supported");
 363                         if (immediate_type != '\0')
 364                                 panic("multiple immediate types not supported");
 365                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 366                         immediate_type = *c;
 367                         break;
 368                 case 'n':
 369                 case 'i':
 370                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 371                                 panic("multiple register classes not supported");
 372                         if (immediate_type != '\0')
 373                                 panic("multiple immediate types not supported");
 374                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 375                         immediate_type = 'i';
 376                         break;
 377
 378                 case 'X':
 379                 case 'g':
 380                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 381                                 panic("multiple register classes not supported");
 382                         if (immediate_type != '\0')
 383                                 panic("multiple immediate types not supported");
 384                         immediate_type        = 'i';
 385                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 386                         all_registers_allowed = 1;
 387                         memory_possible       = 1;
 388                         break;
 389
 390                 case '0':
 391                 case '1':
 392                 case '2':
 393                 case '3':
 394                 case '4':
 395                 case '5':
 396                 case '6':
 397                 case '7':
 398                 case '8':
 399                 case '9':
 400                         if (is_output)
 401                                 panic("can only specify same constraint on input");
 402
 403                         sscanf(c, "%d%n", &same_as, &p);
 404                         if(same_as >= 0) {
 405                                 c += p;
 406                                 continue;
 407                         }
 408                         break;
 409
 410                 case 'm':
 411                 case 'o':
 412                 case 'V':
 413                         /* memory constraint no need to do anything in backend about it
 414                          * (the dependencies are already respected by the memory edge of
 415                          * the node) */
 416                         memory_possible = 1;
 417                         break;
 418
 419                 case 'E': /* no float consts yet */
 420                 case 'F': /* no float consts yet */
 421                 case 's': /* makes no sense on x86 */
 422                 case '<': /* no autodecrement on x86 */
 423                 case '>': /* no autoincrement on x86 */
 424                 case 'C': /* sse constant not supported yet */
 425                 case 'G': /* 80387 constant not supported yet */
 426                 case 'y': /* we don't support mmx registers yet */
 427                 case 'Z': /* not available in 32 bit mode */
 428                 case 'e': /* not available in 32 bit mode */
 429                         panic("unsupported asm constraint '%c' found in (%+F)",
 430                               *c, current_ir_graph);
 431                         break;
 432                 default:
 433                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 434                               current_ir_graph);
 435                         break;
 436                 }
 437                 ++c;
 438         }
 439
 440         if(same_as >= 0) {
 441                 if (cls != NULL)
 442                         panic("same as and register constraint not supported");
 443                 if (immediate_type != '\0')
 444                         panic("same as and immediate constraint not supported");
 445         }
 446
 447         if (cls == NULL && same_as < 0) {
 448                 if (!memory_possible)
 449                         panic("no constraint specified for assembler input");
 450         }
 451
 452         constraint->same_as               = same_as;
 453         constraint->cls                   = cls;
 454         constraint->allowed_registers     = limited;
 455         constraint->all_registers_allowed = all_registers_allowed;
 456         constraint->memory_possible       = memory_possible;
 457         constraint->immediate_type        = immediate_type;
 458 }
 459
 460 ir_node *gen_ASM(ir_node *node)
 461 {
 462         ir_graph                   *irg       = current_ir_graph;
 463 #ifdef FIRM_GRGEN_BE
 464         ir_node                    *new_block = get_nodes_block(node);
 465 #else
 466         ir_node                    *block     = get_nodes_block(node);
 467         ir_node                    *new_block = be_transform_node(block);
 468 #endif
 469         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 470         int                         i, arity;
 471         int                         out_idx;
 472         ir_node                   **in;
 473         ir_node                    *new_node;
 474         int                         out_arity;
 475         int                         n_out_constraints;
 476         int                         n_clobbers;
 477         const arch_register_req_t **out_reg_reqs;
 478         const arch_register_req_t **in_reg_reqs;
 479         ia32_asm_reg_t             *register_map;
 480         unsigned                    reg_map_size = 0;
 481         struct obstack             *obst;
 482         const ir_asm_constraint    *in_constraints;
 483         const ir_asm_constraint    *out_constraints;
 484         ident                     **clobbers;
 485         int                         clobbers_flags = 0;
 486         unsigned                    clobber_bits[N_CLASSES];
 487
 488         memset(&clobber_bits, 0, sizeof(clobber_bits));
 489
 490         /* workaround for lots of buggy code out there as most people think volatile
 491          * asm is enough for everything and forget the flags (linux kernel, etc.)
 492          */
 493         if (get_irn_pinned(node) == op_pin_state_pinned) {
 494                 clobbers_flags = 1;
 495         }
 496
 497         arity = get_irn_arity(node);
 498         in    = alloca(arity * sizeof(in[0]));
 499         memset(in, 0, arity * sizeof(in[0]));
 500
 501         clobbers   = get_ASM_clobbers(node);
 502         n_clobbers = 0;
 503         for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
 504                 const arch_register_req_t *req;
 505                 const char                *c = get_id_str(clobbers[i]);
 506
 507                 if (strcmp(c, "memory") == 0)
 508                         continue;
 509                 if (strcmp(c, "cc") == 0) {
 510                         clobbers_flags = 1;
 511                         continue;
 512                 }
 513
 514                 req = parse_clobber(c);
 515                 clobber_bits[req->cls->index] |= *req->limited;
 516
 517                 n_clobbers++;
 518         }
 519         n_out_constraints = get_ASM_n_output_constraints(node);
 520         out_arity         = n_out_constraints + n_clobbers;
 521
 522         in_constraints  = get_ASM_input_constraints(node);
 523         out_constraints = get_ASM_output_constraints(node);
 524
 525         /* determine size of register_map */
 526         for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 527                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 528                 if (constraint->pos > reg_map_size)
 529                         reg_map_size = constraint->pos;
 530         }
 531         for(i = 0; i < arity; ++i) {
 532                 const ir_asm_constraint   *constraint = &in_constraints[i];
 533                 if(constraint->pos > reg_map_size)
 534                         reg_map_size = constraint->pos;
 535         }
 536         ++reg_map_size;
 537
 538         obst         = get_irg_obstack(irg);
 539         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 540         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 541
 542         /* construct output constraints */
 543         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 544
 545         for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 546                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 547                 const char                *c       = get_id_str(constraint->constraint);
 548                 unsigned                   pos        = constraint->pos;
 549                 constraint_t               parsed_constraint;
 550                 const arch_register_req_t *req;
 551
 552                 parse_asm_constraints(&parsed_constraint, c, 1);
 553                 req = make_register_req(&parsed_constraint, n_out_constraints,
 554                                         out_reg_reqs, out_idx);
 555                 out_reg_reqs[out_idx] = req;
 556
 557                 register_map[pos].use_input = 0;
 558                 register_map[pos].valid     = 1;
 559                 register_map[pos].memory    = 0;
 560                 register_map[pos].inout_pos = out_idx;
 561                 register_map[pos].mode      = constraint->mode;
 562         }
 563
 564         /* inputs + input constraints */
 565         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 566         for(i = 0; i < arity; ++i) {
 567                 ir_node                   *pred         = get_irn_n(node, i);
 568                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 569                 ident                     *constr_id    = constraint->constraint;
 570                 const char                *c            = get_id_str(constr_id);
 571                 unsigned                   pos          = constraint->pos;
 572                 int                        is_memory_op = 0;
 573                 ir_node                   *input        = NULL;
 574                 unsigned                   r_clobber_bits;
 575                 constraint_t               parsed_constraint;
 576                 const arch_register_req_t *req;
 577
 578                 parse_asm_constraints(&parsed_constraint, c, 0);
 579                 if (parsed_constraint.cls != NULL) {
 580                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 581                         if (r_clobber_bits != 0) {
 582                                 if (parsed_constraint.all_registers_allowed) {
 583                                         parsed_constraint.all_registers_allowed = 0;
 584                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 585                                                         parsed_constraint.cls,
 586                                                         &parsed_constraint.allowed_registers);
 587                                 }
 588                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 589                         }
 590                 }
 591
 592                 req = make_register_req(&parsed_constraint, n_out_constraints,
 593                                         out_reg_reqs, i);
 594                 in_reg_reqs[i] = req;
 595
 596                 if (parsed_constraint.immediate_type != '\0') {
 597                         char imm_type = parsed_constraint.immediate_type;
 598                         input = try_create_Immediate(pred, imm_type);
 599                 }
 600
 601                 if (input == NULL) {
 602                         ir_node *pred = get_irn_n(node, i);
 603                         input         = be_transform_node(pred);
 604
 605                         if (parsed_constraint.cls == NULL
 606                                         && parsed_constraint.same_as < 0) {
 607                                 is_memory_op = 1;
 608                         } else if(parsed_constraint.memory_possible) {
 609                                 /* TODO: match Load or Load/Store if memory possible is set */
 610                         }
 611                 }
 612                 in[i] = input;
 613
 614                 register_map[pos].use_input = 1;
 615                 register_map[pos].valid     = 1;
 616                 register_map[pos].memory    = is_memory_op;
 617                 register_map[pos].inout_pos = i;
 618                 register_map[pos].mode      = constraint->mode;
 619         }
 620
 621         /* parse clobbers */
 622         for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
 623                 const char                *c = get_id_str(clobbers[i]);
 624                 const arch_register_req_t *req;
 625
 626                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 627                         continue;
 628
 629                 req = parse_clobber(c);
 630                 out_reg_reqs[out_idx] = req;
 631                 ++out_idx;
 632         }
 633
 634         new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
 635                                    get_ASM_text(node), register_map);
 636
 637         set_ia32_out_req_all(new_node, out_reg_reqs);
 638         set_ia32_in_req_all(new_node, in_reg_reqs);
 639
 640         SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
 641
 642         return new_node;
 643 }
 644
 645 ir_node *gen_Unknown(ir_node *node)
 646 {
 647         ir_mode *mode = get_irn_mode(node);
 648
 649         if (mode_is_float(mode)) {
 650                 if (ia32_cg_config.use_sse2) {
 651                         return ia32_new_Unknown_xmm(env_cg);
 652                 } else {
 653                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 654                         ir_graph *irg   = current_ir_graph;
 655                         dbg_info *dbgi  = get_irn_dbg_info(node);
 656                         ir_node  *block = get_irg_start_block(irg);
 657                         ir_node  *ret   = new_rd_ia32_vfldz(dbgi, irg, block);
 658
 659                         /* Const Nodes before the initial IncSP are a bad idea, because
 660                          * they could be spilled and we have no SP ready at that point yet.
 661                          * So add a dependency to the initial frame pointer calculation to
 662                          * avoid that situation.
 663                          */
 664                         add_irn_dep(ret, get_irg_frame(irg));
 665                         return ret;
 666                 }
 667         } else if (ia32_mode_needs_gp_reg(mode)) {
 668                 return ia32_new_Unknown_gp(env_cg);
 669         } else {
 670                 panic("unsupported Unknown-Mode");
 671         }
 672         return NULL;
 673 }
 674
 675 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 676                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 677 {
 678         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 679         int                  same_as = constraint->same_as;
 680         arch_register_req_t *req;
 681
 682         if (same_as >= 0) {
 683                 const arch_register_req_t *other_constr;
 684
 685                 if (same_as >= n_outs)
 686                         panic("invalid output number in same_as constraint");
 687
 688                 other_constr         = out_reqs[same_as];
 689
 690                 req                  = obstack_alloc(obst, sizeof(req[0]));
 691                 req->cls             = other_constr->cls;
 692                 req->type            = arch_register_req_type_should_be_same;
 693                 req->limited         = NULL;
 694                 req->other_same      = 1U << pos;
 695                 req->other_different = 0;
 696
 697                 /* switch constraints. This is because in firm we have same_as
 698                  * constraints on the output constraints while in the gcc asm syntax
 699                  * they are specified on the input constraints */
 700                 out_reqs[same_as] = req;
 701                 return other_constr;
 702         }
 703
 704         /* pure memory ops */
 705         if (constraint->cls == NULL) {
 706                 return &no_register_req;
 707         }
 708
 709         if (constraint->allowed_registers != 0
 710                         && !constraint->all_registers_allowed) {
 711                 unsigned *limited_ptr;
 712
 713                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 714                 memset(req, 0, sizeof(req[0]));
 715                 limited_ptr = (unsigned*) (req+1);
 716
 717                 req->type    = arch_register_req_type_limited;
 718                 *limited_ptr = constraint->allowed_registers;
 719                 req->limited = limited_ptr;
 720         } else {
 721                 req       = obstack_alloc(obst, sizeof(req[0]));
 722                 memset(req, 0, sizeof(req[0]));
 723                 req->type = arch_register_req_type_normal;
 724         }
 725         req->cls = constraint->cls;
 726
 727         return req;
 728 }
 729
 730 const arch_register_req_t *parse_clobber(const char *clobber)
 731 {
 732         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 733         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 734         arch_register_req_t   *req;
 735         unsigned              *limited;
 736
 737         if(reg == NULL) {
 738                 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
 739         }
 740
 741         assert(reg->index < 32);
 742
 743         limited  = obstack_alloc(obst, sizeof(limited[0]));
 744         *limited = 1 << reg->index;
 745
 746         req          = obstack_alloc(obst, sizeof(req[0]));
 747         memset(req, 0, sizeof(req[0]));
 748         req->type    = arch_register_req_type_limited;
 749         req->cls     = arch_register_get_class(reg);
 750         req->limited = limited;
 751
 752         return req;
 753 }
 754
 755 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
 756 {
 757         int          minus         = 0;
 758         tarval      *offset        = NULL;
 759         int          offset_sign   = 0;
 760         long         val = 0;
 761         ir_entity   *symconst_ent  = NULL;
 762         int          symconst_sign = 0;
 763         ir_mode     *mode;
 764         ir_node     *cnst          = NULL;
 765         ir_node     *symconst      = NULL;
 766         ir_node     *new_node;
 767
 768         mode = get_irn_mode(node);
 769         if(!mode_is_int(mode) && !mode_is_reference(mode)) {
 770                 return NULL;
 771         }
 772
 773         if(is_Minus(node)) {
 774                 minus = 1;
 775                 node  = get_Minus_op(node);
 776         }
 777
 778         if(is_Const(node)) {
 779                 cnst        = node;
 780                 symconst    = NULL;
 781                 offset_sign = minus;
 782         } else if(is_SymConst(node)) {
 783                 cnst          = NULL;
 784                 symconst      = node;
 785                 symconst_sign = minus;
 786         } else if(is_Add(node)) {
 787                 ir_node *left  = get_Add_left(node);
 788                 ir_node *right = get_Add_right(node);
 789                 if(is_Const(left) && is_SymConst(right)) {
 790                         cnst          = left;
 791                         symconst      = right;
 792                         symconst_sign = minus;
 793                         offset_sign   = minus;
 794                 } else if(is_SymConst(left) && is_Const(right)) {
 795                         cnst          = right;
 796                         symconst      = left;
 797                         symconst_sign = minus;
 798                         offset_sign   = minus;
 799                 }
 800         } else if(is_Sub(node)) {
 801                 ir_node *left  = get_Sub_left(node);
 802                 ir_node *right = get_Sub_right(node);
 803                 if(is_Const(left) && is_SymConst(right)) {
 804                         cnst          = left;
 805                         symconst      = right;
 806                         symconst_sign = !minus;
 807                         offset_sign   = minus;
 808                 } else if(is_SymConst(left) && is_Const(right)) {
 809                         cnst          = right;
 810                         symconst      = left;
 811                         symconst_sign = minus;
 812                         offset_sign   = !minus;
 813                 }
 814         } else {
 815                 return NULL;
 816         }
 817
 818         if(cnst != NULL) {
 819                 offset = get_Const_tarval(cnst);
 820                 if(tarval_is_long(offset)) {
 821                         val = get_tarval_long(offset);
 822                 } else {
 823                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
 824                                    "long?\n", cnst);
 825                         return NULL;
 826                 }
 827
 828                 if(!check_immediate_constraint(val, immediate_constraint_type))
 829                         return NULL;
 830         }
 831         if(symconst != NULL) {
 832                 if(immediate_constraint_type != 0) {
 833                         /* we need full 32bits for symconsts */
 834                         return NULL;
 835                 }
 836
 837                 /* unfortunately the assembler/linker doesn't support -symconst */
 838                 if(symconst_sign)
 839                         return NULL;
 840
 841                 if(get_SymConst_kind(symconst) != symconst_addr_ent)
 842                         return NULL;
 843                 symconst_ent = get_SymConst_entity(symconst);
 844         }
 845         if(cnst == NULL && symconst == NULL)
 846                 return NULL;
 847
 848         if(offset_sign && offset != NULL) {
 849                 offset = tarval_neg(offset);
 850         }
 851
 852         new_node = create_Immediate(symconst_ent, symconst_sign, val);
 853
 854         return new_node;
 855 }