nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33 #include "bitset.h"
  34
  35 #include "../betranshlp.h"
  36 #include "../beirg.h"
  37 #include "../beabi.h"
  38
  39 #include "ia32_architecture.h"
  40 #include "ia32_common_transform.h"
  41 #include "ia32_new_nodes.h"
  42
  43 #include "gen_ia32_new_nodes.h"
  44 #include "gen_ia32_regalloc_if.h"
  45
  46 /** hold the current code generator during transformation */
  47 ia32_code_gen_t *env_cg = NULL;
  48
  49 heights_t *heights = NULL;
  50
  51 static const arch_register_req_t no_register_req = {
  52         arch_register_req_type_none,
  53         NULL,                         /* regclass */
  54         NULL,                         /* limit bitset */
  55         0,                            /* same pos */
  56         0                             /* different pos */
  57 };
  58
  59 static int check_immediate_constraint(long val, char immediate_constraint_type)
  60 {
  61         switch (immediate_constraint_type) {
  62                 case 0:
  63                 case 'i': return 1;
  64
  65                 case 'I': return    0 <= val && val <=  31;
  66                 case 'J': return    0 <= val && val <=  63;
  67                 case 'K': return -128 <= val && val <= 127;
  68                 case 'L': return val == 0xff || val == 0xffff;
  69                 case 'M': return    0 <= val && val <=   3;
  70                 case 'N': return    0 <= val && val <= 255;
  71                 case 'O': return    0 <= val && val <= 127;
  72
  73                 default: panic("Invalid immediate constraint found");
  74         }
  75 }
  76
  77 /* creates a unique ident by adding a number to a tag */
  78 ident *ia32_unique_id(const char *tag)
  79 {
  80         static unsigned id = 0;
  81         char str[256];
  82
  83         snprintf(str, sizeof(str), tag, ++id);
  84         return new_id_from_str(str);
  85 }
  86
  87 /**
  88  * Get a primitive type for a mode with alignment 16.
  89  */
  90 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  91 {
  92         pmap_entry *e = pmap_find(types, mode);
  93         ir_type *res;
  94
  95         if (! e) {
  96                 res = new_type_primitive(mode);
  97                 if (get_mode_size_bits(mode) >= 80) {
  98                         set_type_alignment_bytes(res, 16);
  99                 }
 100                 pmap_insert(types, mode, res);
 101         }
 102         else
 103                 res = e->value;
 104         return res;
 105 }
 106
 107 ir_entity *create_float_const_entity(ir_node *cnst)
 108 {
 109         ia32_isa_t *isa = env_cg->isa;
 110         tarval *key     = get_Const_tarval(cnst);
 111         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 112         ir_entity *res;
 113         ir_graph *rem;
 114
 115         if (e == NULL) {
 116                 tarval  *tv   = key;
 117                 ir_mode *mode = get_tarval_mode(tv);
 118                 ir_type *tp;
 119
 120                 if (! ia32_cg_config.use_sse2) {
 121                         /* try to reduce the mode to produce smaller sized entities */
 122                         if (mode != mode_F) {
 123                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 124                                         mode = mode_F;
 125                                         tv = tarval_convert_to(tv, mode);
 126                                 } else if (mode != mode_D) {
 127                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 128                                                 mode = mode_D;
 129                                                 tv = tarval_convert_to(tv, mode);
 130                                         }
 131                                 }
 132                         }
 133                 }
 134
 135                 if (mode == get_irn_mode(cnst)) {
 136                         /* mode was not changed */
 137                         tp = get_Const_type(cnst);
 138                         if (tp == firm_unknown_type)
 139                                 tp = ia32_get_prim_type(isa->types, mode);
 140                 } else
 141                         tp = ia32_get_prim_type(isa->types, mode);
 142
 143                 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
 144
 145                 set_entity_ld_ident(res, get_entity_ident(res));
 146                 set_entity_linkage(res, IR_LINKAGE_LOCAL | IR_LINKAGE_CONSTANT);
 147
 148                  /* we create a new entity here: It's initialization must resist on the
 149                     const code irg */
 150                 rem = current_ir_graph;
 151                 current_ir_graph = get_const_code_irg();
 152                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 153                 current_ir_graph = rem;
 154
 155                 pmap_insert(isa->tv_ent, key, res);
 156         } else {
 157                 res = e->value;
 158         }
 159
 160         return res;
 161 }
 162
 163 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 164 {
 165         ir_graph *irg         = current_ir_graph;
 166         ir_node  *start_block = get_irg_start_block(irg);
 167         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 168                         symconst_sign, no_pic_adjust, val);
 169         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 170
 171         return immediate;
 172 }
 173
 174 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 175 {
 176         const arch_register_t       *reg = NULL;
 177         int                          c;
 178         size_t                       r;
 179         const arch_register_class_t *cls;
 180
 181         /* TODO: construct a hashmap instead of doing linear search for clobber
 182          * register */
 183         for(c = 0; c < N_CLASSES; ++c) {
 184                 cls = & ia32_reg_classes[c];
 185                 for(r = 0; r < cls->n_regs; ++r) {
 186                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 187                         if (strcmp(temp_reg->name, clobber) == 0
 188                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 189                                 reg = temp_reg;
 190                                 break;
 191                         }
 192                 }
 193                 if (reg != NULL)
 194                         break;
 195         }
 196
 197         return reg;
 198 }
 199
 200 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 201         if (mode == mode_fpcw)
 202                 return 0;
 203         if (get_mode_size_bits(mode) > 32)
 204                 return 0;
 205         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 206 }
 207
 208 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 209                            int is_output)
 210 {
 211         char                         immediate_type     = '\0';
 212         unsigned                     limited            = 0;
 213         const arch_register_class_t *cls                = NULL;
 214         int                          memory_possible       = 0;
 215         int                          all_registers_allowed = 0;
 216         int                          p;
 217         int                          same_as = -1;
 218
 219         memset(constraint, 0, sizeof(constraint[0]));
 220         constraint->same_as = -1;
 221
 222         if (*c == 0) {
 223                 /* a memory constraint: no need to do anything in backend about it
 224                  * (the dependencies are already respected by the memory edge of
 225                  * the node) */
 226                 return;
 227         }
 228
 229         /* TODO: improve error messages with node and source info. (As users can
 230          * easily hit these) */
 231         while(*c != 0) {
 232                 switch(*c) {
 233                 case ' ':
 234                 case '\t':
 235                 case '\n':
 236                         break;
 237
 238                 /* Skip out/in-out marker */
 239                 case '=': break;
 240                 case '+': break;
 241
 242                 case '&': break;
 243
 244                 case '*':
 245                         ++c;
 246                         break;
 247                 case '#':
 248                         while(*c != 0 && *c != ',')
 249                                 ++c;
 250                         break;
 251
 252                 case 'a':
 253                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 254                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 255                         limited |= 1 << REG_EAX;
 256                         break;
 257                 case 'b':
 258                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 259                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 260                         limited |= 1 << REG_EBX;
 261                         break;
 262                 case 'c':
 263                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 264                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 265                         limited |= 1 << REG_ECX;
 266                         break;
 267                 case 'd':
 268                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 269                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 270                         limited |= 1 << REG_EDX;
 271                         break;
 272                 case 'D':
 273                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 274                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 275                         limited |= 1 << REG_EDI;
 276                         break;
 277                 case 'S':
 278                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 279                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 280                         limited |= 1 << REG_ESI;
 281                         break;
 282                 case 'Q':
 283                 case 'q':
 284                         /* q means lower part of the regs only, this makes no
 285                          * difference to Q for us (we only assign whole registers) */
 286                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 287                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 288                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 289                                    1 << REG_EDX;
 290                         break;
 291                 case 'A':
 292                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 293                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 294                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 295                         break;
 296                 case 'l':
 297                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 298                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 299                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 300                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 301                                    1 << REG_EBP;
 302                         break;
 303
 304                 case 'R':
 305                 case 'r':
 306                 case 'p':
 307                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 308                                 panic("multiple register classes not supported");
 309                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 310                         all_registers_allowed = 1;
 311                         break;
 312
 313                 case 'f':
 314                 case 't':
 315                 case 'u':
 316                         /* TODO: mark values so the x87 simulator knows about t and u */
 317                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 318                                 panic("multiple register classes not supported");
 319                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 320                         all_registers_allowed = 1;
 321                         break;
 322
 323                 case 'Y':
 324                 case 'x':
 325                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 326                                 panic("multiple register classes not supproted");
 327                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 328                         all_registers_allowed = 1;
 329                         break;
 330
 331                 case 'I':
 332                 case 'J':
 333                 case 'K':
 334                 case 'L':
 335                 case 'M':
 336                 case 'N':
 337                 case 'O':
 338                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 339                                 panic("multiple register classes not supported");
 340                         if (immediate_type != '\0')
 341                                 panic("multiple immediate types not supported");
 342                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 343                         immediate_type = *c;
 344                         break;
 345                 case 'n':
 346                 case 'i':
 347                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 348                                 panic("multiple register classes not supported");
 349                         if (immediate_type != '\0')
 350                                 panic("multiple immediate types not supported");
 351                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 352                         immediate_type = 'i';
 353                         break;
 354
 355                 case 'X':
 356                 case 'g':
 357                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 358                                 panic("multiple register classes not supported");
 359                         if (immediate_type != '\0')
 360                                 panic("multiple immediate types not supported");
 361                         immediate_type        = 'i';
 362                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 363                         all_registers_allowed = 1;
 364                         memory_possible       = 1;
 365                         break;
 366
 367                 case '0':
 368                 case '1':
 369                 case '2':
 370                 case '3':
 371                 case '4':
 372                 case '5':
 373                 case '6':
 374                 case '7':
 375                 case '8':
 376                 case '9':
 377                         if (is_output)
 378                                 panic("can only specify same constraint on input");
 379
 380                         sscanf(c, "%d%n", &same_as, &p);
 381                         if (same_as >= 0) {
 382                                 c += p;
 383                                 continue;
 384                         }
 385                         break;
 386
 387                 case 'm':
 388                 case 'o':
 389                 case 'V':
 390                         /* memory constraint no need to do anything in backend about it
 391                          * (the dependencies are already respected by the memory edge of
 392                          * the node) */
 393                         memory_possible = 1;
 394                         break;
 395
 396                 case 'E': /* no float consts yet */
 397                 case 'F': /* no float consts yet */
 398                 case 's': /* makes no sense on x86 */
 399                 case '<': /* no autodecrement on x86 */
 400                 case '>': /* no autoincrement on x86 */
 401                 case 'C': /* sse constant not supported yet */
 402                 case 'G': /* 80387 constant not supported yet */
 403                 case 'y': /* we don't support mmx registers yet */
 404                 case 'Z': /* not available in 32 bit mode */
 405                 case 'e': /* not available in 32 bit mode */
 406                         panic("unsupported asm constraint '%c' found in (%+F)",
 407                               *c, current_ir_graph);
 408                         break;
 409                 default:
 410                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 411                               current_ir_graph);
 412                         break;
 413                 }
 414                 ++c;
 415         }
 416
 417         if (same_as >= 0) {
 418                 if (cls != NULL)
 419                         panic("same as and register constraint not supported");
 420                 if (immediate_type != '\0')
 421                         panic("same as and immediate constraint not supported");
 422         }
 423
 424         if (cls == NULL && same_as < 0) {
 425                 if (!memory_possible)
 426                         panic("no constraint specified for assembler input");
 427         }
 428
 429         constraint->same_as               = same_as;
 430         constraint->cls                   = cls;
 431         constraint->allowed_registers     = limited;
 432         constraint->all_registers_allowed = all_registers_allowed;
 433         constraint->memory_possible       = memory_possible;
 434         constraint->immediate_type        = immediate_type;
 435 }
 436
 437 static bool can_match(const arch_register_req_t *in,
 438                       const arch_register_req_t *out)
 439 {
 440         if (in->cls != out->cls)
 441                 return false;
 442         if ( (in->type & arch_register_req_type_limited) == 0
 443                 || (out->type & arch_register_req_type_limited) == 0 )
 444                 return true;
 445
 446         return (*in->limited & *out->limited) != 0;
 447 }
 448
 449 ir_node *gen_ASM(ir_node *node)
 450 {
 451         ir_node                    *block = NULL;
 452         ir_node                    *new_block = NULL;
 453         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 454         int                         i, arity;
 455         int                         out_idx;
 456         ir_node                   **in;
 457         ir_node                    *new_node;
 458         int                         out_arity;
 459         int                         n_out_constraints;
 460         int                         n_clobbers;
 461         const arch_register_req_t **out_reg_reqs;
 462         const arch_register_req_t **in_reg_reqs;
 463         ia32_asm_reg_t             *register_map;
 464         unsigned                    reg_map_size = 0;
 465         struct obstack             *obst;
 466         const ir_asm_constraint    *in_constraints;
 467         const ir_asm_constraint    *out_constraints;
 468         ident                     **clobbers;
 469         int                         clobbers_flags = 0;
 470         unsigned                    clobber_bits[N_CLASSES];
 471         int                         out_size;
 472         backend_info_t             *info;
 473
 474         memset(&clobber_bits, 0, sizeof(clobber_bits));
 475
 476         switch (be_transformer) {
 477         case TRANSFORMER_DEFAULT:
 478                 block     = get_nodes_block(node);
 479                 new_block = be_transform_node(block);
 480                 break;
 481
 482 #ifdef FIRM_GRGEN_BE
 483         case TRANSFORMER_PBQP:
 484         case TRANSFORMER_RAND:
 485                 new_block = get_nodes_block(node);
 486                 break;
 487 #endif
 488
 489         default:
 490                 panic("invalid transformer");
 491         }
 492
 493         /* workaround for lots of buggy code out there as most people think volatile
 494          * asm is enough for everything and forget the flags (linux kernel, etc.)
 495          */
 496         if (get_irn_pinned(node) == op_pin_state_pinned) {
 497                 clobbers_flags = 1;
 498         }
 499
 500         arity = get_irn_arity(node);
 501         in    = ALLOCANZ(ir_node*, arity);
 502
 503         clobbers   = get_ASM_clobbers(node);
 504         n_clobbers = 0;
 505         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 506                 const arch_register_req_t *req;
 507                 const char                *c = get_id_str(clobbers[i]);
 508
 509                 if (strcmp(c, "memory") == 0)
 510                         continue;
 511                 if (strcmp(c, "cc") == 0) {
 512                         clobbers_flags = 1;
 513                         continue;
 514                 }
 515
 516                 req = parse_clobber(c);
 517                 clobber_bits[req->cls->index] |= *req->limited;
 518
 519                 n_clobbers++;
 520         }
 521         n_out_constraints = get_ASM_n_output_constraints(node);
 522         out_arity         = n_out_constraints + n_clobbers;
 523
 524         in_constraints  = get_ASM_input_constraints(node);
 525         out_constraints = get_ASM_output_constraints(node);
 526
 527         /* determine size of register_map */
 528         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 529                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 530                 if (constraint->pos > reg_map_size)
 531                         reg_map_size = constraint->pos;
 532         }
 533         for (i = 0; i < arity; ++i) {
 534                 const ir_asm_constraint   *constraint = &in_constraints[i];
 535                 if (constraint->pos > reg_map_size)
 536                         reg_map_size = constraint->pos;
 537         }
 538         ++reg_map_size;
 539
 540         obst         = get_irg_obstack(current_ir_graph);
 541         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 542         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 543
 544         /* construct output constraints */
 545         out_size = out_arity + 1;
 546         out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
 547
 548         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 549                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 550                 const char                *c       = get_id_str(constraint->constraint);
 551                 unsigned                   pos        = constraint->pos;
 552                 constraint_t               parsed_constraint;
 553                 const arch_register_req_t *req;
 554
 555                 parse_asm_constraints(&parsed_constraint, c, 1);
 556                 req = make_register_req(&parsed_constraint, n_out_constraints,
 557                                         out_reg_reqs, out_idx);
 558                 out_reg_reqs[out_idx] = req;
 559
 560                 register_map[pos].use_input = 0;
 561                 register_map[pos].valid     = 1;
 562                 register_map[pos].memory    = 0;
 563                 register_map[pos].inout_pos = out_idx;
 564                 register_map[pos].mode      = constraint->mode;
 565         }
 566
 567         /* inputs + input constraints */
 568         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 569         for (i = 0; i < arity; ++i) {
 570                 ir_node                   *pred         = get_irn_n(node, i);
 571                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 572                 ident                     *constr_id    = constraint->constraint;
 573                 const char                *c            = get_id_str(constr_id);
 574                 unsigned                   pos          = constraint->pos;
 575                 int                        is_memory_op = 0;
 576                 ir_node                   *input        = NULL;
 577                 unsigned                   r_clobber_bits;
 578                 constraint_t               parsed_constraint;
 579                 const arch_register_req_t *req;
 580
 581                 parse_asm_constraints(&parsed_constraint, c, 0);
 582                 if (parsed_constraint.cls != NULL) {
 583                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 584                         if (r_clobber_bits != 0) {
 585                                 if (parsed_constraint.all_registers_allowed) {
 586                                         parsed_constraint.all_registers_allowed = 0;
 587                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 588                                                         parsed_constraint.cls,
 589                                                         &parsed_constraint.allowed_registers);
 590                                 }
 591                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 592                         }
 593                 }
 594
 595                 req = make_register_req(&parsed_constraint, n_out_constraints,
 596                                         out_reg_reqs, i);
 597                 in_reg_reqs[i] = req;
 598
 599                 if (parsed_constraint.immediate_type != '\0') {
 600                         char imm_type = parsed_constraint.immediate_type;
 601                         input = try_create_Immediate(pred, imm_type);
 602                 }
 603
 604                 if (input == NULL) {
 605                         ir_node *pred = NULL;
 606                         switch (be_transformer) {
 607                         case TRANSFORMER_DEFAULT:
 608                                 pred  = get_irn_n(node, i);
 609                                 input = be_transform_node(pred);
 610                                 break;
 611
 612 #ifdef FIRM_GRGEN_BE
 613                         case TRANSFORMER_PBQP:
 614                         case TRANSFORMER_RAND:
 615                                 input = get_irn_n(node, i);
 616                                 break;
 617 #endif
 618
 619                         default: panic("invalid transformer");
 620                         }
 621
 622                         if (parsed_constraint.cls == NULL
 623                                         && parsed_constraint.same_as < 0) {
 624                                 is_memory_op = 1;
 625                         } else if (parsed_constraint.memory_possible) {
 626                                 /* TODO: match Load or Load/Store if memory possible is set */
 627                         }
 628                 }
 629                 in[i] = input;
 630
 631                 register_map[pos].use_input = 1;
 632                 register_map[pos].valid     = 1;
 633                 register_map[pos].memory    = is_memory_op;
 634                 register_map[pos].inout_pos = i;
 635                 register_map[pos].mode      = constraint->mode;
 636         }
 637
 638         /* parse clobbers */
 639         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 640                 const char                *c = get_id_str(clobbers[i]);
 641                 const arch_register_req_t *req;
 642
 643                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 644                         continue;
 645
 646                 req = parse_clobber(c);
 647                 out_reg_reqs[out_idx] = req;
 648                 ++out_idx;
 649         }
 650
 651         /* Attempt to make ASM node register pressure faithful.
 652          * (This does not work for complicated cases yet!)
 653          *
 654          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 655          * the smaller list). Then try to match each constraint of the smaller list
 656          * to 1 of the other list. If we can't match it, then we have to add a dummy
 657          * input/output to the other list
 658          *
 659          * FIXME: This is still broken in lots of cases. But at least better than
 660          *        before...
 661          * FIXME: need to do this per register class...
 662          */
 663         if (out_arity <= arity) {
 664                 int       orig_arity = arity;
 665                 int       in_size    = arity;
 666                 int       o;
 667                 bitset_t *used_ins = bitset_alloca(arity);
 668                 for (o = 0; o < out_arity; ++o) {
 669                         int   i;
 670                         const arch_register_req_t *outreq = out_reg_reqs[o];
 671
 672                         if (outreq->cls == NULL) {
 673                                 continue;
 674                         }
 675
 676                         for (i = 0; i < orig_arity; ++i) {
 677                                 const arch_register_req_t *inreq;
 678                                 if (bitset_is_set(used_ins, i))
 679                                         continue;
 680                                 inreq = in_reg_reqs[i];
 681                                 if (!can_match(outreq, inreq))
 682                                         continue;
 683                                 bitset_set(used_ins, i);
 684                                 break;
 685                         }
 686                         /* did we find any match? */
 687                         if (i < orig_arity)
 688                                 continue;
 689
 690                         /* we might need more space in the input arrays */
 691                         if (arity >= in_size) {
 692                                 const arch_register_req_t **new_in_reg_reqs;
 693                                 ir_node             **new_in;
 694
 695                                 in_size *= 2;
 696                                 new_in_reg_reqs
 697                                         = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
 698                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 699                                 new_in = ALLOCANZ(ir_node*, in_size);
 700                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 701
 702                                 in_reg_reqs = new_in_reg_reqs;
 703                                 in          = new_in;
 704                         }
 705
 706                         /* add a new (dummy) input which occupies the register */
 707                         assert(outreq->type & arch_register_req_type_limited);
 708                         in_reg_reqs[arity] = outreq;
 709                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 710                         be_dep_on_frame(in[arity]);
 711                         ++arity;
 712                 }
 713         } else {
 714                 int       i;
 715                 bitset_t *used_outs = bitset_alloca(out_arity);
 716                 int       orig_out_arity = out_arity;
 717                 for (i = 0; i < arity; ++i) {
 718                         int   o;
 719                         const arch_register_req_t *inreq = in_reg_reqs[i];
 720
 721                         if (inreq->cls == NULL) {
 722                                 continue;
 723                         }
 724
 725                         for (o = 0; o < orig_out_arity; ++o) {
 726                                 const arch_register_req_t *outreq;
 727                                 if (bitset_is_set(used_outs, o))
 728                                         continue;
 729                                 outreq = out_reg_reqs[o];
 730                                 if (!can_match(outreq, inreq))
 731                                         continue;
 732                                 bitset_set(used_outs, i);
 733                                 break;
 734                         }
 735                         /* did we find any match? */
 736                         if (o < orig_out_arity)
 737                                 continue;
 738
 739                         /* we might need more space in the output arrays */
 740                         if (out_arity >= out_size) {
 741                                 const arch_register_req_t **new_out_reg_reqs;
 742
 743                                 out_size *= 2;
 744                                 new_out_reg_reqs
 745                                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 746                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 747                                        out_arity * sizeof(new_out_reg_reqs[0]));
 748                                 out_reg_reqs = new_out_reg_reqs;
 749                         }
 750
 751                         /* add a new (dummy) output which occupies the register */
 752                         assert(inreq->type & arch_register_req_type_limited);
 753                         out_reg_reqs[out_arity] = inreq;
 754                         ++out_arity;
 755                 }
 756         }
 757
 758         /* append none register requirement for the memory output */
 759         if (out_arity + 1 >= out_size) {
 760                 const arch_register_req_t **new_out_reg_reqs;
 761
 762                 out_size = out_arity + 1;
 763                 new_out_reg_reqs
 764                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 765                 memcpy(new_out_reg_reqs, out_reg_reqs,
 766                            out_arity * sizeof(new_out_reg_reqs[0]));
 767                 out_reg_reqs = new_out_reg_reqs;
 768         }
 769
 770         /* add a new (dummy) output which occupies the register */
 771         out_reg_reqs[out_arity] = arch_no_register_req;
 772         ++out_arity;
 773
 774         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 775                                    get_ASM_text(node), register_map);
 776
 777         if (arity == 0)
 778                 be_dep_on_frame(new_node);
 779
 780         info = be_get_info(new_node);
 781         for (i = 0; i < out_arity; ++i) {
 782                 info->out_infos[i].req = out_reg_reqs[i];
 783         }
 784         set_ia32_in_req_all(new_node, in_reg_reqs);
 785
 786         SET_IA32_ORIG_NODE(new_node, node);
 787
 788         return new_node;
 789 }
 790
 791 ir_node *gen_CopyB(ir_node *node) {
 792         ir_node  *block    = NULL;
 793         ir_node  *src      = NULL;
 794         ir_node  *new_src  = NULL;
 795         ir_node  *dst      = NULL;
 796         ir_node  *new_dst  = NULL;
 797         ir_node  *mem      = NULL;
 798         ir_node  *new_mem  = NULL;
 799         ir_node  *res      = NULL;
 800         dbg_info *dbgi     = get_irn_dbg_info(node);
 801         int      size      = get_type_size_bytes(get_CopyB_type(node));
 802         int      rem;
 803
 804         switch (be_transformer) {
 805                 case TRANSFORMER_DEFAULT:
 806                         block    = be_transform_node(get_nodes_block(node));
 807                         src      = get_CopyB_src(node);
 808                         new_src  = be_transform_node(src);
 809                         dst      = get_CopyB_dst(node);
 810                         new_dst  = be_transform_node(dst);
 811                         mem      = get_CopyB_mem(node);
 812                         new_mem  = be_transform_node(mem);
 813                         break;
 814
 815 #ifdef FIRM_GRGEN_BE
 816                 case TRANSFORMER_PBQP:
 817                 case TRANSFORMER_RAND:
 818                         block    = get_nodes_block(node);
 819                         new_src  = get_CopyB_src(node);
 820                         new_dst  = get_CopyB_dst(node);
 821                         new_mem  = get_CopyB_mem(node);
 822                         break;
 823 #endif
 824
 825                 default: panic("invalid transformer");
 826         }
 827
 828         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 829         /* then we need the size explicitly in ECX.                    */
 830         if (size >= 32 * 4) {
 831                 rem = size & 0x3; /* size % 4 */
 832                 size >>= 2;
 833
 834                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 835                 be_dep_on_frame(res);
 836
 837                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 838         } else {
 839                 if (size == 0) {
 840                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 841                                    node);
 842                 }
 843                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 844         }
 845
 846         SET_IA32_ORIG_NODE(res, node);
 847
 848         return res;
 849 }
 850
 851 ir_node *gen_Proj_tls(ir_node *node) {
 852         ir_node  *block = NULL;
 853         dbg_info *dbgi  = NULL;
 854         ir_node  *res   = NULL;
 855
 856         switch (be_transformer) {
 857                 case TRANSFORMER_DEFAULT:
 858                         block = be_transform_node(get_nodes_block(node));
 859                         break;
 860
 861 #ifdef FIRM_GRGEN_BE
 862                 case TRANSFORMER_PBQP:
 863                 case TRANSFORMER_RAND:
 864                         block = get_nodes_block(node);
 865                         break;
 866 #endif
 867
 868                 default: panic("invalid transformer");
 869         }
 870
 871         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 872
 873         return res;
 874 }
 875
 876 ir_node *gen_Unknown(ir_node *node)
 877 {
 878         ir_mode *mode = get_irn_mode(node);
 879
 880         if (mode_is_float(mode)) {
 881                 if (ia32_cg_config.use_sse2) {
 882                         return ia32_new_Unknown_xmm(env_cg);
 883                 } else {
 884                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 885                         ir_graph *irg   = current_ir_graph;
 886                         dbg_info *dbgi  = get_irn_dbg_info(node);
 887                         ir_node  *block = get_irg_start_block(irg);
 888                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 889
 890                         be_dep_on_frame(ret);
 891                         return ret;
 892                 }
 893         } else if (ia32_mode_needs_gp_reg(mode)) {
 894                 return ia32_new_Unknown_gp(env_cg);
 895         } else {
 896                 panic("unsupported Unknown-Mode");
 897         }
 898         return NULL;
 899 }
 900
 901 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 902                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 903 {
 904         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 905         int                  same_as = constraint->same_as;
 906         arch_register_req_t *req;
 907
 908         if (same_as >= 0) {
 909                 const arch_register_req_t *other_constr;
 910
 911                 if (same_as >= n_outs)
 912                         panic("invalid output number in same_as constraint");
 913
 914                 other_constr     = out_reqs[same_as];
 915
 916                 req              = obstack_alloc(obst, sizeof(req[0]));
 917                 *req             = *other_constr;
 918                 req->type       |= arch_register_req_type_should_be_same;
 919                 req->other_same  = 1U << pos;
 920
 921                 /* switch constraints. This is because in firm we have same_as
 922                  * constraints on the output constraints while in the gcc asm syntax
 923                  * they are specified on the input constraints */
 924                 out_reqs[same_as] = req;
 925                 return other_constr;
 926         }
 927
 928         /* pure memory ops */
 929         if (constraint->cls == NULL) {
 930                 return &no_register_req;
 931         }
 932
 933         if (constraint->allowed_registers != 0
 934                         && !constraint->all_registers_allowed) {
 935                 unsigned *limited_ptr;
 936
 937                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 938                 memset(req, 0, sizeof(req[0]));
 939                 limited_ptr = (unsigned*) (req+1);
 940
 941                 req->type    = arch_register_req_type_limited;
 942                 *limited_ptr = constraint->allowed_registers;
 943                 req->limited = limited_ptr;
 944         } else {
 945                 req       = obstack_alloc(obst, sizeof(req[0]));
 946                 memset(req, 0, sizeof(req[0]));
 947                 req->type = arch_register_req_type_normal;
 948         }
 949         req->cls = constraint->cls;
 950
 951         return req;
 952 }
 953
 954 const arch_register_req_t *parse_clobber(const char *clobber)
 955 {
 956         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 957         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 958         arch_register_req_t   *req;
 959         unsigned              *limited;
 960
 961         if (reg == NULL) {
 962                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 963         }
 964
 965         assert(reg->index < 32);
 966
 967         limited  = obstack_alloc(obst, sizeof(limited[0]));
 968         *limited = 1 << reg->index;
 969
 970         req          = obstack_alloc(obst, sizeof(req[0]));
 971         memset(req, 0, sizeof(req[0]));
 972         req->type    = arch_register_req_type_limited;
 973         req->cls     = arch_register_get_class(reg);
 974         req->limited = limited;
 975
 976         return req;
 977 }
 978
 979
 980 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 981                        ir_node *const other)
 982 {
 983         if (get_nodes_block(other) != block)
 984                 return 0;
 985
 986         if (is_Sync(other)) {
 987                 int i;
 988
 989                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 990                         ir_node *const pred = get_Sync_pred(other, i);
 991
 992                         if (get_nodes_block(pred) != block)
 993                                 continue;
 994
 995                         /* Do not block ourselves from getting eaten */
 996                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
 997                                 continue;
 998
 999                         if (!heights_reachable_in_block(heights, pred, am_candidate))
1000                                 continue;
1001
1002                         return 1;
1003                 }
1004
1005                 return 0;
1006         } else {
1007                 /* Do not block ourselves from getting eaten */
1008                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
1009                         return 0;
1010
1011                 if (!heights_reachable_in_block(heights, other, am_candidate))
1012                         return 0;
1013
1014                 return 1;
1015         }
1016 }
1017
1018 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
1019 {
1020         int          minus         = 0;
1021         tarval      *offset        = NULL;
1022         int          offset_sign   = 0;
1023         long         val = 0;
1024         ir_entity   *symconst_ent  = NULL;
1025         int          symconst_sign = 0;
1026         ir_mode     *mode;
1027         ir_node     *cnst          = NULL;
1028         ir_node     *symconst      = NULL;
1029         ir_node     *new_node;
1030
1031         mode = get_irn_mode(node);
1032         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
1033                 return NULL;
1034         }
1035
1036         if (is_Minus(node)) {
1037                 minus = 1;
1038                 node  = get_Minus_op(node);
1039         }
1040
1041         if (is_Const(node)) {
1042                 cnst        = node;
1043                 symconst    = NULL;
1044                 offset_sign = minus;
1045         } else if (is_SymConst(node)) {
1046                 cnst          = NULL;
1047                 symconst      = node;
1048                 symconst_sign = minus;
1049         } else if (is_Add(node)) {
1050                 ir_node *left  = get_Add_left(node);
1051                 ir_node *right = get_Add_right(node);
1052                 if (is_Const(left) && is_SymConst(right)) {
1053                         cnst          = left;
1054                         symconst      = right;
1055                         symconst_sign = minus;
1056                         offset_sign   = minus;
1057                 } else if (is_SymConst(left) && is_Const(right)) {
1058                         cnst          = right;
1059                         symconst      = left;
1060                         symconst_sign = minus;
1061                         offset_sign   = minus;
1062                 }
1063         } else if (is_Sub(node)) {
1064                 ir_node *left  = get_Sub_left(node);
1065                 ir_node *right = get_Sub_right(node);
1066                 if (is_Const(left) && is_SymConst(right)) {
1067                         cnst          = left;
1068                         symconst      = right;
1069                         symconst_sign = !minus;
1070                         offset_sign   = minus;
1071                 } else if (is_SymConst(left) && is_Const(right)) {
1072                         cnst          = right;
1073                         symconst      = left;
1074                         symconst_sign = minus;
1075                         offset_sign   = !minus;
1076                 }
1077         } else {
1078                 return NULL;
1079         }
1080
1081         if (cnst != NULL) {
1082                 offset = get_Const_tarval(cnst);
1083                 if (tarval_is_long(offset)) {
1084                         val = get_tarval_long(offset);
1085                 } else {
1086                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
1087                                    "long?\n", cnst);
1088                         return NULL;
1089                 }
1090
1091                 if (!check_immediate_constraint(val, immediate_constraint_type))
1092                         return NULL;
1093         }
1094         if (symconst != NULL) {
1095                 if (immediate_constraint_type != 0) {
1096                         /* we need full 32bits for symconsts */
1097                         return NULL;
1098                 }
1099
1100                 /* unfortunately the assembler/linker doesn't support -symconst */
1101                 if (symconst_sign)
1102                         return NULL;
1103
1104                 if (get_SymConst_kind(symconst) != symconst_addr_ent)
1105                         return NULL;
1106                 symconst_ent = get_SymConst_entity(symconst);
1107         }
1108         if (cnst == NULL && symconst == NULL)
1109                 return NULL;
1110
1111         if (offset_sign && offset != NULL) {
1112                 offset = tarval_neg(offset);
1113         }
1114
1115         new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val);
1116
1117         return new_node;
1118 }