nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #include "config.h"
  28
  29 #include "error.h"
  30 #include "ircons.h"
  31 #include "irprintf.h"
  32 #include "typerep.h"
  33 #include "bitset.h"
  34
  35 #include "../betranshlp.h"
  36 #include "../beirg.h"
  37 #include "../beabi.h"
  38
  39 #include "ia32_architecture.h"
  40 #include "ia32_common_transform.h"
  41 #include "ia32_new_nodes.h"
  42
  43 #include "gen_ia32_new_nodes.h"
  44 #include "gen_ia32_regalloc_if.h"
  45
  46 /** hold the current code generator during transformation */
  47 ia32_code_gen_t *env_cg = NULL;
  48
  49 heights_t *heights = NULL;
  50
  51 static const arch_register_req_t no_register_req = {
  52         arch_register_req_type_none,
  53         NULL,                         /* regclass */
  54         NULL,                         /* limit bitset */
  55         0,                            /* same pos */
  56         0                             /* different pos */
  57 };
  58
  59 static int check_immediate_constraint(long val, char immediate_constraint_type)
  60 {
  61         switch (immediate_constraint_type) {
  62                 case 0:
  63                 case 'i': return 1;
  64
  65                 case 'I': return    0 <= val && val <=  31;
  66                 case 'J': return    0 <= val && val <=  63;
  67                 case 'K': return -128 <= val && val <= 127;
  68                 case 'L': return val == 0xff || val == 0xffff;
  69                 case 'M': return    0 <= val && val <=   3;
  70                 case 'N': return    0 <= val && val <= 255;
  71                 case 'O': return    0 <= val && val <= 127;
  72
  73                 default: panic("Invalid immediate constraint found");
  74         }
  75 }
  76
  77 /* creates a unique ident by adding a number to a tag */
  78 ident *ia32_unique_id(const char *tag)
  79 {
  80         static unsigned id = 0;
  81         char str[256];
  82
  83         snprintf(str, sizeof(str), tag, ++id);
  84         return new_id_from_str(str);
  85 }
  86
  87 /**
  88  * Get a primitive type for a mode with alignment 16.
  89  */
  90 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  91 {
  92         pmap_entry *e = pmap_find(types, mode);
  93         ir_type *res;
  94
  95         if (! e) {
  96                 char buf[64];
  97                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
  98                 res = new_type_primitive(new_id_from_str(buf), mode);
  99                 if (get_mode_size_bits(mode) >= 80) {
 100                         set_type_alignment_bytes(res, 16);
 101                 }
 102                 pmap_insert(types, mode, res);
 103         }
 104         else
 105                 res = e->value;
 106         return res;
 107 }
 108
 109 ir_entity *create_float_const_entity(ir_node *cnst)
 110 {
 111         ia32_isa_t *isa = env_cg->isa;
 112         tarval *key     = get_Const_tarval(cnst);
 113         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 114         ir_entity *res;
 115         ir_graph *rem;
 116
 117         if (e == NULL) {
 118                 tarval  *tv   = key;
 119                 ir_mode *mode = get_tarval_mode(tv);
 120                 ir_type *tp;
 121
 122                 if (! ia32_cg_config.use_sse2) {
 123                         /* try to reduce the mode to produce smaller sized entities */
 124                         if (mode != mode_F) {
 125                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 126                                         mode = mode_F;
 127                                         tv = tarval_convert_to(tv, mode);
 128                                 } else if (mode != mode_D) {
 129                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 130                                                 mode = mode_D;
 131                                                 tv = tarval_convert_to(tv, mode);
 132                                         }
 133                                 }
 134                         }
 135                 }
 136
 137                 if (mode == get_irn_mode(cnst)) {
 138                         /* mode was not changed */
 139                         tp = get_Const_type(cnst);
 140                         if (tp == firm_unknown_type)
 141                                 tp = ia32_get_prim_type(isa->types, mode);
 142                 } else
 143                         tp = ia32_get_prim_type(isa->types, mode);
 144
 145                 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
 146
 147                 set_entity_ld_ident(res, get_entity_ident(res));
 148                 set_entity_visibility(res, visibility_local);
 149                 set_entity_variability(res, variability_constant);
 150                 set_entity_allocation(res, allocation_static);
 151
 152                  /* we create a new entity here: It's initialization must resist on the
 153                     const code irg */
 154                 rem = current_ir_graph;
 155                 current_ir_graph = get_const_code_irg();
 156                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 157                 current_ir_graph = rem;
 158
 159                 pmap_insert(isa->tv_ent, key, res);
 160         } else {
 161                 res = e->value;
 162         }
 163
 164         return res;
 165 }
 166
 167 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 168 {
 169         ir_graph *irg         = current_ir_graph;
 170         ir_node  *start_block = get_irg_start_block(irg);
 171         ir_node  *immediate   = new_bd_ia32_Immediate(NULL, start_block, symconst,
 172                         symconst_sign, no_pic_adjust, val);
 173         arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
 174
 175         return immediate;
 176 }
 177
 178 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 179 {
 180         const arch_register_t       *reg = NULL;
 181         int                          c;
 182         size_t                       r;
 183         const arch_register_class_t *cls;
 184
 185         /* TODO: construct a hashmap instead of doing linear search for clobber
 186          * register */
 187         for(c = 0; c < N_CLASSES; ++c) {
 188                 cls = & ia32_reg_classes[c];
 189                 for(r = 0; r < cls->n_regs; ++r) {
 190                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 191                         if (strcmp(temp_reg->name, clobber) == 0
 192                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 193                                 reg = temp_reg;
 194                                 break;
 195                         }
 196                 }
 197                 if (reg != NULL)
 198                         break;
 199         }
 200
 201         return reg;
 202 }
 203
 204 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 205         if (mode == mode_fpcw)
 206                 return 0;
 207         if (get_mode_size_bits(mode) > 32)
 208                 return 0;
 209         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 210 }
 211
 212 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 213                            int is_output)
 214 {
 215         char                         immediate_type     = '\0';
 216         unsigned                     limited            = 0;
 217         const arch_register_class_t *cls                = NULL;
 218         int                          memory_possible       = 0;
 219         int                          all_registers_allowed = 0;
 220         int                          p;
 221         int                          same_as = -1;
 222
 223         memset(constraint, 0, sizeof(constraint[0]));
 224         constraint->same_as = -1;
 225
 226         if (*c == 0) {
 227                 /* a memory constraint: no need to do anything in backend about it
 228                  * (the dependencies are already respected by the memory edge of
 229                  * the node) */
 230                 return;
 231         }
 232
 233         /* TODO: improve error messages with node and source info. (As users can
 234          * easily hit these) */
 235         while(*c != 0) {
 236                 switch(*c) {
 237                 case ' ':
 238                 case '\t':
 239                 case '\n':
 240                         break;
 241
 242                 /* Skip out/in-out marker */
 243                 case '=': break;
 244                 case '+': break;
 245
 246                 case '&': break;
 247
 248                 case '*':
 249                         ++c;
 250                         break;
 251                 case '#':
 252                         while(*c != 0 && *c != ',')
 253                                 ++c;
 254                         break;
 255
 256                 case 'a':
 257                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 258                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 259                         limited |= 1 << REG_EAX;
 260                         break;
 261                 case 'b':
 262                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 263                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 264                         limited |= 1 << REG_EBX;
 265                         break;
 266                 case 'c':
 267                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 268                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 269                         limited |= 1 << REG_ECX;
 270                         break;
 271                 case 'd':
 272                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 273                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 274                         limited |= 1 << REG_EDX;
 275                         break;
 276                 case 'D':
 277                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 278                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 279                         limited |= 1 << REG_EDI;
 280                         break;
 281                 case 'S':
 282                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 283                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 284                         limited |= 1 << REG_ESI;
 285                         break;
 286                 case 'Q':
 287                 case 'q':
 288                         /* q means lower part of the regs only, this makes no
 289                          * difference to Q for us (we only assign whole registers) */
 290                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 291                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 292                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 293                                    1 << REG_EDX;
 294                         break;
 295                 case 'A':
 296                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 297                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 298                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 299                         break;
 300                 case 'l':
 301                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 302                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 303                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 304                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 305                                    1 << REG_EBP;
 306                         break;
 307
 308                 case 'R':
 309                 case 'r':
 310                 case 'p':
 311                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 312                                 panic("multiple register classes not supported");
 313                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 314                         all_registers_allowed = 1;
 315                         break;
 316
 317                 case 'f':
 318                 case 't':
 319                 case 'u':
 320                         /* TODO: mark values so the x87 simulator knows about t and u */
 321                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 322                                 panic("multiple register classes not supported");
 323                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 324                         all_registers_allowed = 1;
 325                         break;
 326
 327                 case 'Y':
 328                 case 'x':
 329                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 330                                 panic("multiple register classes not supproted");
 331                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 332                         all_registers_allowed = 1;
 333                         break;
 334
 335                 case 'I':
 336                 case 'J':
 337                 case 'K':
 338                 case 'L':
 339                 case 'M':
 340                 case 'N':
 341                 case 'O':
 342                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 343                                 panic("multiple register classes not supported");
 344                         if (immediate_type != '\0')
 345                                 panic("multiple immediate types not supported");
 346                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 347                         immediate_type = *c;
 348                         break;
 349                 case 'n':
 350                 case 'i':
 351                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 352                                 panic("multiple register classes not supported");
 353                         if (immediate_type != '\0')
 354                                 panic("multiple immediate types not supported");
 355                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 356                         immediate_type = 'i';
 357                         break;
 358
 359                 case 'X':
 360                 case 'g':
 361                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 362                                 panic("multiple register classes not supported");
 363                         if (immediate_type != '\0')
 364                                 panic("multiple immediate types not supported");
 365                         immediate_type        = 'i';
 366                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 367                         all_registers_allowed = 1;
 368                         memory_possible       = 1;
 369                         break;
 370
 371                 case '0':
 372                 case '1':
 373                 case '2':
 374                 case '3':
 375                 case '4':
 376                 case '5':
 377                 case '6':
 378                 case '7':
 379                 case '8':
 380                 case '9':
 381                         if (is_output)
 382                                 panic("can only specify same constraint on input");
 383
 384                         sscanf(c, "%d%n", &same_as, &p);
 385                         if (same_as >= 0) {
 386                                 c += p;
 387                                 continue;
 388                         }
 389                         break;
 390
 391                 case 'm':
 392                 case 'o':
 393                 case 'V':
 394                         /* memory constraint no need to do anything in backend about it
 395                          * (the dependencies are already respected by the memory edge of
 396                          * the node) */
 397                         memory_possible = 1;
 398                         break;
 399
 400                 case 'E': /* no float consts yet */
 401                 case 'F': /* no float consts yet */
 402                 case 's': /* makes no sense on x86 */
 403                 case '<': /* no autodecrement on x86 */
 404                 case '>': /* no autoincrement on x86 */
 405                 case 'C': /* sse constant not supported yet */
 406                 case 'G': /* 80387 constant not supported yet */
 407                 case 'y': /* we don't support mmx registers yet */
 408                 case 'Z': /* not available in 32 bit mode */
 409                 case 'e': /* not available in 32 bit mode */
 410                         panic("unsupported asm constraint '%c' found in (%+F)",
 411                               *c, current_ir_graph);
 412                         break;
 413                 default:
 414                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 415                               current_ir_graph);
 416                         break;
 417                 }
 418                 ++c;
 419         }
 420
 421         if (same_as >= 0) {
 422                 if (cls != NULL)
 423                         panic("same as and register constraint not supported");
 424                 if (immediate_type != '\0')
 425                         panic("same as and immediate constraint not supported");
 426         }
 427
 428         if (cls == NULL && same_as < 0) {
 429                 if (!memory_possible)
 430                         panic("no constraint specified for assembler input");
 431         }
 432
 433         constraint->same_as               = same_as;
 434         constraint->cls                   = cls;
 435         constraint->allowed_registers     = limited;
 436         constraint->all_registers_allowed = all_registers_allowed;
 437         constraint->memory_possible       = memory_possible;
 438         constraint->immediate_type        = immediate_type;
 439 }
 440
 441 static bool can_match(const arch_register_req_t *in,
 442                       const arch_register_req_t *out)
 443 {
 444         if (in->cls != out->cls)
 445                 return false;
 446         if ( (in->type & arch_register_req_type_limited) == 0
 447                 || (out->type & arch_register_req_type_limited) == 0 )
 448                 return true;
 449
 450         return (*in->limited & *out->limited) != 0;
 451 }
 452
 453 ir_node *gen_ASM(ir_node *node)
 454 {
 455         ir_node                    *block = NULL;
 456         ir_node                    *new_block = NULL;
 457         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 458         int                         i, arity;
 459         int                         out_idx;
 460         ir_node                   **in;
 461         ir_node                    *new_node;
 462         int                         out_arity;
 463         int                         n_out_constraints;
 464         int                         n_clobbers;
 465         const arch_register_req_t **out_reg_reqs;
 466         const arch_register_req_t **in_reg_reqs;
 467         ia32_asm_reg_t             *register_map;
 468         unsigned                    reg_map_size = 0;
 469         struct obstack             *obst;
 470         const ir_asm_constraint    *in_constraints;
 471         const ir_asm_constraint    *out_constraints;
 472         ident                     **clobbers;
 473         int                         clobbers_flags = 0;
 474         unsigned                    clobber_bits[N_CLASSES];
 475         int                         out_size;
 476         backend_info_t             *info;
 477
 478         memset(&clobber_bits, 0, sizeof(clobber_bits));
 479
 480         switch (be_transformer) {
 481         case TRANSFORMER_DEFAULT:
 482                 block     = get_nodes_block(node);
 483                 new_block = be_transform_node(block);
 484                 break;
 485
 486 #ifdef FIRM_GRGEN_BE
 487         case TRANSFORMER_PBQP:
 488         case TRANSFORMER_RAND:
 489                 new_block = get_nodes_block(node);
 490                 break;
 491 #endif
 492
 493         default:
 494                 panic("invalid transformer");
 495         }
 496
 497         /* workaround for lots of buggy code out there as most people think volatile
 498          * asm is enough for everything and forget the flags (linux kernel, etc.)
 499          */
 500         if (get_irn_pinned(node) == op_pin_state_pinned) {
 501                 clobbers_flags = 1;
 502         }
 503
 504         arity = get_irn_arity(node);
 505         in    = ALLOCANZ(ir_node*, arity);
 506
 507         clobbers   = get_ASM_clobbers(node);
 508         n_clobbers = 0;
 509         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 510                 const arch_register_req_t *req;
 511                 const char                *c = get_id_str(clobbers[i]);
 512
 513                 if (strcmp(c, "memory") == 0)
 514                         continue;
 515                 if (strcmp(c, "cc") == 0) {
 516                         clobbers_flags = 1;
 517                         continue;
 518                 }
 519
 520                 req = parse_clobber(c);
 521                 clobber_bits[req->cls->index] |= *req->limited;
 522
 523                 n_clobbers++;
 524         }
 525         n_out_constraints = get_ASM_n_output_constraints(node);
 526         out_arity         = n_out_constraints + n_clobbers;
 527
 528         in_constraints  = get_ASM_input_constraints(node);
 529         out_constraints = get_ASM_output_constraints(node);
 530
 531         /* determine size of register_map */
 532         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 533                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 534                 if (constraint->pos > reg_map_size)
 535                         reg_map_size = constraint->pos;
 536         }
 537         for (i = 0; i < arity; ++i) {
 538                 const ir_asm_constraint   *constraint = &in_constraints[i];
 539                 if (constraint->pos > reg_map_size)
 540                         reg_map_size = constraint->pos;
 541         }
 542         ++reg_map_size;
 543
 544         obst         = get_irg_obstack(current_ir_graph);
 545         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 546         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 547
 548         /* construct output constraints */
 549         out_size = out_arity + 1;
 550         out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
 551
 552         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 553                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 554                 const char                *c       = get_id_str(constraint->constraint);
 555                 unsigned                   pos        = constraint->pos;
 556                 constraint_t               parsed_constraint;
 557                 const arch_register_req_t *req;
 558
 559                 parse_asm_constraints(&parsed_constraint, c, 1);
 560                 req = make_register_req(&parsed_constraint, n_out_constraints,
 561                                         out_reg_reqs, out_idx);
 562                 out_reg_reqs[out_idx] = req;
 563
 564                 register_map[pos].use_input = 0;
 565                 register_map[pos].valid     = 1;
 566                 register_map[pos].memory    = 0;
 567                 register_map[pos].inout_pos = out_idx;
 568                 register_map[pos].mode      = constraint->mode;
 569         }
 570
 571         /* inputs + input constraints */
 572         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 573         for (i = 0; i < arity; ++i) {
 574                 ir_node                   *pred         = get_irn_n(node, i);
 575                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 576                 ident                     *constr_id    = constraint->constraint;
 577                 const char                *c            = get_id_str(constr_id);
 578                 unsigned                   pos          = constraint->pos;
 579                 int                        is_memory_op = 0;
 580                 ir_node                   *input        = NULL;
 581                 unsigned                   r_clobber_bits;
 582                 constraint_t               parsed_constraint;
 583                 const arch_register_req_t *req;
 584
 585                 parse_asm_constraints(&parsed_constraint, c, 0);
 586                 if (parsed_constraint.cls != NULL) {
 587                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 588                         if (r_clobber_bits != 0) {
 589                                 if (parsed_constraint.all_registers_allowed) {
 590                                         parsed_constraint.all_registers_allowed = 0;
 591                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 592                                                         parsed_constraint.cls,
 593                                                         &parsed_constraint.allowed_registers);
 594                                 }
 595                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 596                         }
 597                 }
 598
 599                 req = make_register_req(&parsed_constraint, n_out_constraints,
 600                                         out_reg_reqs, i);
 601                 in_reg_reqs[i] = req;
 602
 603                 if (parsed_constraint.immediate_type != '\0') {
 604                         char imm_type = parsed_constraint.immediate_type;
 605                         input = try_create_Immediate(pred, imm_type);
 606                 }
 607
 608                 if (input == NULL) {
 609                         ir_node *pred = NULL;
 610                         switch (be_transformer) {
 611                         case TRANSFORMER_DEFAULT:
 612                                 pred  = get_irn_n(node, i);
 613                                 input = be_transform_node(pred);
 614                                 break;
 615
 616 #ifdef FIRM_GRGEN_BE
 617                         case TRANSFORMER_PBQP:
 618                         case TRANSFORMER_RAND:
 619                                 input = get_irn_n(node, i);
 620                                 break;
 621 #endif
 622
 623                         default: panic("invalid transformer");
 624                         }
 625
 626                         if (parsed_constraint.cls == NULL
 627                                         && parsed_constraint.same_as < 0) {
 628                                 is_memory_op = 1;
 629                         } else if (parsed_constraint.memory_possible) {
 630                                 /* TODO: match Load or Load/Store if memory possible is set */
 631                         }
 632                 }
 633                 in[i] = input;
 634
 635                 register_map[pos].use_input = 1;
 636                 register_map[pos].valid     = 1;
 637                 register_map[pos].memory    = is_memory_op;
 638                 register_map[pos].inout_pos = i;
 639                 register_map[pos].mode      = constraint->mode;
 640         }
 641
 642         /* parse clobbers */
 643         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 644                 const char                *c = get_id_str(clobbers[i]);
 645                 const arch_register_req_t *req;
 646
 647                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 648                         continue;
 649
 650                 req = parse_clobber(c);
 651                 out_reg_reqs[out_idx] = req;
 652                 ++out_idx;
 653         }
 654
 655         /* Attempt to make ASM node register pressure faithful.
 656          * (This does not work for complicated cases yet!)
 657          *
 658          * Algorithm: Check if there are fewer inputs or outputs (I will call this
 659          * the smaller list). Then try to match each constraint of the smaller list
 660          * to 1 of the other list. If we can't match it, then we have to add a dummy
 661          * input/output to the other list
 662          *
 663          * FIXME: This is still broken in lots of cases. But at least better than
 664          *        before...
 665          * FIXME: need to do this per register class...
 666          */
 667         if (out_arity <= arity) {
 668                 int       orig_arity = arity;
 669                 int       in_size    = arity;
 670                 int       o;
 671                 bitset_t *used_ins = bitset_alloca(arity);
 672                 for (o = 0; o < out_arity; ++o) {
 673                         int   i;
 674                         const arch_register_req_t *outreq = out_reg_reqs[o];
 675
 676                         if (outreq->cls == NULL) {
 677                                 continue;
 678                         }
 679
 680                         for (i = 0; i < orig_arity; ++i) {
 681                                 const arch_register_req_t *inreq;
 682                                 if (bitset_is_set(used_ins, i))
 683                                         continue;
 684                                 inreq = in_reg_reqs[i];
 685                                 if (!can_match(outreq, inreq))
 686                                         continue;
 687                                 bitset_set(used_ins, i);
 688                                 break;
 689                         }
 690                         /* did we find any match? */
 691                         if (i < orig_arity)
 692                                 continue;
 693
 694                         /* we might need more space in the input arrays */
 695                         if (arity >= in_size) {
 696                                 const arch_register_req_t **new_in_reg_reqs;
 697                                 ir_node             **new_in;
 698
 699                                 in_size *= 2;
 700                                 new_in_reg_reqs
 701                                         = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
 702                                 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
 703                                 new_in = ALLOCANZ(ir_node*, in_size);
 704                                 memcpy(new_in, in, arity*sizeof(new_in[0]));
 705
 706                                 in_reg_reqs = new_in_reg_reqs;
 707                                 in          = new_in;
 708                         }
 709
 710                         /* add a new (dummy) input which occupies the register */
 711                         assert(outreq->type & arch_register_req_type_limited);
 712                         in_reg_reqs[arity] = outreq;
 713                         in[arity]          = new_bd_ia32_ProduceVal(NULL, block);
 714                         be_dep_on_frame(in[arity]);
 715                         ++arity;
 716                 }
 717         } else {
 718                 int       i;
 719                 bitset_t *used_outs = bitset_alloca(out_arity);
 720                 int       orig_out_arity = out_arity;
 721                 for (i = 0; i < arity; ++i) {
 722                         int   o;
 723                         const arch_register_req_t *inreq = in_reg_reqs[i];
 724
 725                         if (inreq->cls == NULL) {
 726                                 continue;
 727                         }
 728
 729                         for (o = 0; o < orig_out_arity; ++o) {
 730                                 const arch_register_req_t *outreq;
 731                                 if (bitset_is_set(used_outs, o))
 732                                         continue;
 733                                 outreq = out_reg_reqs[o];
 734                                 if (!can_match(outreq, inreq))
 735                                         continue;
 736                                 bitset_set(used_outs, i);
 737                                 break;
 738                         }
 739                         /* did we find any match? */
 740                         if (o < orig_out_arity)
 741                                 continue;
 742
 743                         /* we might need more space in the output arrays */
 744                         if (out_arity >= out_size) {
 745                                 const arch_register_req_t **new_out_reg_reqs;
 746
 747                                 out_size *= 2;
 748                                 new_out_reg_reqs
 749                                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 750                                 memcpy(new_out_reg_reqs, out_reg_reqs,
 751                                        out_arity * sizeof(new_out_reg_reqs[0]));
 752                                 out_reg_reqs = new_out_reg_reqs;
 753                         }
 754
 755                         /* add a new (dummy) output which occupies the register */
 756                         assert(inreq->type & arch_register_req_type_limited);
 757                         out_reg_reqs[out_arity] = inreq;
 758                         ++out_arity;
 759                 }
 760         }
 761
 762         /* append none register requirement for the memory output */
 763         if (out_arity + 1 >= out_size) {
 764                 const arch_register_req_t **new_out_reg_reqs;
 765
 766                 out_size = out_arity + 1;
 767                 new_out_reg_reqs
 768                         = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
 769                 memcpy(new_out_reg_reqs, out_reg_reqs,
 770                            out_arity * sizeof(new_out_reg_reqs[0]));
 771                 out_reg_reqs = new_out_reg_reqs;
 772         }
 773
 774         /* add a new (dummy) output which occupies the register */
 775         out_reg_reqs[out_arity] = arch_no_register_req;
 776         ++out_arity;
 777
 778         new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
 779                                    get_ASM_text(node), register_map);
 780
 781         if (arity == 0)
 782                 be_dep_on_frame(new_node);
 783
 784         info = be_get_info(new_node);
 785         for (i = 0; i < out_arity; ++i) {
 786                 info->out_infos[i].req = out_reg_reqs[i];
 787         }
 788         set_ia32_in_req_all(new_node, in_reg_reqs);
 789
 790         SET_IA32_ORIG_NODE(new_node, node);
 791
 792         return new_node;
 793 }
 794
 795 ir_node *gen_CopyB(ir_node *node) {
 796         ir_node  *block    = NULL;
 797         ir_node  *src      = NULL;
 798         ir_node  *new_src  = NULL;
 799         ir_node  *dst      = NULL;
 800         ir_node  *new_dst  = NULL;
 801         ir_node  *mem      = NULL;
 802         ir_node  *new_mem  = NULL;
 803         ir_node  *res      = NULL;
 804         dbg_info *dbgi     = get_irn_dbg_info(node);
 805         int      size      = get_type_size_bytes(get_CopyB_type(node));
 806         int      rem;
 807
 808         switch (be_transformer) {
 809                 case TRANSFORMER_DEFAULT:
 810                         block    = be_transform_node(get_nodes_block(node));
 811                         src      = get_CopyB_src(node);
 812                         new_src  = be_transform_node(src);
 813                         dst      = get_CopyB_dst(node);
 814                         new_dst  = be_transform_node(dst);
 815                         mem      = get_CopyB_mem(node);
 816                         new_mem  = be_transform_node(mem);
 817                         break;
 818
 819 #ifdef FIRM_GRGEN_BE
 820                 case TRANSFORMER_PBQP:
 821                 case TRANSFORMER_RAND:
 822                         block    = get_nodes_block(node);
 823                         new_src  = get_CopyB_src(node);
 824                         new_dst  = get_CopyB_dst(node);
 825                         new_mem  = get_CopyB_mem(node);
 826                         break;
 827 #endif
 828
 829                 default: panic("invalid transformer");
 830         }
 831
 832         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 833         /* then we need the size explicitly in ECX.                    */
 834         if (size >= 32 * 4) {
 835                 rem = size & 0x3; /* size % 4 */
 836                 size >>= 2;
 837
 838                 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
 839                 be_dep_on_frame(res);
 840
 841                 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
 842         } else {
 843                 if (size == 0) {
 844                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 845                                    node);
 846                 }
 847                 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
 848         }
 849
 850         SET_IA32_ORIG_NODE(res, node);
 851
 852         return res;
 853 }
 854
 855 ir_node *gen_Proj_tls(ir_node *node) {
 856         ir_node  *block = NULL;
 857         dbg_info *dbgi  = NULL;
 858         ir_node  *res   = NULL;
 859
 860         switch (be_transformer) {
 861                 case TRANSFORMER_DEFAULT:
 862                         block = be_transform_node(get_nodes_block(node));
 863                         break;
 864
 865 #ifdef FIRM_GRGEN_BE
 866                 case TRANSFORMER_PBQP:
 867                 case TRANSFORMER_RAND:
 868                         block = get_nodes_block(node);
 869                         break;
 870 #endif
 871
 872                 default: panic("invalid transformer");
 873         }
 874
 875         res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
 876
 877         return res;
 878 }
 879
 880 ir_node *gen_Unknown(ir_node *node)
 881 {
 882         ir_mode *mode = get_irn_mode(node);
 883
 884         if (mode_is_float(mode)) {
 885                 if (ia32_cg_config.use_sse2) {
 886                         return ia32_new_Unknown_xmm(env_cg);
 887                 } else {
 888                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 889                         ir_graph *irg   = current_ir_graph;
 890                         dbg_info *dbgi  = get_irn_dbg_info(node);
 891                         ir_node  *block = get_irg_start_block(irg);
 892                         ir_node  *ret   = new_bd_ia32_vfldz(dbgi, block);
 893
 894                         be_dep_on_frame(ret);
 895                         return ret;
 896                 }
 897         } else if (ia32_mode_needs_gp_reg(mode)) {
 898                 return ia32_new_Unknown_gp(env_cg);
 899         } else {
 900                 panic("unsupported Unknown-Mode");
 901         }
 902         return NULL;
 903 }
 904
 905 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 906                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 907 {
 908         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 909         int                  same_as = constraint->same_as;
 910         arch_register_req_t *req;
 911
 912         if (same_as >= 0) {
 913                 const arch_register_req_t *other_constr;
 914
 915                 if (same_as >= n_outs)
 916                         panic("invalid output number in same_as constraint");
 917
 918                 other_constr     = out_reqs[same_as];
 919
 920                 req              = obstack_alloc(obst, sizeof(req[0]));
 921                 *req             = *other_constr;
 922                 req->type       |= arch_register_req_type_should_be_same;
 923                 req->other_same  = 1U << pos;
 924
 925                 /* switch constraints. This is because in firm we have same_as
 926                  * constraints on the output constraints while in the gcc asm syntax
 927                  * they are specified on the input constraints */
 928                 out_reqs[same_as] = req;
 929                 return other_constr;
 930         }
 931
 932         /* pure memory ops */
 933         if (constraint->cls == NULL) {
 934                 return &no_register_req;
 935         }
 936
 937         if (constraint->allowed_registers != 0
 938                         && !constraint->all_registers_allowed) {
 939                 unsigned *limited_ptr;
 940
 941                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 942                 memset(req, 0, sizeof(req[0]));
 943                 limited_ptr = (unsigned*) (req+1);
 944
 945                 req->type    = arch_register_req_type_limited;
 946                 *limited_ptr = constraint->allowed_registers;
 947                 req->limited = limited_ptr;
 948         } else {
 949                 req       = obstack_alloc(obst, sizeof(req[0]));
 950                 memset(req, 0, sizeof(req[0]));
 951                 req->type = arch_register_req_type_normal;
 952         }
 953         req->cls = constraint->cls;
 954
 955         return req;
 956 }
 957
 958 const arch_register_req_t *parse_clobber(const char *clobber)
 959 {
 960         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 961         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 962         arch_register_req_t   *req;
 963         unsigned              *limited;
 964
 965         if (reg == NULL) {
 966                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 967         }
 968
 969         assert(reg->index < 32);
 970
 971         limited  = obstack_alloc(obst, sizeof(limited[0]));
 972         *limited = 1 << reg->index;
 973
 974         req          = obstack_alloc(obst, sizeof(req[0]));
 975         memset(req, 0, sizeof(req[0]));
 976         req->type    = arch_register_req_type_limited;
 977         req->cls     = arch_register_get_class(reg);
 978         req->limited = limited;
 979
 980         return req;
 981 }
 982
 983
 984 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
 985                        ir_node *const other)
 986 {
 987         if (get_nodes_block(other) != block)
 988                 return 0;
 989
 990         if (is_Sync(other)) {
 991                 int i;
 992
 993                 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
 994                         ir_node *const pred = get_Sync_pred(other, i);
 995
 996                         if (get_nodes_block(pred) != block)
 997                                 continue;
 998
 999                         /* Do not block ourselves from getting eaten */
1000                         if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
1001                                 continue;
1002
1003                         if (!heights_reachable_in_block(heights, pred, am_candidate))
1004                                 continue;
1005
1006                         return 1;
1007                 }
1008
1009                 return 0;
1010         } else {
1011                 /* Do not block ourselves from getting eaten */
1012                 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
1013                         return 0;
1014
1015                 if (!heights_reachable_in_block(heights, other, am_candidate))
1016                         return 0;
1017
1018                 return 1;
1019         }
1020 }
1021
1022 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
1023 {
1024         int          minus         = 0;
1025         tarval      *offset        = NULL;
1026         int          offset_sign   = 0;
1027         long         val = 0;
1028         ir_entity   *symconst_ent  = NULL;
1029         int          symconst_sign = 0;
1030         ir_mode     *mode;
1031         ir_node     *cnst          = NULL;
1032         ir_node     *symconst      = NULL;
1033         ir_node     *new_node;
1034
1035         mode = get_irn_mode(node);
1036         if (!mode_is_int(mode) && !mode_is_reference(mode)) {
1037                 return NULL;
1038         }
1039
1040         if (is_Minus(node)) {
1041                 minus = 1;
1042                 node  = get_Minus_op(node);
1043         }
1044
1045         if (is_Const(node)) {
1046                 cnst        = node;
1047                 symconst    = NULL;
1048                 offset_sign = minus;
1049         } else if (is_SymConst(node)) {
1050                 cnst          = NULL;
1051                 symconst      = node;
1052                 symconst_sign = minus;
1053         } else if (is_Add(node)) {
1054                 ir_node *left  = get_Add_left(node);
1055                 ir_node *right = get_Add_right(node);
1056                 if (is_Const(left) && is_SymConst(right)) {
1057                         cnst          = left;
1058                         symconst      = right;
1059                         symconst_sign = minus;
1060                         offset_sign   = minus;
1061                 } else if (is_SymConst(left) && is_Const(right)) {
1062                         cnst          = right;
1063                         symconst      = left;
1064                         symconst_sign = minus;
1065                         offset_sign   = minus;
1066                 }
1067         } else if (is_Sub(node)) {
1068                 ir_node *left  = get_Sub_left(node);
1069                 ir_node *right = get_Sub_right(node);
1070                 if (is_Const(left) && is_SymConst(right)) {
1071                         cnst          = left;
1072                         symconst      = right;
1073                         symconst_sign = !minus;
1074                         offset_sign   = minus;
1075                 } else if (is_SymConst(left) && is_Const(right)) {
1076                         cnst          = right;
1077                         symconst      = left;
1078                         symconst_sign = minus;
1079                         offset_sign   = !minus;
1080                 }
1081         } else {
1082                 return NULL;
1083         }
1084
1085         if (cnst != NULL) {
1086                 offset = get_Const_tarval(cnst);
1087                 if (tarval_is_long(offset)) {
1088                         val = get_tarval_long(offset);
1089                 } else {
1090                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
1091                                    "long?\n", cnst);
1092                         return NULL;
1093                 }
1094
1095                 if (!check_immediate_constraint(val, immediate_constraint_type))
1096                         return NULL;
1097         }
1098         if (symconst != NULL) {
1099                 if (immediate_constraint_type != 0) {
1100                         /* we need full 32bits for symconsts */
1101                         return NULL;
1102                 }
1103
1104                 /* unfortunately the assembler/linker doesn't support -symconst */
1105                 if (symconst_sign)
1106                         return NULL;
1107
1108                 if (get_SymConst_kind(symconst) != symconst_addr_ent)
1109                         return NULL;
1110                 symconst_ent = get_SymConst_entity(symconst);
1111         }
1112         if (cnst == NULL && symconst == NULL)
1113                 return NULL;
1114
1115         if (offset_sign && offset != NULL) {
1116                 offset = tarval_neg(offset);
1117         }
1118
1119         new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val);
1120
1121         return new_node;
1122 }