nsz Git - libfirm/blob - ir/be/ia32/ia32_common_transform.c

   1 /*
   2  * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This file implements the common parts of IR transformation from
  23  *              firm into ia32-Firm.
  24  * @author      Matthias Braun, Sebastian Buchwald
  25  * @version     $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
  26  */
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "error.h"
  32 #include "irargs_t.h"
  33 #include "ircons.h"
  34 #include "irprintf.h"
  35 #include "typerep.h"
  36
  37 #include "../betranshlp.h"
  38 #include "../beirg_t.h"
  39
  40 #include "ia32_architecture.h"
  41 #include "ia32_common_transform.h"
  42 #include "ia32_new_nodes.h"
  43
  44 #include "gen_ia32_new_nodes.h"
  45 #include "gen_ia32_regalloc_if.h"
  46
  47 /** hold the current code generator during transformation */
  48 ia32_code_gen_t *env_cg = NULL;
  49
  50 heights_t *heights = NULL;
  51
  52 static const arch_register_req_t no_register_req = {
  53         arch_register_req_type_none,
  54         NULL,                         /* regclass */
  55         NULL,                         /* limit bitset */
  56         0,                            /* same pos */
  57         0                             /* different pos */
  58 };
  59
  60 static int check_immediate_constraint(long val, char immediate_constraint_type)
  61 {
  62         switch (immediate_constraint_type) {
  63                 case 0:
  64                 case 'i': return 1;
  65
  66                 case 'I': return    0 <= val && val <=  31;
  67                 case 'J': return    0 <= val && val <=  63;
  68                 case 'K': return -128 <= val && val <= 127;
  69                 case 'L': return val == 0xff || val == 0xffff;
  70                 case 'M': return    0 <= val && val <=   3;
  71                 case 'N': return    0 <= val && val <= 255;
  72                 case 'O': return    0 <= val && val <= 127;
  73
  74                 default: panic("Invalid immediate constraint found");
  75         }
  76 }
  77
  78 /**
  79  * creates a unique ident by adding a number to a tag
  80  *
  81  * @param tag   the tag string, must contain a %d if a number
  82  *              should be added
  83  */
  84 static ident *unique_id(const char *tag)
  85 {
  86         static unsigned id = 0;
  87         char str[256];
  88
  89         snprintf(str, sizeof(str), tag, ++id);
  90         return new_id_from_str(str);
  91 }
  92
  93 /**
  94  * Get a primitive type for a mode.
  95  */
  96 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
  97 {
  98         pmap_entry *e = pmap_find(types, mode);
  99         ir_type *res;
 100
 101         if (! e) {
 102                 char buf[64];
 103                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
 104                 res = new_type_primitive(new_id_from_str(buf), mode);
 105                 set_type_alignment_bytes(res, 16);
 106                 pmap_insert(types, mode, res);
 107         }
 108         else
 109                 res = e->value;
 110         return res;
 111 }
 112
 113 ir_entity *create_float_const_entity(ir_node *cnst)
 114 {
 115         ia32_isa_t *isa = env_cg->isa;
 116         tarval *key     = get_Const_tarval(cnst);
 117         pmap_entry *e   = pmap_find(isa->tv_ent, key);
 118         ir_entity *res;
 119         ir_graph *rem;
 120
 121         if (e == NULL) {
 122                 tarval  *tv   = key;
 123                 ir_mode *mode = get_tarval_mode(tv);
 124                 ir_type *tp;
 125
 126                 if (! ia32_cg_config.use_sse2) {
 127                         /* try to reduce the mode to produce smaller sized entities */
 128                         if (mode != mode_F) {
 129                                 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
 130                                         mode = mode_F;
 131                                         tv = tarval_convert_to(tv, mode);
 132                                 } else if (mode != mode_D) {
 133                                         if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
 134                                                 mode = mode_D;
 135                                                 tv = tarval_convert_to(tv, mode);
 136                                         }
 137                                 }
 138                         }
 139                 }
 140
 141                 if (mode == get_irn_mode(cnst)) {
 142                         /* mode was not changed */
 143                         tp = get_Const_type(cnst);
 144                         if (tp == firm_unknown_type)
 145                                 tp = ia32_get_prim_type(isa->types, mode);
 146                 } else
 147                         tp = ia32_get_prim_type(isa->types, mode);
 148
 149                 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
 150
 151                 set_entity_ld_ident(res, get_entity_ident(res));
 152                 set_entity_visibility(res, visibility_local);
 153                 set_entity_variability(res, variability_constant);
 154                 set_entity_allocation(res, allocation_static);
 155
 156                  /* we create a new entity here: It's initialization must resist on the
 157                     const code irg */
 158                 rem = current_ir_graph;
 159                 current_ir_graph = get_const_code_irg();
 160                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 161                 current_ir_graph = rem;
 162
 163                 pmap_insert(isa->tv_ent, key, res);
 164         } else {
 165                 res = e->value;
 166         }
 167
 168         return res;
 169 }
 170
 171 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
 172 {
 173         ir_graph *irg         = current_ir_graph;
 174         ir_node  *start_block = get_irg_start_block(irg);
 175         ir_node  *immediate   = new_rd_ia32_Immediate(NULL, irg, start_block,
 176                                                       symconst, symconst_sign, val);
 177         arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
 178
 179         return immediate;
 180 }
 181
 182 const arch_register_t *ia32_get_clobber_register(const char *clobber)
 183 {
 184         const arch_register_t       *reg = NULL;
 185         int                          c;
 186         size_t                       r;
 187         const arch_register_class_t *cls;
 188
 189         /* TODO: construct a hashmap instead of doing linear search for clobber
 190          * register */
 191         for(c = 0; c < N_CLASSES; ++c) {
 192                 cls = & ia32_reg_classes[c];
 193                 for(r = 0; r < cls->n_regs; ++r) {
 194                         const arch_register_t *temp_reg = arch_register_for_index(cls, r);
 195                         if(strcmp(temp_reg->name, clobber) == 0
 196                                         || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
 197                                 reg = temp_reg;
 198                                 break;
 199                         }
 200                 }
 201                 if(reg != NULL)
 202                         break;
 203         }
 204
 205         return reg;
 206 }
 207
 208 #ifndef NDEBUG
 209 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
 210         ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
 211
 212         lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
 213         obstack_1grow(isa->name_obst, 0);
 214         return obstack_finish(isa->name_obst);
 215 }
 216 #endif /* NDEBUG */
 217
 218 int ia32_mode_needs_gp_reg(ir_mode *mode) {
 219         if(mode == mode_fpcw)
 220                 return 0;
 221         if(get_mode_size_bits(mode) > 32)
 222                 return 0;
 223         return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
 224 }
 225
 226 static void parse_asm_constraints(constraint_t *constraint, const char *c,
 227                            int is_output)
 228 {
 229         asm_constraint_flags_t       flags              = 0;
 230         char                         immediate_type     = '\0';
 231         unsigned                     limited            = 0;
 232         const arch_register_class_t *cls                = NULL;
 233         int                          memory_possible       = 0;
 234         int                          all_registers_allowed = 0;
 235         int                          p;
 236         int                          same_as = -1;
 237
 238         memset(constraint, 0, sizeof(constraint[0]));
 239         constraint->same_as = -1;
 240
 241         if(*c == 0) {
 242                 /* a memory constraint: no need to do anything in backend about it
 243                  * (the dependencies are already respected by the memory edge of
 244                  * the node) */
 245                 return;
 246         }
 247
 248         /* TODO: improve error messages with node and source info. (As users can
 249          * easily hit these) */
 250         while(*c != 0) {
 251                 switch(*c) {
 252                 case ' ':
 253                 case '\t':
 254                 case '\n':
 255                         break;
 256
 257                 case '=':
 258                         flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
 259                                 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
 260                         break;
 261
 262                 case '+':
 263                         flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
 264                                 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
 265                         break;
 266
 267                 case '*':
 268                         ++c;
 269                         break;
 270                 case '#':
 271                         while(*c != 0 && *c != ',')
 272                                 ++c;
 273                         break;
 274
 275                 case 'a':
 276                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 277                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 278                         limited |= 1 << REG_EAX;
 279                         break;
 280                 case 'b':
 281                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 282                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 283                         limited |= 1 << REG_EBX;
 284                         break;
 285                 case 'c':
 286                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 287                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 288                         limited |= 1 << REG_ECX;
 289                         break;
 290                 case 'd':
 291                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 292                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 293                         limited |= 1 << REG_EDX;
 294                         break;
 295                 case 'D':
 296                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 297                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 298                         limited |= 1 << REG_EDI;
 299                         break;
 300                 case 'S':
 301                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 302                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 303                         limited |= 1 << REG_ESI;
 304                         break;
 305                 case 'Q':
 306                 case 'q':
 307                         /* q means lower part of the regs only, this makes no
 308                          * difference to Q for us (we only assign whole registers) */
 309                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 310                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 311                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 312                                    1 << REG_EDX;
 313                         break;
 314                 case 'A':
 315                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 316                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 317                         limited |= 1 << REG_EAX | 1 << REG_EDX;
 318                         break;
 319                 case 'l':
 320                         assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
 321                         cls      = &ia32_reg_classes[CLASS_ia32_gp];
 322                         limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
 323                                    1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
 324                                    1 << REG_EBP;
 325                         break;
 326
 327                 case 'R':
 328                 case 'r':
 329                 case 'p':
 330                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 331                                 panic("multiple register classes not supported");
 332                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 333                         all_registers_allowed = 1;
 334                         break;
 335
 336                 case 'f':
 337                 case 't':
 338                 case 'u':
 339                         /* TODO: mark values so the x87 simulator knows about t and u */
 340                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
 341                                 panic("multiple register classes not supported");
 342                         cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
 343                         all_registers_allowed = 1;
 344                         break;
 345
 346                 case 'Y':
 347                 case 'x':
 348                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
 349                                 panic("multiple register classes not supproted");
 350                         cls                   = &ia32_reg_classes[CLASS_ia32_xmm];
 351                         all_registers_allowed = 1;
 352                         break;
 353
 354                 case 'I':
 355                 case 'J':
 356                 case 'K':
 357                 case 'L':
 358                 case 'M':
 359                 case 'N':
 360                 case 'O':
 361                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 362                                 panic("multiple register classes not supported");
 363                         if (immediate_type != '\0')
 364                                 panic("multiple immediate types not supported");
 365                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 366                         immediate_type = *c;
 367                         break;
 368                 case 'n':
 369                 case 'i':
 370                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 371                                 panic("multiple register classes not supported");
 372                         if (immediate_type != '\0')
 373                                 panic("multiple immediate types not supported");
 374                         cls            = &ia32_reg_classes[CLASS_ia32_gp];
 375                         immediate_type = 'i';
 376                         break;
 377
 378                 case 'X':
 379                 case 'g':
 380                         if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
 381                                 panic("multiple register classes not supported");
 382                         if (immediate_type != '\0')
 383                                 panic("multiple immediate types not supported");
 384                         immediate_type        = 'i';
 385                         cls                   = &ia32_reg_classes[CLASS_ia32_gp];
 386                         all_registers_allowed = 1;
 387                         memory_possible       = 1;
 388                         break;
 389
 390                 case '0':
 391                 case '1':
 392                 case '2':
 393                 case '3':
 394                 case '4':
 395                 case '5':
 396                 case '6':
 397                 case '7':
 398                 case '8':
 399                 case '9':
 400                         if (is_output)
 401                                 panic("can only specify same constraint on input");
 402
 403                         sscanf(c, "%d%n", &same_as, &p);
 404                         if(same_as >= 0) {
 405                                 c += p;
 406                                 continue;
 407                         }
 408                         break;
 409
 410                 case 'm':
 411                 case 'o':
 412                 case 'V':
 413                         /* memory constraint no need to do anything in backend about it
 414                          * (the dependencies are already respected by the memory edge of
 415                          * the node) */
 416                         memory_possible = 1;
 417                         break;
 418
 419                 case 'E': /* no float consts yet */
 420                 case 'F': /* no float consts yet */
 421                 case 's': /* makes no sense on x86 */
 422                 case '<': /* no autodecrement on x86 */
 423                 case '>': /* no autoincrement on x86 */
 424                 case 'C': /* sse constant not supported yet */
 425                 case 'G': /* 80387 constant not supported yet */
 426                 case 'y': /* we don't support mmx registers yet */
 427                 case 'Z': /* not available in 32 bit mode */
 428                 case 'e': /* not available in 32 bit mode */
 429                         panic("unsupported asm constraint '%c' found in (%+F)",
 430                               *c, current_ir_graph);
 431                         break;
 432                 default:
 433                         panic("unknown asm constraint '%c' found in (%+F)", *c,
 434                               current_ir_graph);
 435                         break;
 436                 }
 437                 ++c;
 438         }
 439
 440         if(same_as >= 0) {
 441                 if (cls != NULL)
 442                         panic("same as and register constraint not supported");
 443                 if (immediate_type != '\0')
 444                         panic("same as and immediate constraint not supported");
 445         }
 446
 447         if (cls == NULL && same_as < 0) {
 448                 if (!memory_possible)
 449                         panic("no constraint specified for assembler input");
 450         }
 451
 452         constraint->same_as               = same_as;
 453         constraint->cls                   = cls;
 454         constraint->allowed_registers     = limited;
 455         constraint->all_registers_allowed = all_registers_allowed;
 456         constraint->memory_possible       = memory_possible;
 457         constraint->immediate_type        = immediate_type;
 458 }
 459
 460 ir_node *gen_ASM(ir_node *node)
 461 {
 462         ir_graph                   *irg       = current_ir_graph;
 463         ir_node                    *block = NULL;
 464         ir_node                    *new_block = NULL;
 465         dbg_info                   *dbgi      = get_irn_dbg_info(node);
 466         int                         i, arity;
 467         int                         out_idx;
 468         ir_node                   **in;
 469         ir_node                    *new_node;
 470         int                         out_arity;
 471         int                         n_out_constraints;
 472         int                         n_clobbers;
 473         const arch_register_req_t **out_reg_reqs;
 474         const arch_register_req_t **in_reg_reqs;
 475         ia32_asm_reg_t             *register_map;
 476         unsigned                    reg_map_size = 0;
 477         struct obstack             *obst;
 478         const ir_asm_constraint    *in_constraints;
 479         const ir_asm_constraint    *out_constraints;
 480         ident                     **clobbers;
 481         int                         clobbers_flags = 0;
 482         unsigned                    clobber_bits[N_CLASSES];
 483
 484         memset(&clobber_bits, 0, sizeof(clobber_bits));
 485
 486         switch (be_transformer) {
 487         case TRANSFORMER_DEFAULT:
 488                 block     = get_nodes_block(node);
 489                 new_block = be_transform_node(block);
 490                 break;
 491
 492 #ifdef FIRM_GRGEN_BE
 493         case TRANSFORMER_PBQP:
 494                 new_block = get_nodes_block(node);
 495                 break;
 496 #endif
 497
 498         default:
 499                 panic("invalid transformer");
 500         }
 501
 502         /* workaround for lots of buggy code out there as most people think volatile
 503          * asm is enough for everything and forget the flags (linux kernel, etc.)
 504          */
 505         if (get_irn_pinned(node) == op_pin_state_pinned) {
 506                 clobbers_flags = 1;
 507         }
 508
 509         arity = get_irn_arity(node);
 510         in    = alloca(arity * sizeof(in[0]));
 511         memset(in, 0, arity * sizeof(in[0]));
 512
 513         clobbers   = get_ASM_clobbers(node);
 514         n_clobbers = 0;
 515         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 516                 const arch_register_req_t *req;
 517                 const char                *c = get_id_str(clobbers[i]);
 518
 519                 if (strcmp(c, "memory") == 0)
 520                         continue;
 521                 if (strcmp(c, "cc") == 0) {
 522                         clobbers_flags = 1;
 523                         continue;
 524                 }
 525
 526                 req = parse_clobber(c);
 527                 clobber_bits[req->cls->index] |= *req->limited;
 528
 529                 n_clobbers++;
 530         }
 531         n_out_constraints = get_ASM_n_output_constraints(node);
 532         out_arity         = n_out_constraints + n_clobbers;
 533
 534         in_constraints  = get_ASM_input_constraints(node);
 535         out_constraints = get_ASM_output_constraints(node);
 536
 537         /* determine size of register_map */
 538         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 539                 const ir_asm_constraint *constraint = &out_constraints[out_idx];
 540                 if (constraint->pos > reg_map_size)
 541                         reg_map_size = constraint->pos;
 542         }
 543         for (i = 0; i < arity; ++i) {
 544                 const ir_asm_constraint   *constraint = &in_constraints[i];
 545                 if(constraint->pos > reg_map_size)
 546                         reg_map_size = constraint->pos;
 547         }
 548         ++reg_map_size;
 549
 550         obst         = get_irg_obstack(irg);
 551         register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
 552         memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
 553
 554         /* construct output constraints */
 555         out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
 556
 557         for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
 558                 const ir_asm_constraint   *constraint = &out_constraints[out_idx];
 559                 const char                *c       = get_id_str(constraint->constraint);
 560                 unsigned                   pos        = constraint->pos;
 561                 constraint_t               parsed_constraint;
 562                 const arch_register_req_t *req;
 563
 564                 parse_asm_constraints(&parsed_constraint, c, 1);
 565                 req = make_register_req(&parsed_constraint, n_out_constraints,
 566                                         out_reg_reqs, out_idx);
 567                 out_reg_reqs[out_idx] = req;
 568
 569                 register_map[pos].use_input = 0;
 570                 register_map[pos].valid     = 1;
 571                 register_map[pos].memory    = 0;
 572                 register_map[pos].inout_pos = out_idx;
 573                 register_map[pos].mode      = constraint->mode;
 574         }
 575
 576         /* inputs + input constraints */
 577         in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
 578         for (i = 0; i < arity; ++i) {
 579                 ir_node                   *pred         = get_irn_n(node, i);
 580                 const ir_asm_constraint   *constraint   = &in_constraints[i];
 581                 ident                     *constr_id    = constraint->constraint;
 582                 const char                *c            = get_id_str(constr_id);
 583                 unsigned                   pos          = constraint->pos;
 584                 int                        is_memory_op = 0;
 585                 ir_node                   *input        = NULL;
 586                 unsigned                   r_clobber_bits;
 587                 constraint_t               parsed_constraint;
 588                 const arch_register_req_t *req;
 589
 590                 parse_asm_constraints(&parsed_constraint, c, 0);
 591                 if (parsed_constraint.cls != NULL) {
 592                         r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
 593                         if (r_clobber_bits != 0) {
 594                                 if (parsed_constraint.all_registers_allowed) {
 595                                         parsed_constraint.all_registers_allowed = 0;
 596                                         be_abi_set_non_ignore_regs(env_cg->birg->abi,
 597                                                         parsed_constraint.cls,
 598                                                         &parsed_constraint.allowed_registers);
 599                                 }
 600                                 parsed_constraint.allowed_registers &= ~r_clobber_bits;
 601                         }
 602                 }
 603
 604                 req = make_register_req(&parsed_constraint, n_out_constraints,
 605                                         out_reg_reqs, i);
 606                 in_reg_reqs[i] = req;
 607
 608                 if (parsed_constraint.immediate_type != '\0') {
 609                         char imm_type = parsed_constraint.immediate_type;
 610                         input = try_create_Immediate(pred, imm_type);
 611                 }
 612
 613                 if (input == NULL) {
 614                         ir_node *pred = NULL;
 615                         switch (be_transformer) {
 616                         case TRANSFORMER_DEFAULT:
 617                                 pred  = get_irn_n(node, i);
 618                                 input = be_transform_node(pred);
 619                                 break;
 620
 621 #ifdef FIRM_GRGEN_BE
 622                         case TRANSFORMER_PBQP:
 623                                 input = get_irn_n(node, i);
 624                                 break;
 625 #endif
 626
 627                         default: panic("invalid transformer");
 628                         }
 629
 630                         if (parsed_constraint.cls == NULL
 631                                         && parsed_constraint.same_as < 0) {
 632                                 is_memory_op = 1;
 633                         } else if(parsed_constraint.memory_possible) {
 634                                 /* TODO: match Load or Load/Store if memory possible is set */
 635                         }
 636                 }
 637                 in[i] = input;
 638
 639                 register_map[pos].use_input = 1;
 640                 register_map[pos].valid     = 1;
 641                 register_map[pos].memory    = is_memory_op;
 642                 register_map[pos].inout_pos = i;
 643                 register_map[pos].mode      = constraint->mode;
 644         }
 645
 646         /* parse clobbers */
 647         for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
 648                 const char                *c = get_id_str(clobbers[i]);
 649                 const arch_register_req_t *req;
 650
 651                 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
 652                         continue;
 653
 654                 req = parse_clobber(c);
 655                 out_reg_reqs[out_idx] = req;
 656                 ++out_idx;
 657         }
 658
 659         new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
 660                                    get_ASM_text(node), register_map);
 661
 662         /* Prevent the ASM node from being scheduled before the Barrier, if it has
 663          * no inputs */
 664         if (arity == 0 && get_irg_start_block(irg) == new_block) {
 665                 add_irn_dep(new_node, get_irg_frame(irg));
 666         }
 667
 668         set_ia32_out_req_all(new_node, out_reg_reqs);
 669         set_ia32_in_req_all(new_node, in_reg_reqs);
 670
 671         SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
 672
 673         return new_node;
 674 }
 675
 676 ir_node *gen_CopyB(ir_node *node) {
 677         ir_node  *block    = NULL;
 678         ir_node  *src      = NULL;
 679         ir_node  *new_src  = NULL;
 680         ir_node  *dst      = NULL;
 681         ir_node  *new_dst  = NULL;
 682         ir_node  *mem      = NULL;
 683         ir_node  *new_mem  = NULL;
 684         ir_node  *res      = NULL;
 685         ir_graph *irg      = current_ir_graph;
 686         dbg_info *dbgi     = get_irn_dbg_info(node);
 687         int      size      = get_type_size_bytes(get_CopyB_type(node));
 688         int      rem;
 689
 690         switch (be_transformer) {
 691                 case TRANSFORMER_DEFAULT:
 692                         block    = be_transform_node(get_nodes_block(node));
 693                         src      = get_CopyB_src(node);
 694                         new_src  = be_transform_node(src);
 695                         dst      = get_CopyB_dst(node);
 696                         new_dst  = be_transform_node(dst);
 697                         mem      = get_CopyB_mem(node);
 698                         new_mem  = be_transform_node(mem);
 699                         break;
 700
 701 #ifdef FIRM_GRGEN_BE
 702                 case TRANSFORMER_PBQP:
 703                         block    = get_nodes_block(node);
 704                         new_src  = get_CopyB_src(node);
 705                         new_dst  = get_CopyB_dst(node);
 706                         new_mem  = get_CopyB_mem(node);
 707                         break;
 708 #endif
 709
 710                 default: panic("invalid transformer");
 711         }
 712
 713         /* If we have to copy more than 32 bytes, we use REP MOVSx and */
 714         /* then we need the size explicitly in ECX.                    */
 715         if (size >= 32 * 4) {
 716                 rem = size & 0x3; /* size % 4 */
 717                 size >>= 2;
 718
 719                 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
 720                 add_irn_dep(res, get_irg_frame(irg));
 721
 722                 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
 723         } else {
 724                 if(size == 0) {
 725                         ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
 726                                    node);
 727                 }
 728                 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
 729         }
 730
 731         SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
 732
 733         return res;
 734 }
 735
 736 ir_node *gen_Proj_tls(ir_node *node) {
 737         ir_node  *block = NULL;
 738         ir_graph *irg   = current_ir_graph;
 739         dbg_info *dbgi  = NULL;
 740         ir_node  *res   = NULL;
 741
 742         switch (be_transformer) {
 743                 case TRANSFORMER_DEFAULT:
 744                         block = be_transform_node(get_nodes_block(node));
 745                         break;
 746
 747 #ifdef FIRM_GRGEN_BE
 748                 case TRANSFORMER_PBQP:
 749                         block = get_nodes_block(node);
 750                         break;
 751 #endif
 752
 753                 default: panic("invalid transformer");
 754         }
 755
 756         res   = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
 757
 758         return res;
 759 }
 760
 761 ir_node *gen_Unknown(ir_node *node)
 762 {
 763         ir_mode *mode = get_irn_mode(node);
 764
 765         if (mode_is_float(mode)) {
 766                 if (ia32_cg_config.use_sse2) {
 767                         return ia32_new_Unknown_xmm(env_cg);
 768                 } else {
 769                         /* Unknown nodes are buggy in x87 simulator, use zero for now... */
 770                         ir_graph *irg   = current_ir_graph;
 771                         dbg_info *dbgi  = get_irn_dbg_info(node);
 772                         ir_node  *block = get_irg_start_block(irg);
 773                         ir_node  *ret   = new_rd_ia32_vfldz(dbgi, irg, block);
 774
 775                         /* Const Nodes before the initial IncSP are a bad idea, because
 776                          * they could be spilled and we have no SP ready at that point yet.
 777                          * So add a dependency to the initial frame pointer calculation to
 778                          * avoid that situation.
 779                          */
 780                         add_irn_dep(ret, get_irg_frame(irg));
 781                         return ret;
 782                 }
 783         } else if (ia32_mode_needs_gp_reg(mode)) {
 784                 return ia32_new_Unknown_gp(env_cg);
 785         } else {
 786                 panic("unsupported Unknown-Mode");
 787         }
 788         return NULL;
 789 }
 790
 791 const arch_register_req_t *make_register_req(const constraint_t *constraint,
 792                 int n_outs, const arch_register_req_t **out_reqs, int pos)
 793 {
 794         struct obstack      *obst    = get_irg_obstack(current_ir_graph);
 795         int                  same_as = constraint->same_as;
 796         arch_register_req_t *req;
 797
 798         if (same_as >= 0) {
 799                 const arch_register_req_t *other_constr;
 800
 801                 if (same_as >= n_outs)
 802                         panic("invalid output number in same_as constraint");
 803
 804                 other_constr     = out_reqs[same_as];
 805
 806                 req              = obstack_alloc(obst, sizeof(req[0]));
 807                 *req             = *other_constr;
 808                 req->type       |= arch_register_req_type_should_be_same;
 809                 req->other_same  = 1U << pos;
 810
 811                 /* switch constraints. This is because in firm we have same_as
 812                  * constraints on the output constraints while in the gcc asm syntax
 813                  * they are specified on the input constraints */
 814                 out_reqs[same_as] = req;
 815                 return other_constr;
 816         }
 817
 818         /* pure memory ops */
 819         if (constraint->cls == NULL) {
 820                 return &no_register_req;
 821         }
 822
 823         if (constraint->allowed_registers != 0
 824                         && !constraint->all_registers_allowed) {
 825                 unsigned *limited_ptr;
 826
 827                 req         = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
 828                 memset(req, 0, sizeof(req[0]));
 829                 limited_ptr = (unsigned*) (req+1);
 830
 831                 req->type    = arch_register_req_type_limited;
 832                 *limited_ptr = constraint->allowed_registers;
 833                 req->limited = limited_ptr;
 834         } else {
 835                 req       = obstack_alloc(obst, sizeof(req[0]));
 836                 memset(req, 0, sizeof(req[0]));
 837                 req->type = arch_register_req_type_normal;
 838         }
 839         req->cls = constraint->cls;
 840
 841         return req;
 842 }
 843
 844 const arch_register_req_t *parse_clobber(const char *clobber)
 845 {
 846         struct obstack        *obst = get_irg_obstack(current_ir_graph);
 847         const arch_register_t *reg  = ia32_get_clobber_register(clobber);
 848         arch_register_req_t   *req;
 849         unsigned              *limited;
 850
 851         if(reg == NULL) {
 852                 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
 853         }
 854
 855         assert(reg->index < 32);
 856
 857         limited  = obstack_alloc(obst, sizeof(limited[0]));
 858         *limited = 1 << reg->index;
 859
 860         req          = obstack_alloc(obst, sizeof(req[0]));
 861         memset(req, 0, sizeof(req[0]));
 862         req->type    = arch_register_req_type_limited;
 863         req->cls     = arch_register_get_class(reg);
 864         req->limited = limited;
 865
 866         return req;
 867 }
 868
 869 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
 870 {
 871         int          minus         = 0;
 872         tarval      *offset        = NULL;
 873         int          offset_sign   = 0;
 874         long         val = 0;
 875         ir_entity   *symconst_ent  = NULL;
 876         int          symconst_sign = 0;
 877         ir_mode     *mode;
 878         ir_node     *cnst          = NULL;
 879         ir_node     *symconst      = NULL;
 880         ir_node     *new_node;
 881
 882         mode = get_irn_mode(node);
 883         if(!mode_is_int(mode) && !mode_is_reference(mode)) {
 884                 return NULL;
 885         }
 886
 887         if(is_Minus(node)) {
 888                 minus = 1;
 889                 node  = get_Minus_op(node);
 890         }
 891
 892         if(is_Const(node)) {
 893                 cnst        = node;
 894                 symconst    = NULL;
 895                 offset_sign = minus;
 896         } else if(is_SymConst(node)) {
 897                 cnst          = NULL;
 898                 symconst      = node;
 899                 symconst_sign = minus;
 900         } else if(is_Add(node)) {
 901                 ir_node *left  = get_Add_left(node);
 902                 ir_node *right = get_Add_right(node);
 903                 if(is_Const(left) && is_SymConst(right)) {
 904                         cnst          = left;
 905                         symconst      = right;
 906                         symconst_sign = minus;
 907                         offset_sign   = minus;
 908                 } else if(is_SymConst(left) && is_Const(right)) {
 909                         cnst          = right;
 910                         symconst      = left;
 911                         symconst_sign = minus;
 912                         offset_sign   = minus;
 913                 }
 914         } else if(is_Sub(node)) {
 915                 ir_node *left  = get_Sub_left(node);
 916                 ir_node *right = get_Sub_right(node);
 917                 if(is_Const(left) && is_SymConst(right)) {
 918                         cnst          = left;
 919                         symconst      = right;
 920                         symconst_sign = !minus;
 921                         offset_sign   = minus;
 922                 } else if(is_SymConst(left) && is_Const(right)) {
 923                         cnst          = right;
 924                         symconst      = left;
 925                         symconst_sign = minus;
 926                         offset_sign   = !minus;
 927                 }
 928         } else {
 929                 return NULL;
 930         }
 931
 932         if(cnst != NULL) {
 933                 offset = get_Const_tarval(cnst);
 934                 if(tarval_is_long(offset)) {
 935                         val = get_tarval_long(offset);
 936                 } else {
 937                         ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
 938                                    "long?\n", cnst);
 939                         return NULL;
 940                 }
 941
 942                 if(!check_immediate_constraint(val, immediate_constraint_type))
 943                         return NULL;
 944         }
 945         if(symconst != NULL) {
 946                 if(immediate_constraint_type != 0) {
 947                         /* we need full 32bits for symconsts */
 948                         return NULL;
 949                 }
 950
 951                 /* unfortunately the assembler/linker doesn't support -symconst */
 952                 if(symconst_sign)
 953                         return NULL;
 954
 955                 if(get_SymConst_kind(symconst) != symconst_addr_ent)
 956                         return NULL;
 957                 symconst_ent = get_SymConst_entity(symconst);
 958         }
 959         if(cnst == NULL && symconst == NULL)
 960                 return NULL;
 961
 962         if(offset_sign && offset != NULL) {
 963                 offset = tarval_neg(offset);
 964         }
 965
 966         new_node = create_Immediate(symconst_ent, symconst_sign, val);
 967
 968         return new_node;
 969 }