2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
36 #include "../betranshlp.h"
40 #include "ia32_architecture.h"
41 #include "ia32_common_transform.h"
42 #include "ia32_new_nodes.h"
44 #include "gen_ia32_new_nodes.h"
45 #include "gen_ia32_regalloc_if.h"
47 ir_heights_t *ia32_heights = NULL;
49 static int check_immediate_constraint(long val, char immediate_constraint_type)
51 switch (immediate_constraint_type) {
55 case 'I': return 0 <= val && val <= 31;
56 case 'J': return 0 <= val && val <= 63;
57 case 'K': return -128 <= val && val <= 127;
58 case 'L': return val == 0xff || val == 0xffff;
59 case 'M': return 0 <= val && val <= 3;
60 case 'N': return 0 <= val && val <= 255;
61 case 'O': return 0 <= val && val <= 127;
63 default: panic("Invalid immediate constraint found");
68 * Get a primitive type for a mode with alignment 16.
70 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
72 ir_type *res = (ir_type*)pmap_get(types, mode);
76 res = new_type_primitive(mode);
77 if (get_mode_size_bits(mode) >= 80) {
78 set_type_alignment_bytes(res, 16);
80 pmap_insert(types, mode, res);
84 ir_entity *ia32_create_float_const_entity(ir_node *cnst)
86 ir_graph *irg = get_irn_irg(cnst);
87 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
88 ia32_isa_t *isa = (ia32_isa_t*) arch_env;
89 ir_tarval *tv = get_Const_tarval(cnst);
90 ir_entity *res = (ir_entity*)pmap_get(isa->tv_ent, tv);
91 ir_initializer_t *initializer;
98 mode = get_tarval_mode(tv);
100 if (! ia32_cg_config.use_sse2) {
101 /* try to reduce the mode to produce smaller sized entities */
102 if (mode != mode_F) {
103 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
105 tv = tarval_convert_to(tv, mode);
106 } else if (mode != mode_D) {
107 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
109 tv = tarval_convert_to(tv, mode);
115 tp = ia32_get_prim_type(isa->types, mode);
116 res = new_entity(get_glob_type(), id_unique("C%u"), tp);
117 set_entity_ld_ident(res, get_entity_ident(res));
118 set_entity_visibility(res, ir_visibility_private);
119 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
121 initializer = create_initializer_tarval(tv);
122 set_entity_initializer(res, initializer);
124 pmap_insert(isa->tv_ent, tv, res);
128 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
130 ir_graph *irg = current_ir_graph;
131 ir_node *start_block = get_irg_start_block(irg);
132 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
133 symconst_sign, ia32_no_pic_adjust, val);
134 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
139 const arch_register_t *ia32_get_clobber_register(const char *clobber)
141 const arch_register_t *reg = NULL;
144 const arch_register_class_t *cls;
146 /* TODO: construct a hashmap instead of doing linear search for clobber
148 for (c = 0; c < N_IA32_CLASSES; ++c) {
149 cls = & ia32_reg_classes[c];
150 for (r = 0; r < cls->n_regs; ++r) {
151 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
152 if (strcmp(temp_reg->name, clobber) == 0
153 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
165 int ia32_mode_needs_gp_reg(ir_mode *mode)
167 if (mode == ia32_mode_fpcw)
169 if (get_mode_size_bits(mode) > 32)
171 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
174 static void parse_asm_constraints(constraint_t *constraint, const char *c,
177 char immediate_type = '\0';
178 unsigned limited = 0;
179 const arch_register_class_t *cls = NULL;
180 int memory_possible = 0;
181 int all_registers_allowed = 0;
185 memset(constraint, 0, sizeof(constraint[0]));
186 constraint->same_as = -1;
189 /* a memory constraint: no need to do anything in backend about it
190 * (the dependencies are already respected by the memory edge of
195 /* TODO: improve error messages with node and source info. (As users can
196 * easily hit these) */
204 /* Skip out/in-out marker */
214 while (*c != 0 && *c != ',')
219 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
220 cls = &ia32_reg_classes[CLASS_ia32_gp];
221 limited |= 1 << REG_GP_EAX;
224 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
225 cls = &ia32_reg_classes[CLASS_ia32_gp];
226 limited |= 1 << REG_GP_EBX;
229 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
230 cls = &ia32_reg_classes[CLASS_ia32_gp];
231 limited |= 1 << REG_GP_ECX;
234 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
235 cls = &ia32_reg_classes[CLASS_ia32_gp];
236 limited |= 1 << REG_GP_EDX;
239 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
240 cls = &ia32_reg_classes[CLASS_ia32_gp];
241 limited |= 1 << REG_GP_EDI;
244 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
245 cls = &ia32_reg_classes[CLASS_ia32_gp];
246 limited |= 1 << REG_GP_ESI;
250 /* q means lower part of the regs only, this makes no
251 * difference to Q for us (we only assign whole registers) */
252 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
253 cls = &ia32_reg_classes[CLASS_ia32_gp];
254 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
258 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
259 cls = &ia32_reg_classes[CLASS_ia32_gp];
260 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
263 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
264 cls = &ia32_reg_classes[CLASS_ia32_gp];
265 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
266 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
273 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
274 panic("multiple register classes not supported");
275 cls = &ia32_reg_classes[CLASS_ia32_gp];
276 all_registers_allowed = 1;
282 /* TODO: mark values so the x87 simulator knows about t and u */
283 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
284 panic("multiple register classes not supported");
285 cls = &ia32_reg_classes[CLASS_ia32_vfp];
286 all_registers_allowed = 1;
291 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
292 panic("multiple register classes not supproted");
293 cls = &ia32_reg_classes[CLASS_ia32_xmm];
294 all_registers_allowed = 1;
304 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
305 panic("multiple register classes not supported");
306 if (immediate_type != '\0')
307 panic("multiple immediate types not supported");
308 cls = &ia32_reg_classes[CLASS_ia32_gp];
313 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
314 panic("multiple register classes not supported");
315 if (immediate_type != '\0')
316 panic("multiple immediate types not supported");
317 cls = &ia32_reg_classes[CLASS_ia32_gp];
318 immediate_type = 'i';
323 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
324 panic("multiple register classes not supported");
325 if (immediate_type != '\0')
326 panic("multiple immediate types not supported");
327 immediate_type = 'i';
328 cls = &ia32_reg_classes[CLASS_ia32_gp];
329 all_registers_allowed = 1;
344 panic("can only specify same constraint on input");
346 sscanf(c, "%d%n", &same_as, &p);
356 /* memory constraint no need to do anything in backend about it
357 * (the dependencies are already respected by the memory edge of
362 case 'E': /* no float consts yet */
363 case 'F': /* no float consts yet */
364 case 's': /* makes no sense on x86 */
365 case '<': /* no autodecrement on x86 */
366 case '>': /* no autoincrement on x86 */
367 case 'C': /* sse constant not supported yet */
368 case 'G': /* 80387 constant not supported yet */
369 case 'y': /* we don't support mmx registers yet */
370 case 'Z': /* not available in 32 bit mode */
371 case 'e': /* not available in 32 bit mode */
372 panic("unsupported asm constraint '%c' found in (%+F)",
373 *c, current_ir_graph);
375 panic("unknown asm constraint '%c' found in (%+F)", *c,
383 panic("same as and register constraint not supported");
384 if (immediate_type != '\0')
385 panic("same as and immediate constraint not supported");
388 if (cls == NULL && same_as < 0) {
389 if (!memory_possible)
390 panic("no constraint specified for assembler input");
393 constraint->same_as = same_as;
394 constraint->cls = cls;
395 constraint->allowed_registers = limited;
396 constraint->all_registers_allowed = all_registers_allowed;
397 constraint->memory_possible = memory_possible;
398 constraint->immediate_type = immediate_type;
401 static bool can_match(const arch_register_req_t *in,
402 const arch_register_req_t *out)
404 if (in->cls != out->cls)
406 if ( (in->type & arch_register_req_type_limited) == 0
407 || (out->type & arch_register_req_type_limited) == 0 )
410 return (*in->limited & *out->limited) != 0;
413 static inline ir_node *get_new_node(ir_node *node)
416 if (be_transformer == TRANSFORMER_DEFAULT) {
417 return be_transform_node(node);
422 return be_transform_node(node);
426 ir_node *ia32_gen_ASM(ir_node *node)
428 ir_node *block = get_nodes_block(node);
429 ir_node *new_block = get_new_node(block);
430 dbg_info *dbgi = get_irn_dbg_info(node);
437 int n_out_constraints;
439 const arch_register_req_t **out_reg_reqs;
440 const arch_register_req_t **in_reg_reqs;
441 ia32_asm_reg_t *register_map;
442 unsigned reg_map_size = 0;
443 struct obstack *obst;
444 const ir_asm_constraint *in_constraints;
445 const ir_asm_constraint *out_constraints;
447 unsigned clobber_bits[N_IA32_CLASSES];
449 backend_info_t *info;
451 memset(&clobber_bits, 0, sizeof(clobber_bits));
453 arity = get_irn_arity(node);
454 in = ALLOCANZ(ir_node*, arity);
456 clobbers = get_ASM_clobbers(node);
458 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
459 const arch_register_req_t *req;
460 const char *c = get_id_str(clobbers[i]);
462 if (strcmp(c, "memory") == 0)
464 if (strcmp(c, "cc") == 0) {
468 req = ia32_parse_clobber(c);
469 clobber_bits[req->cls->index] |= *req->limited;
473 n_out_constraints = get_ASM_n_output_constraints(node);
474 out_arity = n_out_constraints + n_clobbers;
476 in_constraints = get_ASM_input_constraints(node);
477 out_constraints = get_ASM_output_constraints(node);
479 /* determine size of register_map */
480 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
481 const ir_asm_constraint *constraint = &out_constraints[out_idx];
482 if (constraint->pos > reg_map_size)
483 reg_map_size = constraint->pos;
485 for (i = 0; i < arity; ++i) {
486 const ir_asm_constraint *constraint = &in_constraints[i];
487 if (constraint->pos > reg_map_size)
488 reg_map_size = constraint->pos;
492 obst = get_irg_obstack(current_ir_graph);
493 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
494 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
496 /* construct output constraints */
497 out_size = out_arity + 1;
498 out_reg_reqs = OALLOCN(obst, const arch_register_req_t*, out_size);
500 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
501 const ir_asm_constraint *constraint = &out_constraints[out_idx];
502 const char *c = get_id_str(constraint->constraint);
503 unsigned pos = constraint->pos;
504 constraint_t parsed_constraint;
505 const arch_register_req_t *req;
507 parse_asm_constraints(&parsed_constraint, c, 1);
508 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
509 out_reg_reqs, out_idx);
510 out_reg_reqs[out_idx] = req;
512 /* multiple constraints for same pos. This can happen for example when
513 * a =A constraint gets lowered to two constraints: =a and =d for the
515 if (register_map[pos].valid)
518 register_map[pos].use_input = 0;
519 register_map[pos].valid = 1;
520 register_map[pos].memory = 0;
521 register_map[pos].inout_pos = out_idx;
522 register_map[pos].mode = constraint->mode;
525 /* inputs + input constraints */
526 in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, arity);
527 for (i = 0; i < arity; ++i) {
528 ir_node *pred = get_irn_n(node, i);
529 const ir_asm_constraint *constraint = &in_constraints[i];
530 ident *constr_id = constraint->constraint;
531 const char *c = get_id_str(constr_id);
532 unsigned pos = constraint->pos;
533 int is_memory_op = 0;
534 ir_node *input = NULL;
535 unsigned r_clobber_bits;
536 constraint_t parsed_constraint;
537 const arch_register_req_t *req;
539 parse_asm_constraints(&parsed_constraint, c, 0);
540 if (parsed_constraint.cls != NULL) {
541 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
542 if (r_clobber_bits != 0) {
543 if (parsed_constraint.all_registers_allowed) {
544 parsed_constraint.all_registers_allowed = 0;
545 be_set_allocatable_regs(current_ir_graph,
546 parsed_constraint.cls,
547 &parsed_constraint.allowed_registers);
549 parsed_constraint.allowed_registers &= ~r_clobber_bits;
553 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
555 in_reg_reqs[i] = req;
557 if (parsed_constraint.immediate_type != '\0') {
558 char imm_type = parsed_constraint.immediate_type;
559 input = ia32_try_create_Immediate(pred, imm_type);
563 input = get_new_node(pred);
565 if (parsed_constraint.cls == NULL
566 && parsed_constraint.same_as < 0) {
568 } else if (parsed_constraint.memory_possible) {
569 /* TODO: match Load or Load/Store if memory possible is set */
574 register_map[pos].use_input = 1;
575 register_map[pos].valid = 1;
576 register_map[pos].memory = is_memory_op;
577 register_map[pos].inout_pos = i;
578 register_map[pos].mode = constraint->mode;
582 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
583 const char *c = get_id_str(clobbers[i]);
584 const arch_register_req_t *req;
586 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
589 req = ia32_parse_clobber(c);
590 out_reg_reqs[out_idx] = req;
594 /* count inputs which are real values (and not memory) */
596 for (i = 0; i < arity; ++i) {
597 ir_node *node_in = get_irn_n(node, i);
598 if (get_irn_mode(node_in) == mode_M)
603 /* Attempt to make ASM node register pressure faithful.
604 * (This does not work for complicated cases yet!)
606 * Algorithm: Check if there are fewer inputs or outputs (I will call this
607 * the smaller list). Then try to match each constraint of the smaller list
608 * to 1 of the other list. If we can't match it, then we have to add a dummy
609 * input/output to the other list
611 * FIXME: This is still broken in lots of cases. But at least better than
613 * FIXME: need to do this per register class...
615 if (out_arity <= value_arity) {
616 int orig_arity = arity;
619 bitset_t *used_ins = bitset_alloca(arity);
620 for (o = 0; o < out_arity; ++o) {
621 const arch_register_req_t *outreq = out_reg_reqs[o];
623 if (outreq->cls == NULL) {
627 for (i = 0; i < orig_arity; ++i) {
628 const arch_register_req_t *inreq;
629 if (bitset_is_set(used_ins, i))
631 inreq = in_reg_reqs[i];
632 if (!can_match(outreq, inreq))
634 bitset_set(used_ins, i);
637 /* did we find any match? */
641 /* we might need more space in the input arrays */
642 if (arity >= in_size) {
643 const arch_register_req_t **new_in_reg_reqs;
647 new_in_reg_reqs = OALLOCN(obst, const arch_register_req_t*,
649 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
650 new_in = ALLOCANZ(ir_node*, in_size);
651 memcpy(new_in, in, arity*sizeof(new_in[0]));
653 in_reg_reqs = new_in_reg_reqs;
657 /* add a new (dummy) input which occupies the register */
658 assert(outreq->type & arch_register_req_type_limited);
659 in_reg_reqs[arity] = outreq;
660 in[arity] = new_bd_ia32_ProduceVal(NULL, block);
664 bitset_t *used_outs = bitset_alloca(out_arity);
665 int orig_out_arity = out_arity;
666 for (i = 0; i < arity; ++i) {
668 const arch_register_req_t *inreq = in_reg_reqs[i];
670 if (inreq->cls == NULL) {
674 for (o = 0; o < orig_out_arity; ++o) {
675 const arch_register_req_t *outreq;
676 if (bitset_is_set(used_outs, o))
678 outreq = out_reg_reqs[o];
679 if (!can_match(outreq, inreq))
681 bitset_set(used_outs, i);
684 /* did we find any match? */
685 if (o < orig_out_arity)
688 /* we might need more space in the output arrays */
689 if (out_arity >= out_size) {
690 const arch_register_req_t **new_out_reg_reqs;
694 = OALLOCN(obst, const arch_register_req_t*, out_size);
695 memcpy(new_out_reg_reqs, out_reg_reqs,
696 out_arity * sizeof(new_out_reg_reqs[0]));
697 out_reg_reqs = new_out_reg_reqs;
700 /* add a new (dummy) output which occupies the register */
701 assert(inreq->type & arch_register_req_type_limited);
702 out_reg_reqs[out_arity] = inreq;
707 /* append none register requirement for the memory output */
708 if (out_arity + 1 >= out_size) {
709 const arch_register_req_t **new_out_reg_reqs;
711 out_size = out_arity + 1;
713 = OALLOCN(obst, const arch_register_req_t*, out_size);
714 memcpy(new_out_reg_reqs, out_reg_reqs,
715 out_arity * sizeof(new_out_reg_reqs[0]));
716 out_reg_reqs = new_out_reg_reqs;
719 /* add a new (dummy) output which occupies the register */
720 out_reg_reqs[out_arity] = arch_no_register_req;
723 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
724 get_ASM_text(node), register_map);
726 info = be_get_info(new_node);
727 for (i = 0; i < out_arity; ++i) {
728 info->out_infos[i].req = out_reg_reqs[i];
730 arch_set_in_register_reqs(new_node, in_reg_reqs);
732 SET_IA32_ORIG_NODE(new_node, node);
737 ir_node *ia32_gen_CopyB(ir_node *node)
739 ir_node *block = get_new_node(get_nodes_block(node));
740 ir_node *src = get_CopyB_src(node);
741 ir_node *new_src = get_new_node(src);
742 ir_node *dst = get_CopyB_dst(node);
743 ir_node *new_dst = get_new_node(dst);
744 ir_node *mem = get_CopyB_mem(node);
745 ir_node *new_mem = get_new_node(mem);
747 dbg_info *dbgi = get_irn_dbg_info(node);
748 int size = get_type_size_bytes(get_CopyB_type(node));
749 int throws_exception = ir_throws_exception(node);
752 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
753 /* then we need the size explicitly in ECX. */
754 if (size >= 32 * 4) {
755 rem = size & 0x3; /* size % 4 */
758 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
760 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
763 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
766 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
768 ir_set_throws_exception(res, throws_exception);
770 SET_IA32_ORIG_NODE(res, node);
775 ir_node *ia32_gen_Proj_tls(ir_node *node)
777 ir_node *block = get_new_node(get_nodes_block(node));
778 ir_node *res = new_bd_ia32_LdTls(NULL, block);
782 ir_node *ia32_gen_Unknown(ir_node *node)
784 ir_mode *mode = get_irn_mode(node);
785 ir_graph *irg = current_ir_graph;
786 dbg_info *dbgi = get_irn_dbg_info(node);
787 ir_node *block = get_irg_start_block(irg);
790 if (mode_is_float(mode)) {
791 if (ia32_cg_config.use_sse2) {
792 res = new_bd_ia32_xUnknown(dbgi, block);
794 res = new_bd_ia32_vfldz(dbgi, block);
796 } else if (ia32_mode_needs_gp_reg(mode)) {
797 res = new_bd_ia32_Unknown(dbgi, block);
799 panic("unsupported Unknown-Mode");
805 const arch_register_req_t *ia32_make_register_req(const constraint_t *constraint,
806 int n_outs, const arch_register_req_t **out_reqs, int pos)
808 struct obstack *obst = get_irg_obstack(current_ir_graph);
809 int same_as = constraint->same_as;
810 arch_register_req_t *req;
813 const arch_register_req_t *other_constr;
815 if (same_as >= n_outs)
816 panic("invalid output number in same_as constraint");
818 other_constr = out_reqs[same_as];
820 req = OALLOC(obst, arch_register_req_t);
821 *req = *other_constr;
822 req->type |= arch_register_req_type_should_be_same;
823 req->other_same = 1U << pos;
826 /* switch constraints. This is because in firm we have same_as
827 * constraints on the output constraints while in the gcc asm syntax
828 * they are specified on the input constraints */
829 out_reqs[same_as] = req;
833 /* pure memory ops */
834 if (constraint->cls == NULL) {
835 return arch_no_register_req;
838 if (constraint->allowed_registers != 0
839 && !constraint->all_registers_allowed) {
840 unsigned *limited_ptr;
842 req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
843 memset(req, 0, sizeof(req[0]));
844 limited_ptr = (unsigned*) (req+1);
846 req->type = arch_register_req_type_limited;
847 *limited_ptr = constraint->allowed_registers;
848 req->limited = limited_ptr;
850 req = OALLOCZ(obst, arch_register_req_t);
851 req->type = arch_register_req_type_normal;
853 req->cls = constraint->cls;
859 const arch_register_req_t *ia32_parse_clobber(const char *clobber)
861 struct obstack *obst = get_irg_obstack(current_ir_graph);
862 const arch_register_t *reg = ia32_get_clobber_register(clobber);
863 arch_register_req_t *req;
867 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
870 assert(reg->index < 32);
872 limited = OALLOC(obst, unsigned);
873 *limited = 1 << reg->index;
875 req = OALLOCZ(obst, arch_register_req_t);
876 req->type = arch_register_req_type_limited;
877 req->cls = arch_register_get_class(reg);
878 req->limited = limited;
885 int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
886 ir_node *const other)
888 if (get_nodes_block(other) != block)
891 if (is_Sync(other)) {
894 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
895 ir_node *const pred = get_Sync_pred(other, i);
897 if (get_nodes_block(pred) != block)
900 /* Do not block ourselves from getting eaten */
901 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
904 if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
912 /* Do not block ourselves from getting eaten */
913 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
916 if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
923 ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
926 ir_entity *symconst_ent = NULL;
928 ir_node *cnst = NULL;
929 ir_node *symconst = NULL;
932 mode = get_irn_mode(node);
933 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
937 if (is_Const(node)) {
940 } else if (is_SymConst_addr_ent(node)
941 && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
944 } else if (is_Add(node)) {
945 ir_node *left = get_Add_left(node);
946 ir_node *right = get_Add_right(node);
947 if (is_Const(left) && is_SymConst_addr_ent(right)) {
950 } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
959 ir_tarval *offset = get_Const_tarval(cnst);
960 if (!tarval_is_long(offset)) {
961 ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
965 val = get_tarval_long(offset);
966 if (!check_immediate_constraint(val, immediate_constraint_type))
969 if (symconst != NULL) {
970 if (immediate_constraint_type != 0) {
971 /* we need full 32bits for symconsts */
975 symconst_ent = get_Global_entity(symconst);
977 if (cnst == NULL && symconst == NULL)
980 new_node = ia32_create_Immediate(symconst_ent, 0, val);