2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
36 #include "ia32_architecture.h"
37 #include "ia32_common_transform.h"
38 #include "ia32_new_nodes.h"
40 #include "gen_ia32_new_nodes.h"
41 #include "gen_ia32_regalloc_if.h"
43 /** hold the current code generator during transformation */
44 ia32_code_gen_t *env_cg = NULL;
46 heights_t *heights = NULL;
48 static const arch_register_req_t no_register_req = {
49 arch_register_req_type_none,
51 NULL, /* limit bitset */
56 static int check_immediate_constraint(long val, char immediate_constraint_type)
58 switch (immediate_constraint_type) {
62 case 'I': return 0 <= val && val <= 31;
63 case 'J': return 0 <= val && val <= 63;
64 case 'K': return -128 <= val && val <= 127;
65 case 'L': return val == 0xff || val == 0xffff;
66 case 'M': return 0 <= val && val <= 3;
67 case 'N': return 0 <= val && val <= 255;
68 case 'O': return 0 <= val && val <= 127;
70 default: panic("Invalid immediate constraint found");
75 * creates a unique ident by adding a number to a tag
77 * @param tag the tag string, must contain a %d if a number
80 static ident *unique_id(const char *tag)
82 static unsigned id = 0;
85 snprintf(str, sizeof(str), tag, ++id);
86 return new_id_from_str(str);
90 * Get a primitive type for a mode.
92 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
94 pmap_entry *e = pmap_find(types, mode);
99 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
100 res = new_type_primitive(new_id_from_str(buf), mode);
101 set_type_alignment_bytes(res, 16);
102 pmap_insert(types, mode, res);
109 ir_entity *create_float_const_entity(ir_node *cnst)
111 ia32_isa_t *isa = env_cg->isa;
112 tarval *key = get_Const_tarval(cnst);
113 pmap_entry *e = pmap_find(isa->tv_ent, key);
119 ir_mode *mode = get_tarval_mode(tv);
122 if (! ia32_cg_config.use_sse2) {
123 /* try to reduce the mode to produce smaller sized entities */
124 if (mode != mode_F) {
125 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
127 tv = tarval_convert_to(tv, mode);
128 } else if (mode != mode_D) {
129 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
131 tv = tarval_convert_to(tv, mode);
137 if (mode == get_irn_mode(cnst)) {
138 /* mode was not changed */
139 tp = get_Const_type(cnst);
140 if (tp == firm_unknown_type)
141 tp = ia32_get_prim_type(isa->types, mode);
143 tp = ia32_get_prim_type(isa->types, mode);
145 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
147 set_entity_ld_ident(res, get_entity_ident(res));
148 set_entity_visibility(res, visibility_local);
149 set_entity_variability(res, variability_constant);
150 set_entity_allocation(res, allocation_static);
152 /* we create a new entity here: It's initialization must resist on the
154 rem = current_ir_graph;
155 current_ir_graph = get_const_code_irg();
156 set_atomic_ent_value(res, new_Const_type(tv, tp));
157 current_ir_graph = rem;
159 pmap_insert(isa->tv_ent, key, res);
167 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
169 ir_graph *irg = current_ir_graph;
170 ir_node *start_block = get_irg_start_block(irg);
171 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
172 symconst, symconst_sign, val);
173 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
178 const arch_register_t *ia32_get_clobber_register(const char *clobber)
180 const arch_register_t *reg = NULL;
183 const arch_register_class_t *cls;
185 /* TODO: construct a hashmap instead of doing linear search for clobber
187 for(c = 0; c < N_CLASSES; ++c) {
188 cls = & ia32_reg_classes[c];
189 for(r = 0; r < cls->n_regs; ++r) {
190 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
191 if(strcmp(temp_reg->name, clobber) == 0
192 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
205 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
206 ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
208 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
209 obstack_1grow(isa->name_obst, 0);
210 return obstack_finish(isa->name_obst);
214 int ia32_mode_needs_gp_reg(ir_mode *mode) {
215 if(mode == mode_fpcw)
217 if(get_mode_size_bits(mode) > 32)
219 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
222 static void parse_asm_constraints(constraint_t *constraint, const char *c,
225 asm_constraint_flags_t flags = 0;
226 char immediate_type = '\0';
227 unsigned limited = 0;
228 const arch_register_class_t *cls = NULL;
229 int memory_possible = 0;
230 int all_registers_allowed = 0;
234 memset(constraint, 0, sizeof(constraint[0]));
235 constraint->same_as = -1;
238 /* a memory constraint: no need to do anything in backend about it
239 * (the dependencies are already respected by the memory edge of
244 /* TODO: improve error messages with node and source info. (As users can
245 * easily hit these) */
254 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
255 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
259 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
260 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
267 while(*c != 0 && *c != ',')
272 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
273 cls = &ia32_reg_classes[CLASS_ia32_gp];
274 limited |= 1 << REG_EAX;
277 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
278 cls = &ia32_reg_classes[CLASS_ia32_gp];
279 limited |= 1 << REG_EBX;
282 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
283 cls = &ia32_reg_classes[CLASS_ia32_gp];
284 limited |= 1 << REG_ECX;
287 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
288 cls = &ia32_reg_classes[CLASS_ia32_gp];
289 limited |= 1 << REG_EDX;
292 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
293 cls = &ia32_reg_classes[CLASS_ia32_gp];
294 limited |= 1 << REG_EDI;
297 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
298 cls = &ia32_reg_classes[CLASS_ia32_gp];
299 limited |= 1 << REG_ESI;
303 /* q means lower part of the regs only, this makes no
304 * difference to Q for us (we only assign whole registers) */
305 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
306 cls = &ia32_reg_classes[CLASS_ia32_gp];
307 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
311 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
312 cls = &ia32_reg_classes[CLASS_ia32_gp];
313 limited |= 1 << REG_EAX | 1 << REG_EDX;
316 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
317 cls = &ia32_reg_classes[CLASS_ia32_gp];
318 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
319 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
326 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
327 panic("multiple register classes not supported");
328 cls = &ia32_reg_classes[CLASS_ia32_gp];
329 all_registers_allowed = 1;
335 /* TODO: mark values so the x87 simulator knows about t and u */
336 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
337 panic("multiple register classes not supported");
338 cls = &ia32_reg_classes[CLASS_ia32_vfp];
339 all_registers_allowed = 1;
344 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
345 panic("multiple register classes not supproted");
346 cls = &ia32_reg_classes[CLASS_ia32_xmm];
347 all_registers_allowed = 1;
357 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
358 panic("multiple register classes not supported");
359 if (immediate_type != '\0')
360 panic("multiple immediate types not supported");
361 cls = &ia32_reg_classes[CLASS_ia32_gp];
366 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
367 panic("multiple register classes not supported");
368 if (immediate_type != '\0')
369 panic("multiple immediate types not supported");
370 cls = &ia32_reg_classes[CLASS_ia32_gp];
371 immediate_type = 'i';
376 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
377 panic("multiple register classes not supported");
378 if (immediate_type != '\0')
379 panic("multiple immediate types not supported");
380 immediate_type = 'i';
381 cls = &ia32_reg_classes[CLASS_ia32_gp];
382 all_registers_allowed = 1;
397 panic("can only specify same constraint on input");
399 sscanf(c, "%d%n", &same_as, &p);
409 /* memory constraint no need to do anything in backend about it
410 * (the dependencies are already respected by the memory edge of
415 case 'E': /* no float consts yet */
416 case 'F': /* no float consts yet */
417 case 's': /* makes no sense on x86 */
418 case '<': /* no autodecrement on x86 */
419 case '>': /* no autoincrement on x86 */
420 case 'C': /* sse constant not supported yet */
421 case 'G': /* 80387 constant not supported yet */
422 case 'y': /* we don't support mmx registers yet */
423 case 'Z': /* not available in 32 bit mode */
424 case 'e': /* not available in 32 bit mode */
425 panic("unsupported asm constraint '%c' found in (%+F)",
426 *c, current_ir_graph);
429 panic("unknown asm constraint '%c' found in (%+F)", *c,
438 panic("same as and register constraint not supported");
439 if (immediate_type != '\0')
440 panic("same as and immediate constraint not supported");
443 if (cls == NULL && same_as < 0) {
444 if (!memory_possible)
445 panic("no constraint specified for assembler input");
448 constraint->same_as = same_as;
449 constraint->cls = cls;
450 constraint->allowed_registers = limited;
451 constraint->all_registers_allowed = all_registers_allowed;
452 constraint->memory_possible = memory_possible;
453 constraint->immediate_type = immediate_type;
456 ir_node *gen_ASM(ir_node *node)
458 ir_graph *irg = current_ir_graph;
459 ir_node *block = get_nodes_block(node);
460 ir_node *new_block = be_transform_node(block);
461 dbg_info *dbgi = get_irn_dbg_info(node);
467 int n_out_constraints;
469 const arch_register_req_t **out_reg_reqs;
470 const arch_register_req_t **in_reg_reqs;
471 ia32_asm_reg_t *register_map;
472 unsigned reg_map_size = 0;
473 struct obstack *obst;
474 const ir_asm_constraint *in_constraints;
475 const ir_asm_constraint *out_constraints;
477 int clobbers_flags = 0;
478 unsigned clobber_bits_gp = 0;
480 /* workaround for lots of buggy code out there as most people think volatile
481 * asm is enough for everything and forget the flags (linux kernel, etc.)
483 if (get_irn_pinned(node) == op_pin_state_pinned) {
487 arity = get_irn_arity(node);
488 in = alloca(arity * sizeof(in[0]));
489 memset(in, 0, arity * sizeof(in[0]));
491 clobbers = get_ASM_clobbers(node);
493 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
494 const arch_register_req_t *req;
495 const char *c = get_id_str(clobbers[i]);
497 if (strcmp(c, "memory") == 0)
499 if (strcmp(c, "cc") == 0) {
504 req = parse_clobber(c);
505 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp]) {
506 clobber_bits_gp |= *req->limited;
511 n_out_constraints = get_ASM_n_output_constraints(node);
512 out_arity = n_out_constraints + n_clobbers;
514 in_constraints = get_ASM_input_constraints(node);
515 out_constraints = get_ASM_output_constraints(node);
517 /* determine size of register_map */
518 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
519 const ir_asm_constraint *constraint = &out_constraints[out_idx];
520 if (constraint->pos > reg_map_size)
521 reg_map_size = constraint->pos;
523 for(i = 0; i < arity; ++i) {
524 const ir_asm_constraint *constraint = &in_constraints[i];
525 if(constraint->pos > reg_map_size)
526 reg_map_size = constraint->pos;
530 obst = get_irg_obstack(irg);
531 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
532 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
534 /* construct output constraints */
535 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
537 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
538 const ir_asm_constraint *constraint = &out_constraints[out_idx];
539 const char *c = get_id_str(constraint->constraint);
540 unsigned pos = constraint->pos;
541 constraint_t parsed_constraint;
542 const arch_register_req_t *req;
544 parse_asm_constraints(&parsed_constraint, c, 1);
545 req = make_register_req(&parsed_constraint, n_out_constraints,
546 out_reg_reqs, out_idx);
547 out_reg_reqs[out_idx] = req;
549 register_map[pos].use_input = 0;
550 register_map[pos].valid = 1;
551 register_map[pos].memory = 0;
552 register_map[pos].inout_pos = out_idx;
553 register_map[pos].mode = constraint->mode;
556 /* inputs + input constraints */
557 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
558 for(i = 0; i < arity; ++i) {
559 ir_node *pred = get_irn_n(node, i);
560 const ir_asm_constraint *constraint = &in_constraints[i];
561 ident *constr_id = constraint->constraint;
562 const char *c = get_id_str(constr_id);
563 unsigned pos = constraint->pos;
564 int is_memory_op = 0;
565 ir_node *input = NULL;
566 constraint_t parsed_constraint;
567 const arch_register_req_t *req;
569 parse_asm_constraints(&parsed_constraint, c, 0);
570 if (clobber_bits_gp != 0 &&
571 parsed_constraint.cls == &ia32_reg_classes[CLASS_ia32_gp]) {
572 if (parsed_constraint.all_registers_allowed) {
573 parsed_constraint.all_registers_allowed = 0;
574 parsed_constraint.allowed_registers =
583 parsed_constraint.allowed_registers &= ~clobber_bits_gp;
586 req = make_register_req(&parsed_constraint, n_out_constraints,
588 in_reg_reqs[i] = req;
590 if (parsed_constraint.immediate_type != '\0') {
591 char imm_type = parsed_constraint.immediate_type;
592 input = try_create_Immediate(pred, imm_type);
596 ir_node *pred = get_irn_n(node, i);
597 input = be_transform_node(pred);
599 if (parsed_constraint.cls == NULL
600 && parsed_constraint.same_as < 0) {
602 } else if(parsed_constraint.memory_possible) {
603 /* TODO: match Load or Load/Store if memory possible is set */
608 register_map[pos].use_input = 1;
609 register_map[pos].valid = 1;
610 register_map[pos].memory = is_memory_op;
611 register_map[pos].inout_pos = i;
612 register_map[pos].mode = constraint->mode;
616 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
617 const char *c = get_id_str(clobbers[i]);
618 const arch_register_req_t *req;
620 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
623 req = parse_clobber(c);
624 out_reg_reqs[out_idx] = req;
628 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
629 get_ASM_text(node), register_map);
631 set_ia32_out_req_all(new_node, out_reg_reqs);
632 set_ia32_in_req_all(new_node, in_reg_reqs);
634 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
639 ir_node *gen_Unknown(ir_node *node)
641 ir_mode *mode = get_irn_mode(node);
643 if (mode_is_float(mode)) {
644 if (ia32_cg_config.use_sse2) {
645 return ia32_new_Unknown_xmm(env_cg);
647 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
648 ir_graph *irg = current_ir_graph;
649 dbg_info *dbgi = get_irn_dbg_info(node);
650 ir_node *block = get_irg_start_block(irg);
651 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
653 /* Const Nodes before the initial IncSP are a bad idea, because
654 * they could be spilled and we have no SP ready at that point yet.
655 * So add a dependency to the initial frame pointer calculation to
656 * avoid that situation.
658 add_irn_dep(ret, get_irg_frame(irg));
661 } else if (ia32_mode_needs_gp_reg(mode)) {
662 return ia32_new_Unknown_gp(env_cg);
664 panic("unsupported Unknown-Mode");
669 const arch_register_req_t *make_register_req(const constraint_t *constraint,
670 int n_outs, const arch_register_req_t **out_reqs, int pos)
672 struct obstack *obst = get_irg_obstack(current_ir_graph);
673 int same_as = constraint->same_as;
674 arch_register_req_t *req;
677 const arch_register_req_t *other_constr;
679 if (same_as >= n_outs)
680 panic("invalid output number in same_as constraint");
682 other_constr = out_reqs[same_as];
684 req = obstack_alloc(obst, sizeof(req[0]));
685 req->cls = other_constr->cls;
686 req->type = arch_register_req_type_should_be_same;
688 req->other_same = 1U << pos;
689 req->other_different = 0;
691 /* switch constraints. This is because in firm we have same_as
692 * constraints on the output constraints while in the gcc asm syntax
693 * they are specified on the input constraints */
694 out_reqs[same_as] = req;
698 /* pure memory ops */
699 if (constraint->cls == NULL) {
700 return &no_register_req;
703 if (constraint->allowed_registers != 0
704 && !constraint->all_registers_allowed) {
705 unsigned *limited_ptr;
707 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
708 memset(req, 0, sizeof(req[0]));
709 limited_ptr = (unsigned*) (req+1);
711 req->type = arch_register_req_type_limited;
712 *limited_ptr = constraint->allowed_registers;
713 req->limited = limited_ptr;
715 req = obstack_alloc(obst, sizeof(req[0]));
716 memset(req, 0, sizeof(req[0]));
717 req->type = arch_register_req_type_normal;
719 req->cls = constraint->cls;
724 const arch_register_req_t *parse_clobber(const char *clobber)
726 struct obstack *obst = get_irg_obstack(current_ir_graph);
727 const arch_register_t *reg = ia32_get_clobber_register(clobber);
728 arch_register_req_t *req;
732 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
735 assert(reg->index < 32);
737 limited = obstack_alloc(obst, sizeof(limited[0]));
738 *limited = 1 << reg->index;
740 req = obstack_alloc(obst, sizeof(req[0]));
741 memset(req, 0, sizeof(req[0]));
742 req->type = arch_register_req_type_limited;
743 req->cls = arch_register_get_class(reg);
744 req->limited = limited;
749 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
752 tarval *offset = NULL;
755 ir_entity *symconst_ent = NULL;
756 int symconst_sign = 0;
758 ir_node *cnst = NULL;
759 ir_node *symconst = NULL;
762 mode = get_irn_mode(node);
763 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
769 node = get_Minus_op(node);
776 } else if(is_SymConst(node)) {
779 symconst_sign = minus;
780 } else if(is_Add(node)) {
781 ir_node *left = get_Add_left(node);
782 ir_node *right = get_Add_right(node);
783 if(is_Const(left) && is_SymConst(right)) {
786 symconst_sign = minus;
788 } else if(is_SymConst(left) && is_Const(right)) {
791 symconst_sign = minus;
794 } else if(is_Sub(node)) {
795 ir_node *left = get_Sub_left(node);
796 ir_node *right = get_Sub_right(node);
797 if(is_Const(left) && is_SymConst(right)) {
800 symconst_sign = !minus;
802 } else if(is_SymConst(left) && is_Const(right)) {
805 symconst_sign = minus;
806 offset_sign = !minus;
813 offset = get_Const_tarval(cnst);
814 if(tarval_is_long(offset)) {
815 val = get_tarval_long(offset);
817 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
822 if(!check_immediate_constraint(val, immediate_constraint_type))
825 if(symconst != NULL) {
826 if(immediate_constraint_type != 0) {
827 /* we need full 32bits for symconsts */
831 /* unfortunately the assembler/linker doesn't support -symconst */
835 if(get_SymConst_kind(symconst) != symconst_addr_ent)
837 symconst_ent = get_SymConst_entity(symconst);
839 if(cnst == NULL && symconst == NULL)
842 if(offset_sign && offset != NULL) {
843 offset = tarval_neg(offset);
846 new_node = create_Immediate(symconst_ent, symconst_sign, val);