2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
36 #include "../betranshlp.h"
40 #include "ia32_architecture.h"
41 #include "ia32_common_transform.h"
42 #include "ia32_new_nodes.h"
44 #include "gen_ia32_new_nodes.h"
45 #include "gen_ia32_regalloc_if.h"
47 /** hold the current code generator during transformation */
48 ia32_code_gen_t *env_cg = NULL;
50 ir_heights_t *heights = NULL;
52 static int check_immediate_constraint(long val, char immediate_constraint_type)
54 switch (immediate_constraint_type) {
58 case 'I': return 0 <= val && val <= 31;
59 case 'J': return 0 <= val && val <= 63;
60 case 'K': return -128 <= val && val <= 127;
61 case 'L': return val == 0xff || val == 0xffff;
62 case 'M': return 0 <= val && val <= 3;
63 case 'N': return 0 <= val && val <= 255;
64 case 'O': return 0 <= val && val <= 127;
66 default: panic("Invalid immediate constraint found");
71 * Get a primitive type for a mode with alignment 16.
73 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
75 ir_type *res = pmap_get(types, mode);
79 res = new_type_primitive(mode);
80 if (get_mode_size_bits(mode) >= 80) {
81 set_type_alignment_bytes(res, 16);
83 pmap_insert(types, mode, res);
87 ir_entity *create_float_const_entity(ir_node *cnst)
89 ia32_isa_t *isa = env_cg->isa;
90 tarval *tv = get_Const_tarval(cnst);
91 ir_entity *res = pmap_get(isa->tv_ent, tv);
92 ir_initializer_t *initializer;
99 mode = get_tarval_mode(tv);
101 if (! ia32_cg_config.use_sse2) {
102 /* try to reduce the mode to produce smaller sized entities */
103 if (mode != mode_F) {
104 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
106 tv = tarval_convert_to(tv, mode);
107 } else if (mode != mode_D) {
108 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
110 tv = tarval_convert_to(tv, mode);
116 tp = ia32_get_prim_type(isa->types, mode);
117 res = new_entity(get_glob_type(), id_unique("C%u"), tp);
118 set_entity_ld_ident(res, get_entity_ident(res));
119 set_entity_visibility(res, ir_visibility_private);
120 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
122 initializer = create_initializer_tarval(tv);
123 set_entity_initializer(res, initializer);
125 pmap_insert(isa->tv_ent, tv, res);
129 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
131 ir_graph *irg = current_ir_graph;
132 ir_node *start_block = get_irg_start_block(irg);
133 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
134 symconst_sign, no_pic_adjust, val);
135 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
140 const arch_register_t *ia32_get_clobber_register(const char *clobber)
142 const arch_register_t *reg = NULL;
145 const arch_register_class_t *cls;
147 /* TODO: construct a hashmap instead of doing linear search for clobber
149 for (c = 0; c < N_CLASSES; ++c) {
150 cls = & ia32_reg_classes[c];
151 for (r = 0; r < cls->n_regs; ++r) {
152 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
153 if (strcmp(temp_reg->name, clobber) == 0
154 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
166 int ia32_mode_needs_gp_reg(ir_mode *mode)
168 if (mode == mode_fpcw)
170 if (get_mode_size_bits(mode) > 32)
172 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
175 static void parse_asm_constraints(constraint_t *constraint, const char *c,
178 char immediate_type = '\0';
179 unsigned limited = 0;
180 const arch_register_class_t *cls = NULL;
181 int memory_possible = 0;
182 int all_registers_allowed = 0;
186 memset(constraint, 0, sizeof(constraint[0]));
187 constraint->same_as = -1;
190 /* a memory constraint: no need to do anything in backend about it
191 * (the dependencies are already respected by the memory edge of
196 /* TODO: improve error messages with node and source info. (As users can
197 * easily hit these) */
205 /* Skip out/in-out marker */
215 while (*c != 0 && *c != ',')
220 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
221 cls = &ia32_reg_classes[CLASS_ia32_gp];
222 limited |= 1 << REG_EAX;
225 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
226 cls = &ia32_reg_classes[CLASS_ia32_gp];
227 limited |= 1 << REG_EBX;
230 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
231 cls = &ia32_reg_classes[CLASS_ia32_gp];
232 limited |= 1 << REG_ECX;
235 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
236 cls = &ia32_reg_classes[CLASS_ia32_gp];
237 limited |= 1 << REG_EDX;
240 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
241 cls = &ia32_reg_classes[CLASS_ia32_gp];
242 limited |= 1 << REG_EDI;
245 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
246 cls = &ia32_reg_classes[CLASS_ia32_gp];
247 limited |= 1 << REG_ESI;
251 /* q means lower part of the regs only, this makes no
252 * difference to Q for us (we only assign whole registers) */
253 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
254 cls = &ia32_reg_classes[CLASS_ia32_gp];
255 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
259 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
260 cls = &ia32_reg_classes[CLASS_ia32_gp];
261 limited |= 1 << REG_EAX | 1 << REG_EDX;
264 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
265 cls = &ia32_reg_classes[CLASS_ia32_gp];
266 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
267 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
274 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
275 panic("multiple register classes not supported");
276 cls = &ia32_reg_classes[CLASS_ia32_gp];
277 all_registers_allowed = 1;
283 /* TODO: mark values so the x87 simulator knows about t and u */
284 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
285 panic("multiple register classes not supported");
286 cls = &ia32_reg_classes[CLASS_ia32_vfp];
287 all_registers_allowed = 1;
292 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
293 panic("multiple register classes not supproted");
294 cls = &ia32_reg_classes[CLASS_ia32_xmm];
295 all_registers_allowed = 1;
305 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
306 panic("multiple register classes not supported");
307 if (immediate_type != '\0')
308 panic("multiple immediate types not supported");
309 cls = &ia32_reg_classes[CLASS_ia32_gp];
314 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
315 panic("multiple register classes not supported");
316 if (immediate_type != '\0')
317 panic("multiple immediate types not supported");
318 cls = &ia32_reg_classes[CLASS_ia32_gp];
319 immediate_type = 'i';
324 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
325 panic("multiple register classes not supported");
326 if (immediate_type != '\0')
327 panic("multiple immediate types not supported");
328 immediate_type = 'i';
329 cls = &ia32_reg_classes[CLASS_ia32_gp];
330 all_registers_allowed = 1;
345 panic("can only specify same constraint on input");
347 sscanf(c, "%d%n", &same_as, &p);
357 /* memory constraint no need to do anything in backend about it
358 * (the dependencies are already respected by the memory edge of
363 case 'E': /* no float consts yet */
364 case 'F': /* no float consts yet */
365 case 's': /* makes no sense on x86 */
366 case '<': /* no autodecrement on x86 */
367 case '>': /* no autoincrement on x86 */
368 case 'C': /* sse constant not supported yet */
369 case 'G': /* 80387 constant not supported yet */
370 case 'y': /* we don't support mmx registers yet */
371 case 'Z': /* not available in 32 bit mode */
372 case 'e': /* not available in 32 bit mode */
373 panic("unsupported asm constraint '%c' found in (%+F)",
374 *c, current_ir_graph);
377 panic("unknown asm constraint '%c' found in (%+F)", *c,
386 panic("same as and register constraint not supported");
387 if (immediate_type != '\0')
388 panic("same as and immediate constraint not supported");
391 if (cls == NULL && same_as < 0) {
392 if (!memory_possible)
393 panic("no constraint specified for assembler input");
396 constraint->same_as = same_as;
397 constraint->cls = cls;
398 constraint->allowed_registers = limited;
399 constraint->all_registers_allowed = all_registers_allowed;
400 constraint->memory_possible = memory_possible;
401 constraint->immediate_type = immediate_type;
404 static bool can_match(const arch_register_req_t *in,
405 const arch_register_req_t *out)
407 if (in->cls != out->cls)
409 if ( (in->type & arch_register_req_type_limited) == 0
410 || (out->type & arch_register_req_type_limited) == 0 )
413 return (*in->limited & *out->limited) != 0;
416 static inline ir_node *get_new_node(ir_node *node)
419 if (be_transformer == TRANSFORMER_DEFAULT) {
420 return be_transform_node(node);
425 return be_transform_node(node);
429 ir_node *gen_ASM(ir_node *node)
431 ir_node *block = get_nodes_block(node);
432 ir_node *new_block = get_new_node(block);
433 dbg_info *dbgi = get_irn_dbg_info(node);
440 int n_out_constraints;
442 const arch_register_req_t **out_reg_reqs;
443 const arch_register_req_t **in_reg_reqs;
444 ia32_asm_reg_t *register_map;
445 unsigned reg_map_size = 0;
446 struct obstack *obst;
447 const ir_asm_constraint *in_constraints;
448 const ir_asm_constraint *out_constraints;
450 int clobbers_flags = 0;
451 unsigned clobber_bits[N_CLASSES];
453 backend_info_t *info;
455 memset(&clobber_bits, 0, sizeof(clobber_bits));
457 /* workaround for lots of buggy code out there as most people think volatile
458 * asm is enough for everything and forget the flags (linux kernel, etc.)
460 if (get_irn_pinned(node) == op_pin_state_pinned) {
464 arity = get_irn_arity(node);
465 in = ALLOCANZ(ir_node*, arity);
467 clobbers = get_ASM_clobbers(node);
469 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
470 const arch_register_req_t *req;
471 const char *c = get_id_str(clobbers[i]);
473 if (strcmp(c, "memory") == 0)
475 if (strcmp(c, "cc") == 0) {
480 req = parse_clobber(c);
481 clobber_bits[req->cls->index] |= *req->limited;
485 n_out_constraints = get_ASM_n_output_constraints(node);
486 out_arity = n_out_constraints + n_clobbers;
488 in_constraints = get_ASM_input_constraints(node);
489 out_constraints = get_ASM_output_constraints(node);
491 /* determine size of register_map */
492 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
493 const ir_asm_constraint *constraint = &out_constraints[out_idx];
494 if (constraint->pos > reg_map_size)
495 reg_map_size = constraint->pos;
497 for (i = 0; i < arity; ++i) {
498 const ir_asm_constraint *constraint = &in_constraints[i];
499 if (constraint->pos > reg_map_size)
500 reg_map_size = constraint->pos;
504 obst = get_irg_obstack(current_ir_graph);
505 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
506 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
508 /* construct output constraints */
509 out_size = out_arity + 1;
510 out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
512 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
513 const ir_asm_constraint *constraint = &out_constraints[out_idx];
514 const char *c = get_id_str(constraint->constraint);
515 unsigned pos = constraint->pos;
516 constraint_t parsed_constraint;
517 const arch_register_req_t *req;
519 parse_asm_constraints(&parsed_constraint, c, 1);
520 req = make_register_req(&parsed_constraint, n_out_constraints,
521 out_reg_reqs, out_idx);
522 out_reg_reqs[out_idx] = req;
524 register_map[pos].use_input = 0;
525 register_map[pos].valid = 1;
526 register_map[pos].memory = 0;
527 register_map[pos].inout_pos = out_idx;
528 register_map[pos].mode = constraint->mode;
531 /* inputs + input constraints */
532 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
533 for (i = 0; i < arity; ++i) {
534 ir_node *pred = get_irn_n(node, i);
535 const ir_asm_constraint *constraint = &in_constraints[i];
536 ident *constr_id = constraint->constraint;
537 const char *c = get_id_str(constr_id);
538 unsigned pos = constraint->pos;
539 int is_memory_op = 0;
540 ir_node *input = NULL;
541 unsigned r_clobber_bits;
542 constraint_t parsed_constraint;
543 const arch_register_req_t *req;
545 parse_asm_constraints(&parsed_constraint, c, 0);
546 if (parsed_constraint.cls != NULL) {
547 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
548 if (r_clobber_bits != 0) {
549 if (parsed_constraint.all_registers_allowed) {
550 parsed_constraint.all_registers_allowed = 0;
551 be_abi_set_non_ignore_regs(be_get_irg_abi(env_cg->irg),
552 parsed_constraint.cls,
553 &parsed_constraint.allowed_registers);
555 parsed_constraint.allowed_registers &= ~r_clobber_bits;
559 req = make_register_req(&parsed_constraint, n_out_constraints,
561 in_reg_reqs[i] = req;
563 if (parsed_constraint.immediate_type != '\0') {
564 char imm_type = parsed_constraint.immediate_type;
565 input = try_create_Immediate(pred, imm_type);
569 ir_node *pred = get_irn_n(node, i);
570 input = get_new_node(pred);
572 if (parsed_constraint.cls == NULL
573 && parsed_constraint.same_as < 0) {
575 } else if (parsed_constraint.memory_possible) {
576 /* TODO: match Load or Load/Store if memory possible is set */
581 register_map[pos].use_input = 1;
582 register_map[pos].valid = 1;
583 register_map[pos].memory = is_memory_op;
584 register_map[pos].inout_pos = i;
585 register_map[pos].mode = constraint->mode;
589 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
590 const char *c = get_id_str(clobbers[i]);
591 const arch_register_req_t *req;
593 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
596 req = parse_clobber(c);
597 out_reg_reqs[out_idx] = req;
601 /* count inputs which are real values (and not memory) */
603 for (i = 0; i < arity; ++i) {
604 ir_node *in = get_irn_n(node, i);
605 if (get_irn_mode(in) == mode_M)
610 /* Attempt to make ASM node register pressure faithful.
611 * (This does not work for complicated cases yet!)
613 * Algorithm: Check if there are fewer inputs or outputs (I will call this
614 * the smaller list). Then try to match each constraint of the smaller list
615 * to 1 of the other list. If we can't match it, then we have to add a dummy
616 * input/output to the other list
618 * FIXME: This is still broken in lots of cases. But at least better than
620 * FIXME: need to do this per register class...
622 if (out_arity <= value_arity) {
623 int orig_arity = arity;
626 bitset_t *used_ins = bitset_alloca(arity);
627 for (o = 0; o < out_arity; ++o) {
629 const arch_register_req_t *outreq = out_reg_reqs[o];
631 if (outreq->cls == NULL) {
635 for (i = 0; i < orig_arity; ++i) {
636 const arch_register_req_t *inreq;
637 if (bitset_is_set(used_ins, i))
639 inreq = in_reg_reqs[i];
640 if (!can_match(outreq, inreq))
642 bitset_set(used_ins, i);
645 /* did we find any match? */
649 /* we might need more space in the input arrays */
650 if (arity >= in_size) {
651 const arch_register_req_t **new_in_reg_reqs;
656 = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
657 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
658 new_in = ALLOCANZ(ir_node*, in_size);
659 memcpy(new_in, in, arity*sizeof(new_in[0]));
661 in_reg_reqs = new_in_reg_reqs;
665 /* add a new (dummy) input which occupies the register */
666 assert(outreq->type & arch_register_req_type_limited);
667 in_reg_reqs[arity] = outreq;
668 in[arity] = new_bd_ia32_ProduceVal(NULL, block);
669 be_dep_on_frame(in[arity]);
674 bitset_t *used_outs = bitset_alloca(out_arity);
675 int orig_out_arity = out_arity;
676 for (i = 0; i < arity; ++i) {
678 const arch_register_req_t *inreq = in_reg_reqs[i];
680 if (inreq->cls == NULL) {
684 for (o = 0; o < orig_out_arity; ++o) {
685 const arch_register_req_t *outreq;
686 if (bitset_is_set(used_outs, o))
688 outreq = out_reg_reqs[o];
689 if (!can_match(outreq, inreq))
691 bitset_set(used_outs, i);
694 /* did we find any match? */
695 if (o < orig_out_arity)
698 /* we might need more space in the output arrays */
699 if (out_arity >= out_size) {
700 const arch_register_req_t **new_out_reg_reqs;
704 = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
705 memcpy(new_out_reg_reqs, out_reg_reqs,
706 out_arity * sizeof(new_out_reg_reqs[0]));
707 out_reg_reqs = new_out_reg_reqs;
710 /* add a new (dummy) output which occupies the register */
711 assert(inreq->type & arch_register_req_type_limited);
712 out_reg_reqs[out_arity] = inreq;
717 /* append none register requirement for the memory output */
718 if (out_arity + 1 >= out_size) {
719 const arch_register_req_t **new_out_reg_reqs;
721 out_size = out_arity + 1;
723 = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
724 memcpy(new_out_reg_reqs, out_reg_reqs,
725 out_arity * sizeof(new_out_reg_reqs[0]));
726 out_reg_reqs = new_out_reg_reqs;
729 /* add a new (dummy) output which occupies the register */
730 out_reg_reqs[out_arity] = arch_no_register_req;
733 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
734 get_ASM_text(node), register_map);
737 be_dep_on_frame(new_node);
739 info = be_get_info(new_node);
740 for (i = 0; i < out_arity; ++i) {
741 info->out_infos[i].req = out_reg_reqs[i];
743 set_ia32_in_req_all(new_node, in_reg_reqs);
745 SET_IA32_ORIG_NODE(new_node, node);
750 ir_node *gen_CopyB(ir_node *node)
752 ir_node *block = get_new_node(get_nodes_block(node));
753 ir_node *src = get_CopyB_src(node);
754 ir_node *new_src = get_new_node(src);
755 ir_node *dst = get_CopyB_dst(node);
756 ir_node *new_dst = get_new_node(dst);
757 ir_node *mem = get_CopyB_mem(node);
758 ir_node *new_mem = get_new_node(mem);
760 dbg_info *dbgi = get_irn_dbg_info(node);
761 int size = get_type_size_bytes(get_CopyB_type(node));
764 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
765 /* then we need the size explicitly in ECX. */
766 if (size >= 32 * 4) {
767 rem = size & 0x3; /* size % 4 */
770 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
771 be_dep_on_frame(res);
773 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
776 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
779 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
782 SET_IA32_ORIG_NODE(res, node);
787 ir_node *gen_Proj_tls(ir_node *node)
789 ir_node *block = get_new_node(get_nodes_block(node));
792 res = new_bd_ia32_LdTls(NULL, block, mode_Iu);
797 ir_node *gen_Unknown(ir_node *node)
799 ir_mode *mode = get_irn_mode(node);
800 ir_graph *irg = current_ir_graph;
801 dbg_info *dbgi = get_irn_dbg_info(node);
802 ir_node *block = get_irg_start_block(irg);
805 if (mode_is_float(mode)) {
806 if (ia32_cg_config.use_sse2) {
807 res = new_bd_ia32_xUnknown(dbgi, block);
809 res = new_bd_ia32_vfldz(dbgi, block);
811 } else if (ia32_mode_needs_gp_reg(mode)) {
812 res = new_bd_ia32_Unknown(dbgi, block);
814 panic("unsupported Unknown-Mode");
817 be_dep_on_frame(res);
821 const arch_register_req_t *make_register_req(const constraint_t *constraint,
822 int n_outs, const arch_register_req_t **out_reqs, int pos)
824 struct obstack *obst = get_irg_obstack(current_ir_graph);
825 int same_as = constraint->same_as;
826 arch_register_req_t *req;
829 const arch_register_req_t *other_constr;
831 if (same_as >= n_outs)
832 panic("invalid output number in same_as constraint");
834 other_constr = out_reqs[same_as];
836 req = obstack_alloc(obst, sizeof(req[0]));
837 *req = *other_constr;
838 req->type |= arch_register_req_type_should_be_same;
839 req->other_same = 1U << pos;
842 /* switch constraints. This is because in firm we have same_as
843 * constraints on the output constraints while in the gcc asm syntax
844 * they are specified on the input constraints */
845 out_reqs[same_as] = req;
849 /* pure memory ops */
850 if (constraint->cls == NULL) {
851 return arch_no_register_req;
854 if (constraint->allowed_registers != 0
855 && !constraint->all_registers_allowed) {
856 unsigned *limited_ptr;
858 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
859 memset(req, 0, sizeof(req[0]));
860 limited_ptr = (unsigned*) (req+1);
862 req->type = arch_register_req_type_limited;
863 *limited_ptr = constraint->allowed_registers;
864 req->limited = limited_ptr;
866 req = obstack_alloc(obst, sizeof(req[0]));
867 memset(req, 0, sizeof(req[0]));
868 req->type = arch_register_req_type_normal;
870 req->cls = constraint->cls;
876 const arch_register_req_t *parse_clobber(const char *clobber)
878 struct obstack *obst = get_irg_obstack(current_ir_graph);
879 const arch_register_t *reg = ia32_get_clobber_register(clobber);
880 arch_register_req_t *req;
884 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
887 assert(reg->index < 32);
889 limited = obstack_alloc(obst, sizeof(limited[0]));
890 *limited = 1 << reg->index;
892 req = obstack_alloc(obst, sizeof(req[0]));
893 memset(req, 0, sizeof(req[0]));
894 req->type = arch_register_req_type_limited;
895 req->cls = arch_register_get_class(reg);
896 req->limited = limited;
903 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
904 ir_node *const other)
906 if (get_nodes_block(other) != block)
909 if (is_Sync(other)) {
912 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
913 ir_node *const pred = get_Sync_pred(other, i);
915 if (get_nodes_block(pred) != block)
918 /* Do not block ourselves from getting eaten */
919 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
922 if (!heights_reachable_in_block(heights, pred, am_candidate))
930 /* Do not block ourselves from getting eaten */
931 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
934 if (!heights_reachable_in_block(heights, other, am_candidate))
941 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
944 ir_entity *symconst_ent = NULL;
946 ir_node *cnst = NULL;
947 ir_node *symconst = NULL;
950 mode = get_irn_mode(node);
951 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
955 if (is_Const(node)) {
958 } else if (is_Global(node)) {
961 } else if (is_Add(node)) {
962 ir_node *left = get_Add_left(node);
963 ir_node *right = get_Add_right(node);
964 if (is_Const(left) && is_Global(right)) {
967 } else if (is_Global(left) && is_Const(right)) {
976 tarval *offset = get_Const_tarval(cnst);
977 if (!tarval_is_long(offset)) {
978 ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
982 val = get_tarval_long(offset);
983 if (!check_immediate_constraint(val, immediate_constraint_type))
986 if (symconst != NULL) {
987 if (immediate_constraint_type != 0) {
988 /* we need full 32bits for symconsts */
992 symconst_ent = get_Global_entity(symconst);
994 if (cnst == NULL && symconst == NULL)
997 new_node = ia32_create_Immediate(symconst_ent, 0, val);