2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
35 #include "../betranshlp.h"
36 #include "../beirg_t.h"
38 #include "ia32_architecture.h"
39 #include "ia32_common_transform.h"
40 #include "ia32_new_nodes.h"
42 #include "gen_ia32_new_nodes.h"
43 #include "gen_ia32_regalloc_if.h"
45 /** hold the current code generator during transformation */
46 ia32_code_gen_t *env_cg = NULL;
48 heights_t *heights = NULL;
50 static const arch_register_req_t no_register_req = {
51 arch_register_req_type_none,
53 NULL, /* limit bitset */
58 static int check_immediate_constraint(long val, char immediate_constraint_type)
60 switch (immediate_constraint_type) {
64 case 'I': return 0 <= val && val <= 31;
65 case 'J': return 0 <= val && val <= 63;
66 case 'K': return -128 <= val && val <= 127;
67 case 'L': return val == 0xff || val == 0xffff;
68 case 'M': return 0 <= val && val <= 3;
69 case 'N': return 0 <= val && val <= 255;
70 case 'O': return 0 <= val && val <= 127;
72 default: panic("Invalid immediate constraint found");
77 * creates a unique ident by adding a number to a tag
79 * @param tag the tag string, must contain a %d if a number
82 static ident *unique_id(const char *tag)
84 static unsigned id = 0;
87 snprintf(str, sizeof(str), tag, ++id);
88 return new_id_from_str(str);
92 * Get a primitive type for a mode.
94 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
96 pmap_entry *e = pmap_find(types, mode);
101 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
102 res = new_type_primitive(new_id_from_str(buf), mode);
103 set_type_alignment_bytes(res, 16);
104 pmap_insert(types, mode, res);
111 ir_entity *create_float_const_entity(ir_node *cnst)
113 ia32_isa_t *isa = env_cg->isa;
114 tarval *key = get_Const_tarval(cnst);
115 pmap_entry *e = pmap_find(isa->tv_ent, key);
121 ir_mode *mode = get_tarval_mode(tv);
124 if (! ia32_cg_config.use_sse2) {
125 /* try to reduce the mode to produce smaller sized entities */
126 if (mode != mode_F) {
127 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
129 tv = tarval_convert_to(tv, mode);
130 } else if (mode != mode_D) {
131 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
133 tv = tarval_convert_to(tv, mode);
139 if (mode == get_irn_mode(cnst)) {
140 /* mode was not changed */
141 tp = get_Const_type(cnst);
142 if (tp == firm_unknown_type)
143 tp = ia32_get_prim_type(isa->types, mode);
145 tp = ia32_get_prim_type(isa->types, mode);
147 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
149 set_entity_ld_ident(res, get_entity_ident(res));
150 set_entity_visibility(res, visibility_local);
151 set_entity_variability(res, variability_constant);
152 set_entity_allocation(res, allocation_static);
154 /* we create a new entity here: It's initialization must resist on the
156 rem = current_ir_graph;
157 current_ir_graph = get_const_code_irg();
158 set_atomic_ent_value(res, new_Const_type(tv, tp));
159 current_ir_graph = rem;
161 pmap_insert(isa->tv_ent, key, res);
169 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
171 ir_graph *irg = current_ir_graph;
172 ir_node *start_block = get_irg_start_block(irg);
173 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
174 symconst, symconst_sign, val);
175 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
180 const arch_register_t *ia32_get_clobber_register(const char *clobber)
182 const arch_register_t *reg = NULL;
185 const arch_register_class_t *cls;
187 /* TODO: construct a hashmap instead of doing linear search for clobber
189 for(c = 0; c < N_CLASSES; ++c) {
190 cls = & ia32_reg_classes[c];
191 for(r = 0; r < cls->n_regs; ++r) {
192 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
193 if(strcmp(temp_reg->name, clobber) == 0
194 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
207 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
208 const ia32_isa_t *isa = cg->isa;
210 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
211 obstack_1grow(isa->name_obst, 0);
212 return obstack_finish(isa->name_obst);
216 int ia32_mode_needs_gp_reg(ir_mode *mode) {
217 if(mode == mode_fpcw)
219 if(get_mode_size_bits(mode) > 32)
221 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
224 static void parse_asm_constraints(constraint_t *constraint, const char *c,
227 char immediate_type = '\0';
228 unsigned limited = 0;
229 const arch_register_class_t *cls = NULL;
230 int memory_possible = 0;
231 int all_registers_allowed = 0;
235 memset(constraint, 0, sizeof(constraint[0]));
236 constraint->same_as = -1;
239 /* a memory constraint: no need to do anything in backend about it
240 * (the dependencies are already respected by the memory edge of
245 /* TODO: improve error messages with node and source info. (As users can
246 * easily hit these) */
254 /* Skip out/in-out marker */
262 while(*c != 0 && *c != ',')
267 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
268 cls = &ia32_reg_classes[CLASS_ia32_gp];
269 limited |= 1 << REG_EAX;
272 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
273 cls = &ia32_reg_classes[CLASS_ia32_gp];
274 limited |= 1 << REG_EBX;
277 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
278 cls = &ia32_reg_classes[CLASS_ia32_gp];
279 limited |= 1 << REG_ECX;
282 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
283 cls = &ia32_reg_classes[CLASS_ia32_gp];
284 limited |= 1 << REG_EDX;
287 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
288 cls = &ia32_reg_classes[CLASS_ia32_gp];
289 limited |= 1 << REG_EDI;
292 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
293 cls = &ia32_reg_classes[CLASS_ia32_gp];
294 limited |= 1 << REG_ESI;
298 /* q means lower part of the regs only, this makes no
299 * difference to Q for us (we only assign whole registers) */
300 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
301 cls = &ia32_reg_classes[CLASS_ia32_gp];
302 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
306 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
307 cls = &ia32_reg_classes[CLASS_ia32_gp];
308 limited |= 1 << REG_EAX | 1 << REG_EDX;
311 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
312 cls = &ia32_reg_classes[CLASS_ia32_gp];
313 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
314 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
321 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
322 panic("multiple register classes not supported");
323 cls = &ia32_reg_classes[CLASS_ia32_gp];
324 all_registers_allowed = 1;
330 /* TODO: mark values so the x87 simulator knows about t and u */
331 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
332 panic("multiple register classes not supported");
333 cls = &ia32_reg_classes[CLASS_ia32_vfp];
334 all_registers_allowed = 1;
339 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
340 panic("multiple register classes not supproted");
341 cls = &ia32_reg_classes[CLASS_ia32_xmm];
342 all_registers_allowed = 1;
352 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
353 panic("multiple register classes not supported");
354 if (immediate_type != '\0')
355 panic("multiple immediate types not supported");
356 cls = &ia32_reg_classes[CLASS_ia32_gp];
361 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
362 panic("multiple register classes not supported");
363 if (immediate_type != '\0')
364 panic("multiple immediate types not supported");
365 cls = &ia32_reg_classes[CLASS_ia32_gp];
366 immediate_type = 'i';
371 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
372 panic("multiple register classes not supported");
373 if (immediate_type != '\0')
374 panic("multiple immediate types not supported");
375 immediate_type = 'i';
376 cls = &ia32_reg_classes[CLASS_ia32_gp];
377 all_registers_allowed = 1;
392 panic("can only specify same constraint on input");
394 sscanf(c, "%d%n", &same_as, &p);
404 /* memory constraint no need to do anything in backend about it
405 * (the dependencies are already respected by the memory edge of
410 case 'E': /* no float consts yet */
411 case 'F': /* no float consts yet */
412 case 's': /* makes no sense on x86 */
413 case '<': /* no autodecrement on x86 */
414 case '>': /* no autoincrement on x86 */
415 case 'C': /* sse constant not supported yet */
416 case 'G': /* 80387 constant not supported yet */
417 case 'y': /* we don't support mmx registers yet */
418 case 'Z': /* not available in 32 bit mode */
419 case 'e': /* not available in 32 bit mode */
420 panic("unsupported asm constraint '%c' found in (%+F)",
421 *c, current_ir_graph);
424 panic("unknown asm constraint '%c' found in (%+F)", *c,
433 panic("same as and register constraint not supported");
434 if (immediate_type != '\0')
435 panic("same as and immediate constraint not supported");
438 if (cls == NULL && same_as < 0) {
439 if (!memory_possible)
440 panic("no constraint specified for assembler input");
443 constraint->same_as = same_as;
444 constraint->cls = cls;
445 constraint->allowed_registers = limited;
446 constraint->all_registers_allowed = all_registers_allowed;
447 constraint->memory_possible = memory_possible;
448 constraint->immediate_type = immediate_type;
451 ir_node *gen_ASM(ir_node *node)
453 ir_graph *irg = current_ir_graph;
454 ir_node *block = NULL;
455 ir_node *new_block = NULL;
456 dbg_info *dbgi = get_irn_dbg_info(node);
462 int n_out_constraints;
464 const arch_register_req_t **out_reg_reqs;
465 const arch_register_req_t **in_reg_reqs;
466 ia32_asm_reg_t *register_map;
467 unsigned reg_map_size = 0;
468 struct obstack *obst;
469 const ir_asm_constraint *in_constraints;
470 const ir_asm_constraint *out_constraints;
472 int clobbers_flags = 0;
473 unsigned clobber_bits[N_CLASSES];
475 memset(&clobber_bits, 0, sizeof(clobber_bits));
477 switch (be_transformer) {
478 case TRANSFORMER_DEFAULT:
479 block = get_nodes_block(node);
480 new_block = be_transform_node(block);
484 case TRANSFORMER_PBQP:
485 case TRANSFORMER_RAND:
486 new_block = get_nodes_block(node);
491 panic("invalid transformer");
494 /* workaround for lots of buggy code out there as most people think volatile
495 * asm is enough for everything and forget the flags (linux kernel, etc.)
497 if (get_irn_pinned(node) == op_pin_state_pinned) {
501 arity = get_irn_arity(node);
502 in = alloca(arity * sizeof(in[0]));
503 memset(in, 0, arity * sizeof(in[0]));
505 clobbers = get_ASM_clobbers(node);
507 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
508 const arch_register_req_t *req;
509 const char *c = get_id_str(clobbers[i]);
511 if (strcmp(c, "memory") == 0)
513 if (strcmp(c, "cc") == 0) {
518 req = parse_clobber(c);
519 clobber_bits[req->cls->index] |= *req->limited;
523 n_out_constraints = get_ASM_n_output_constraints(node);
524 out_arity = n_out_constraints + n_clobbers;
526 in_constraints = get_ASM_input_constraints(node);
527 out_constraints = get_ASM_output_constraints(node);
529 /* determine size of register_map */
530 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
531 const ir_asm_constraint *constraint = &out_constraints[out_idx];
532 if (constraint->pos > reg_map_size)
533 reg_map_size = constraint->pos;
535 for (i = 0; i < arity; ++i) {
536 const ir_asm_constraint *constraint = &in_constraints[i];
537 if(constraint->pos > reg_map_size)
538 reg_map_size = constraint->pos;
542 obst = get_irg_obstack(irg);
543 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
544 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
546 /* construct output constraints */
547 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
549 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
550 const ir_asm_constraint *constraint = &out_constraints[out_idx];
551 const char *c = get_id_str(constraint->constraint);
552 unsigned pos = constraint->pos;
553 constraint_t parsed_constraint;
554 const arch_register_req_t *req;
556 parse_asm_constraints(&parsed_constraint, c, 1);
557 req = make_register_req(&parsed_constraint, n_out_constraints,
558 out_reg_reqs, out_idx);
559 out_reg_reqs[out_idx] = req;
561 register_map[pos].use_input = 0;
562 register_map[pos].valid = 1;
563 register_map[pos].memory = 0;
564 register_map[pos].inout_pos = out_idx;
565 register_map[pos].mode = constraint->mode;
568 /* inputs + input constraints */
569 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
570 for (i = 0; i < arity; ++i) {
571 ir_node *pred = get_irn_n(node, i);
572 const ir_asm_constraint *constraint = &in_constraints[i];
573 ident *constr_id = constraint->constraint;
574 const char *c = get_id_str(constr_id);
575 unsigned pos = constraint->pos;
576 int is_memory_op = 0;
577 ir_node *input = NULL;
578 unsigned r_clobber_bits;
579 constraint_t parsed_constraint;
580 const arch_register_req_t *req;
582 parse_asm_constraints(&parsed_constraint, c, 0);
583 if (parsed_constraint.cls != NULL) {
584 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
585 if (r_clobber_bits != 0) {
586 if (parsed_constraint.all_registers_allowed) {
587 parsed_constraint.all_registers_allowed = 0;
588 be_abi_set_non_ignore_regs(env_cg->birg->abi,
589 parsed_constraint.cls,
590 &parsed_constraint.allowed_registers);
592 parsed_constraint.allowed_registers &= ~r_clobber_bits;
596 req = make_register_req(&parsed_constraint, n_out_constraints,
598 in_reg_reqs[i] = req;
600 if (parsed_constraint.immediate_type != '\0') {
601 char imm_type = parsed_constraint.immediate_type;
602 input = try_create_Immediate(pred, imm_type);
606 ir_node *pred = NULL;
607 switch (be_transformer) {
608 case TRANSFORMER_DEFAULT:
609 pred = get_irn_n(node, i);
610 input = be_transform_node(pred);
614 case TRANSFORMER_PBQP:
615 case TRANSFORMER_RAND:
616 input = get_irn_n(node, i);
620 default: panic("invalid transformer");
623 if (parsed_constraint.cls == NULL
624 && parsed_constraint.same_as < 0) {
626 } else if(parsed_constraint.memory_possible) {
627 /* TODO: match Load or Load/Store if memory possible is set */
632 register_map[pos].use_input = 1;
633 register_map[pos].valid = 1;
634 register_map[pos].memory = is_memory_op;
635 register_map[pos].inout_pos = i;
636 register_map[pos].mode = constraint->mode;
640 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
641 const char *c = get_id_str(clobbers[i]);
642 const arch_register_req_t *req;
644 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
647 req = parse_clobber(c);
648 out_reg_reqs[out_idx] = req;
652 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
653 get_ASM_text(node), register_map);
656 be_dep_on_frame(new_node);
658 set_ia32_out_req_all(new_node, out_reg_reqs);
659 set_ia32_in_req_all(new_node, in_reg_reqs);
661 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
666 ir_node *gen_CopyB(ir_node *node) {
667 ir_node *block = NULL;
669 ir_node *new_src = NULL;
671 ir_node *new_dst = NULL;
673 ir_node *new_mem = NULL;
675 ir_graph *irg = current_ir_graph;
676 dbg_info *dbgi = get_irn_dbg_info(node);
677 int size = get_type_size_bytes(get_CopyB_type(node));
680 switch (be_transformer) {
681 case TRANSFORMER_DEFAULT:
682 block = be_transform_node(get_nodes_block(node));
683 src = get_CopyB_src(node);
684 new_src = be_transform_node(src);
685 dst = get_CopyB_dst(node);
686 new_dst = be_transform_node(dst);
687 mem = get_CopyB_mem(node);
688 new_mem = be_transform_node(mem);
692 case TRANSFORMER_PBQP:
693 case TRANSFORMER_RAND:
694 block = get_nodes_block(node);
695 new_src = get_CopyB_src(node);
696 new_dst = get_CopyB_dst(node);
697 new_mem = get_CopyB_mem(node);
701 default: panic("invalid transformer");
704 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
705 /* then we need the size explicitly in ECX. */
706 if (size >= 32 * 4) {
707 rem = size & 0x3; /* size % 4 */
710 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
711 be_dep_on_frame(res);
713 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
716 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
719 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
722 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
727 ir_node *gen_Proj_tls(ir_node *node) {
728 ir_node *block = NULL;
729 ir_graph *irg = current_ir_graph;
730 dbg_info *dbgi = NULL;
733 switch (be_transformer) {
734 case TRANSFORMER_DEFAULT:
735 block = be_transform_node(get_nodes_block(node));
739 case TRANSFORMER_PBQP:
740 case TRANSFORMER_RAND:
741 block = get_nodes_block(node);
745 default: panic("invalid transformer");
748 res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
753 ir_node *gen_Unknown(ir_node *node)
755 ir_mode *mode = get_irn_mode(node);
757 if (mode_is_float(mode)) {
758 if (ia32_cg_config.use_sse2) {
759 return ia32_new_Unknown_xmm(env_cg);
761 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
762 ir_graph *irg = current_ir_graph;
763 dbg_info *dbgi = get_irn_dbg_info(node);
764 ir_node *block = get_irg_start_block(irg);
765 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
767 be_dep_on_frame(ret);
770 } else if (ia32_mode_needs_gp_reg(mode)) {
771 return ia32_new_Unknown_gp(env_cg);
773 panic("unsupported Unknown-Mode");
778 const arch_register_req_t *make_register_req(const constraint_t *constraint,
779 int n_outs, const arch_register_req_t **out_reqs, int pos)
781 struct obstack *obst = get_irg_obstack(current_ir_graph);
782 int same_as = constraint->same_as;
783 arch_register_req_t *req;
786 const arch_register_req_t *other_constr;
788 if (same_as >= n_outs)
789 panic("invalid output number in same_as constraint");
791 other_constr = out_reqs[same_as];
793 req = obstack_alloc(obst, sizeof(req[0]));
794 *req = *other_constr;
795 req->type |= arch_register_req_type_should_be_same;
796 req->other_same = 1U << pos;
798 /* switch constraints. This is because in firm we have same_as
799 * constraints on the output constraints while in the gcc asm syntax
800 * they are specified on the input constraints */
801 out_reqs[same_as] = req;
805 /* pure memory ops */
806 if (constraint->cls == NULL) {
807 return &no_register_req;
810 if (constraint->allowed_registers != 0
811 && !constraint->all_registers_allowed) {
812 unsigned *limited_ptr;
814 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
815 memset(req, 0, sizeof(req[0]));
816 limited_ptr = (unsigned*) (req+1);
818 req->type = arch_register_req_type_limited;
819 *limited_ptr = constraint->allowed_registers;
820 req->limited = limited_ptr;
822 req = obstack_alloc(obst, sizeof(req[0]));
823 memset(req, 0, sizeof(req[0]));
824 req->type = arch_register_req_type_normal;
826 req->cls = constraint->cls;
831 const arch_register_req_t *parse_clobber(const char *clobber)
833 struct obstack *obst = get_irg_obstack(current_ir_graph);
834 const arch_register_t *reg = ia32_get_clobber_register(clobber);
835 arch_register_req_t *req;
839 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
842 assert(reg->index < 32);
844 limited = obstack_alloc(obst, sizeof(limited[0]));
845 *limited = 1 << reg->index;
847 req = obstack_alloc(obst, sizeof(req[0]));
848 memset(req, 0, sizeof(req[0]));
849 req->type = arch_register_req_type_limited;
850 req->cls = arch_register_get_class(reg);
851 req->limited = limited;
857 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
858 ir_node *const other)
860 if (get_nodes_block(other) != block)
863 if (is_Sync(other)) {
866 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
867 ir_node *const pred = get_Sync_pred(other, i);
869 if (get_nodes_block(pred) != block)
872 /* Do not block ourselves from getting eaten */
873 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
876 if (!heights_reachable_in_block(heights, pred, am_candidate))
884 /* Do not block ourselves from getting eaten */
885 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
888 if (!heights_reachable_in_block(heights, other, am_candidate))
895 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
898 tarval *offset = NULL;
901 ir_entity *symconst_ent = NULL;
902 int symconst_sign = 0;
904 ir_node *cnst = NULL;
905 ir_node *symconst = NULL;
908 mode = get_irn_mode(node);
909 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
915 node = get_Minus_op(node);
922 } else if(is_SymConst(node)) {
925 symconst_sign = minus;
926 } else if(is_Add(node)) {
927 ir_node *left = get_Add_left(node);
928 ir_node *right = get_Add_right(node);
929 if(is_Const(left) && is_SymConst(right)) {
932 symconst_sign = minus;
934 } else if(is_SymConst(left) && is_Const(right)) {
937 symconst_sign = minus;
940 } else if(is_Sub(node)) {
941 ir_node *left = get_Sub_left(node);
942 ir_node *right = get_Sub_right(node);
943 if(is_Const(left) && is_SymConst(right)) {
946 symconst_sign = !minus;
948 } else if(is_SymConst(left) && is_Const(right)) {
951 symconst_sign = minus;
952 offset_sign = !minus;
959 offset = get_Const_tarval(cnst);
960 if(tarval_is_long(offset)) {
961 val = get_tarval_long(offset);
963 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
968 if(!check_immediate_constraint(val, immediate_constraint_type))
971 if(symconst != NULL) {
972 if(immediate_constraint_type != 0) {
973 /* we need full 32bits for symconsts */
977 /* unfortunately the assembler/linker doesn't support -symconst */
981 if(get_SymConst_kind(symconst) != symconst_addr_ent)
983 symconst_ent = get_SymConst_entity(symconst);
985 if(cnst == NULL && symconst == NULL)
988 if(offset_sign && offset != NULL) {
989 offset = tarval_neg(offset);
992 new_node = create_Immediate(symconst_ent, symconst_sign, val);