2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
35 #include "../beirg_t.h"
37 #include "ia32_architecture.h"
38 #include "ia32_common_transform.h"
39 #include "ia32_new_nodes.h"
41 #include "gen_ia32_new_nodes.h"
42 #include "gen_ia32_regalloc_if.h"
44 /** hold the current code generator during transformation */
45 ia32_code_gen_t *env_cg = NULL;
47 heights_t *heights = NULL;
49 static const arch_register_req_t no_register_req = {
50 arch_register_req_type_none,
52 NULL, /* limit bitset */
57 static int check_immediate_constraint(long val, char immediate_constraint_type)
59 switch (immediate_constraint_type) {
63 case 'I': return 0 <= val && val <= 31;
64 case 'J': return 0 <= val && val <= 63;
65 case 'K': return -128 <= val && val <= 127;
66 case 'L': return val == 0xff || val == 0xffff;
67 case 'M': return 0 <= val && val <= 3;
68 case 'N': return 0 <= val && val <= 255;
69 case 'O': return 0 <= val && val <= 127;
71 default: panic("Invalid immediate constraint found");
76 * creates a unique ident by adding a number to a tag
78 * @param tag the tag string, must contain a %d if a number
81 static ident *unique_id(const char *tag)
83 static unsigned id = 0;
86 snprintf(str, sizeof(str), tag, ++id);
87 return new_id_from_str(str);
91 * Get a primitive type for a mode.
93 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
95 pmap_entry *e = pmap_find(types, mode);
100 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
101 res = new_type_primitive(new_id_from_str(buf), mode);
102 set_type_alignment_bytes(res, 16);
103 pmap_insert(types, mode, res);
110 ir_entity *create_float_const_entity(ir_node *cnst)
112 ia32_isa_t *isa = env_cg->isa;
113 tarval *key = get_Const_tarval(cnst);
114 pmap_entry *e = pmap_find(isa->tv_ent, key);
120 ir_mode *mode = get_tarval_mode(tv);
123 if (! ia32_cg_config.use_sse2) {
124 /* try to reduce the mode to produce smaller sized entities */
125 if (mode != mode_F) {
126 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
128 tv = tarval_convert_to(tv, mode);
129 } else if (mode != mode_D) {
130 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
132 tv = tarval_convert_to(tv, mode);
138 if (mode == get_irn_mode(cnst)) {
139 /* mode was not changed */
140 tp = get_Const_type(cnst);
141 if (tp == firm_unknown_type)
142 tp = ia32_get_prim_type(isa->types, mode);
144 tp = ia32_get_prim_type(isa->types, mode);
146 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
148 set_entity_ld_ident(res, get_entity_ident(res));
149 set_entity_visibility(res, visibility_local);
150 set_entity_variability(res, variability_constant);
151 set_entity_allocation(res, allocation_static);
153 /* we create a new entity here: It's initialization must resist on the
155 rem = current_ir_graph;
156 current_ir_graph = get_const_code_irg();
157 set_atomic_ent_value(res, new_Const_type(tv, tp));
158 current_ir_graph = rem;
160 pmap_insert(isa->tv_ent, key, res);
168 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
170 ir_graph *irg = current_ir_graph;
171 ir_node *start_block = get_irg_start_block(irg);
172 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
173 symconst, symconst_sign, val);
174 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
179 const arch_register_t *ia32_get_clobber_register(const char *clobber)
181 const arch_register_t *reg = NULL;
184 const arch_register_class_t *cls;
186 /* TODO: construct a hashmap instead of doing linear search for clobber
188 for(c = 0; c < N_CLASSES; ++c) {
189 cls = & ia32_reg_classes[c];
190 for(r = 0; r < cls->n_regs; ++r) {
191 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
192 if(strcmp(temp_reg->name, clobber) == 0
193 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
205 int ia32_mode_needs_gp_reg(ir_mode *mode) {
206 if(mode == mode_fpcw)
208 if(get_mode_size_bits(mode) > 32)
210 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
213 static void parse_asm_constraints(constraint_t *constraint, const char *c,
216 char immediate_type = '\0';
217 unsigned limited = 0;
218 const arch_register_class_t *cls = NULL;
219 int memory_possible = 0;
220 int all_registers_allowed = 0;
224 memset(constraint, 0, sizeof(constraint[0]));
225 constraint->same_as = -1;
228 /* a memory constraint: no need to do anything in backend about it
229 * (the dependencies are already respected by the memory edge of
234 /* TODO: improve error messages with node and source info. (As users can
235 * easily hit these) */
243 /* Skip out/in-out marker */
251 while(*c != 0 && *c != ',')
256 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
257 cls = &ia32_reg_classes[CLASS_ia32_gp];
258 limited |= 1 << REG_EAX;
261 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
262 cls = &ia32_reg_classes[CLASS_ia32_gp];
263 limited |= 1 << REG_EBX;
266 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
267 cls = &ia32_reg_classes[CLASS_ia32_gp];
268 limited |= 1 << REG_ECX;
271 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
272 cls = &ia32_reg_classes[CLASS_ia32_gp];
273 limited |= 1 << REG_EDX;
276 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
277 cls = &ia32_reg_classes[CLASS_ia32_gp];
278 limited |= 1 << REG_EDI;
281 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
282 cls = &ia32_reg_classes[CLASS_ia32_gp];
283 limited |= 1 << REG_ESI;
287 /* q means lower part of the regs only, this makes no
288 * difference to Q for us (we only assign whole registers) */
289 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
290 cls = &ia32_reg_classes[CLASS_ia32_gp];
291 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
295 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
296 cls = &ia32_reg_classes[CLASS_ia32_gp];
297 limited |= 1 << REG_EAX | 1 << REG_EDX;
300 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
301 cls = &ia32_reg_classes[CLASS_ia32_gp];
302 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
303 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
310 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
311 panic("multiple register classes not supported");
312 cls = &ia32_reg_classes[CLASS_ia32_gp];
313 all_registers_allowed = 1;
319 /* TODO: mark values so the x87 simulator knows about t and u */
320 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
321 panic("multiple register classes not supported");
322 cls = &ia32_reg_classes[CLASS_ia32_vfp];
323 all_registers_allowed = 1;
328 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
329 panic("multiple register classes not supproted");
330 cls = &ia32_reg_classes[CLASS_ia32_xmm];
331 all_registers_allowed = 1;
341 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
342 panic("multiple register classes not supported");
343 if (immediate_type != '\0')
344 panic("multiple immediate types not supported");
345 cls = &ia32_reg_classes[CLASS_ia32_gp];
350 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
351 panic("multiple register classes not supported");
352 if (immediate_type != '\0')
353 panic("multiple immediate types not supported");
354 cls = &ia32_reg_classes[CLASS_ia32_gp];
355 immediate_type = 'i';
360 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
361 panic("multiple register classes not supported");
362 if (immediate_type != '\0')
363 panic("multiple immediate types not supported");
364 immediate_type = 'i';
365 cls = &ia32_reg_classes[CLASS_ia32_gp];
366 all_registers_allowed = 1;
381 panic("can only specify same constraint on input");
383 sscanf(c, "%d%n", &same_as, &p);
393 /* memory constraint no need to do anything in backend about it
394 * (the dependencies are already respected by the memory edge of
399 case 'E': /* no float consts yet */
400 case 'F': /* no float consts yet */
401 case 's': /* makes no sense on x86 */
402 case '<': /* no autodecrement on x86 */
403 case '>': /* no autoincrement on x86 */
404 case 'C': /* sse constant not supported yet */
405 case 'G': /* 80387 constant not supported yet */
406 case 'y': /* we don't support mmx registers yet */
407 case 'Z': /* not available in 32 bit mode */
408 case 'e': /* not available in 32 bit mode */
409 panic("unsupported asm constraint '%c' found in (%+F)",
410 *c, current_ir_graph);
413 panic("unknown asm constraint '%c' found in (%+F)", *c,
422 panic("same as and register constraint not supported");
423 if (immediate_type != '\0')
424 panic("same as and immediate constraint not supported");
427 if (cls == NULL && same_as < 0) {
428 if (!memory_possible)
429 panic("no constraint specified for assembler input");
432 constraint->same_as = same_as;
433 constraint->cls = cls;
434 constraint->allowed_registers = limited;
435 constraint->all_registers_allowed = all_registers_allowed;
436 constraint->memory_possible = memory_possible;
437 constraint->immediate_type = immediate_type;
440 ir_node *gen_ASM(ir_node *node)
442 ir_graph *irg = current_ir_graph;
443 ir_node *block = NULL;
444 ir_node *new_block = NULL;
445 dbg_info *dbgi = get_irn_dbg_info(node);
451 int n_out_constraints;
453 const arch_register_req_t **out_reg_reqs;
454 const arch_register_req_t **in_reg_reqs;
455 ia32_asm_reg_t *register_map;
456 unsigned reg_map_size = 0;
457 struct obstack *obst;
458 const ir_asm_constraint *in_constraints;
459 const ir_asm_constraint *out_constraints;
461 int clobbers_flags = 0;
462 unsigned clobber_bits[N_CLASSES];
464 memset(&clobber_bits, 0, sizeof(clobber_bits));
466 switch (be_transformer) {
467 case TRANSFORMER_DEFAULT:
468 block = get_nodes_block(node);
469 new_block = be_transform_node(block);
473 case TRANSFORMER_PBQP:
474 case TRANSFORMER_RAND:
475 new_block = get_nodes_block(node);
480 panic("invalid transformer");
483 /* workaround for lots of buggy code out there as most people think volatile
484 * asm is enough for everything and forget the flags (linux kernel, etc.)
486 if (get_irn_pinned(node) == op_pin_state_pinned) {
490 arity = get_irn_arity(node);
491 in = ALLOCANZ(ir_node*, arity);
493 clobbers = get_ASM_clobbers(node);
495 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
496 const arch_register_req_t *req;
497 const char *c = get_id_str(clobbers[i]);
499 if (strcmp(c, "memory") == 0)
501 if (strcmp(c, "cc") == 0) {
506 req = parse_clobber(c);
507 clobber_bits[req->cls->index] |= *req->limited;
511 n_out_constraints = get_ASM_n_output_constraints(node);
512 out_arity = n_out_constraints + n_clobbers;
514 in_constraints = get_ASM_input_constraints(node);
515 out_constraints = get_ASM_output_constraints(node);
517 /* determine size of register_map */
518 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
519 const ir_asm_constraint *constraint = &out_constraints[out_idx];
520 if (constraint->pos > reg_map_size)
521 reg_map_size = constraint->pos;
523 for (i = 0; i < arity; ++i) {
524 const ir_asm_constraint *constraint = &in_constraints[i];
525 if(constraint->pos > reg_map_size)
526 reg_map_size = constraint->pos;
530 obst = get_irg_obstack(irg);
531 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
532 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
534 /* construct output constraints */
535 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
537 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
538 const ir_asm_constraint *constraint = &out_constraints[out_idx];
539 const char *c = get_id_str(constraint->constraint);
540 unsigned pos = constraint->pos;
541 constraint_t parsed_constraint;
542 const arch_register_req_t *req;
544 parse_asm_constraints(&parsed_constraint, c, 1);
545 req = make_register_req(&parsed_constraint, n_out_constraints,
546 out_reg_reqs, out_idx);
547 out_reg_reqs[out_idx] = req;
549 register_map[pos].use_input = 0;
550 register_map[pos].valid = 1;
551 register_map[pos].memory = 0;
552 register_map[pos].inout_pos = out_idx;
553 register_map[pos].mode = constraint->mode;
556 /* inputs + input constraints */
557 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
558 for (i = 0; i < arity; ++i) {
559 ir_node *pred = get_irn_n(node, i);
560 const ir_asm_constraint *constraint = &in_constraints[i];
561 ident *constr_id = constraint->constraint;
562 const char *c = get_id_str(constr_id);
563 unsigned pos = constraint->pos;
564 int is_memory_op = 0;
565 ir_node *input = NULL;
566 unsigned r_clobber_bits;
567 constraint_t parsed_constraint;
568 const arch_register_req_t *req;
570 parse_asm_constraints(&parsed_constraint, c, 0);
571 if (parsed_constraint.cls != NULL) {
572 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
573 if (r_clobber_bits != 0) {
574 if (parsed_constraint.all_registers_allowed) {
575 parsed_constraint.all_registers_allowed = 0;
576 be_abi_set_non_ignore_regs(env_cg->birg->abi,
577 parsed_constraint.cls,
578 &parsed_constraint.allowed_registers);
580 parsed_constraint.allowed_registers &= ~r_clobber_bits;
584 req = make_register_req(&parsed_constraint, n_out_constraints,
586 in_reg_reqs[i] = req;
588 if (parsed_constraint.immediate_type != '\0') {
589 char imm_type = parsed_constraint.immediate_type;
590 input = try_create_Immediate(pred, imm_type);
594 ir_node *pred = NULL;
595 switch (be_transformer) {
596 case TRANSFORMER_DEFAULT:
597 pred = get_irn_n(node, i);
598 input = be_transform_node(pred);
602 case TRANSFORMER_PBQP:
603 case TRANSFORMER_RAND:
604 input = get_irn_n(node, i);
608 default: panic("invalid transformer");
611 if (parsed_constraint.cls == NULL
612 && parsed_constraint.same_as < 0) {
614 } else if(parsed_constraint.memory_possible) {
615 /* TODO: match Load or Load/Store if memory possible is set */
620 register_map[pos].use_input = 1;
621 register_map[pos].valid = 1;
622 register_map[pos].memory = is_memory_op;
623 register_map[pos].inout_pos = i;
624 register_map[pos].mode = constraint->mode;
628 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
629 const char *c = get_id_str(clobbers[i]);
630 const arch_register_req_t *req;
632 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
635 req = parse_clobber(c);
636 out_reg_reqs[out_idx] = req;
640 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
641 get_ASM_text(node), register_map);
644 be_dep_on_frame(new_node);
646 set_ia32_out_req_all(new_node, out_reg_reqs);
647 set_ia32_in_req_all(new_node, in_reg_reqs);
649 SET_IA32_ORIG_NODE(new_node, node);
654 ir_node *gen_CopyB(ir_node *node) {
655 ir_node *block = NULL;
657 ir_node *new_src = NULL;
659 ir_node *new_dst = NULL;
661 ir_node *new_mem = NULL;
663 ir_graph *irg = current_ir_graph;
664 dbg_info *dbgi = get_irn_dbg_info(node);
665 int size = get_type_size_bytes(get_CopyB_type(node));
668 switch (be_transformer) {
669 case TRANSFORMER_DEFAULT:
670 block = be_transform_node(get_nodes_block(node));
671 src = get_CopyB_src(node);
672 new_src = be_transform_node(src);
673 dst = get_CopyB_dst(node);
674 new_dst = be_transform_node(dst);
675 mem = get_CopyB_mem(node);
676 new_mem = be_transform_node(mem);
680 case TRANSFORMER_PBQP:
681 case TRANSFORMER_RAND:
682 block = get_nodes_block(node);
683 new_src = get_CopyB_src(node);
684 new_dst = get_CopyB_dst(node);
685 new_mem = get_CopyB_mem(node);
689 default: panic("invalid transformer");
692 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
693 /* then we need the size explicitly in ECX. */
694 if (size >= 32 * 4) {
695 rem = size & 0x3; /* size % 4 */
698 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
699 be_dep_on_frame(res);
701 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
704 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
707 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
710 SET_IA32_ORIG_NODE(res, node);
715 ir_node *gen_Proj_tls(ir_node *node) {
716 ir_node *block = NULL;
717 ir_graph *irg = current_ir_graph;
718 dbg_info *dbgi = NULL;
721 switch (be_transformer) {
722 case TRANSFORMER_DEFAULT:
723 block = be_transform_node(get_nodes_block(node));
727 case TRANSFORMER_PBQP:
728 case TRANSFORMER_RAND:
729 block = get_nodes_block(node);
733 default: panic("invalid transformer");
736 res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
741 ir_node *gen_Unknown(ir_node *node)
743 ir_mode *mode = get_irn_mode(node);
745 if (mode_is_float(mode)) {
746 if (ia32_cg_config.use_sse2) {
747 return ia32_new_Unknown_xmm(env_cg);
749 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
750 ir_graph *irg = current_ir_graph;
751 dbg_info *dbgi = get_irn_dbg_info(node);
752 ir_node *block = get_irg_start_block(irg);
753 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
755 be_dep_on_frame(ret);
758 } else if (ia32_mode_needs_gp_reg(mode)) {
759 return ia32_new_Unknown_gp(env_cg);
761 panic("unsupported Unknown-Mode");
766 const arch_register_req_t *make_register_req(const constraint_t *constraint,
767 int n_outs, const arch_register_req_t **out_reqs, int pos)
769 struct obstack *obst = get_irg_obstack(current_ir_graph);
770 int same_as = constraint->same_as;
771 arch_register_req_t *req;
774 const arch_register_req_t *other_constr;
776 if (same_as >= n_outs)
777 panic("invalid output number in same_as constraint");
779 other_constr = out_reqs[same_as];
781 req = obstack_alloc(obst, sizeof(req[0]));
782 *req = *other_constr;
783 req->type |= arch_register_req_type_should_be_same;
784 req->other_same = 1U << pos;
786 /* switch constraints. This is because in firm we have same_as
787 * constraints on the output constraints while in the gcc asm syntax
788 * they are specified on the input constraints */
789 out_reqs[same_as] = req;
793 /* pure memory ops */
794 if (constraint->cls == NULL) {
795 return &no_register_req;
798 if (constraint->allowed_registers != 0
799 && !constraint->all_registers_allowed) {
800 unsigned *limited_ptr;
802 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
803 memset(req, 0, sizeof(req[0]));
804 limited_ptr = (unsigned*) (req+1);
806 req->type = arch_register_req_type_limited;
807 *limited_ptr = constraint->allowed_registers;
808 req->limited = limited_ptr;
810 req = obstack_alloc(obst, sizeof(req[0]));
811 memset(req, 0, sizeof(req[0]));
812 req->type = arch_register_req_type_normal;
814 req->cls = constraint->cls;
819 const arch_register_req_t *parse_clobber(const char *clobber)
821 struct obstack *obst = get_irg_obstack(current_ir_graph);
822 const arch_register_t *reg = ia32_get_clobber_register(clobber);
823 arch_register_req_t *req;
827 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
830 assert(reg->index < 32);
832 limited = obstack_alloc(obst, sizeof(limited[0]));
833 *limited = 1 << reg->index;
835 req = obstack_alloc(obst, sizeof(req[0]));
836 memset(req, 0, sizeof(req[0]));
837 req->type = arch_register_req_type_limited;
838 req->cls = arch_register_get_class(reg);
839 req->limited = limited;
845 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
846 ir_node *const other)
848 if (get_nodes_block(other) != block)
851 if (is_Sync(other)) {
854 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
855 ir_node *const pred = get_Sync_pred(other, i);
857 if (get_nodes_block(pred) != block)
860 /* Do not block ourselves from getting eaten */
861 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
864 if (!heights_reachable_in_block(heights, pred, am_candidate))
872 /* Do not block ourselves from getting eaten */
873 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
876 if (!heights_reachable_in_block(heights, other, am_candidate))
883 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
886 tarval *offset = NULL;
889 ir_entity *symconst_ent = NULL;
890 int symconst_sign = 0;
892 ir_node *cnst = NULL;
893 ir_node *symconst = NULL;
896 mode = get_irn_mode(node);
897 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
903 node = get_Minus_op(node);
910 } else if(is_SymConst(node)) {
913 symconst_sign = minus;
914 } else if(is_Add(node)) {
915 ir_node *left = get_Add_left(node);
916 ir_node *right = get_Add_right(node);
917 if(is_Const(left) && is_SymConst(right)) {
920 symconst_sign = minus;
922 } else if(is_SymConst(left) && is_Const(right)) {
925 symconst_sign = minus;
928 } else if(is_Sub(node)) {
929 ir_node *left = get_Sub_left(node);
930 ir_node *right = get_Sub_right(node);
931 if(is_Const(left) && is_SymConst(right)) {
934 symconst_sign = !minus;
936 } else if(is_SymConst(left) && is_Const(right)) {
939 symconst_sign = minus;
940 offset_sign = !minus;
947 offset = get_Const_tarval(cnst);
948 if(tarval_is_long(offset)) {
949 val = get_tarval_long(offset);
951 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
956 if(!check_immediate_constraint(val, immediate_constraint_type))
959 if(symconst != NULL) {
960 if(immediate_constraint_type != 0) {
961 /* we need full 32bits for symconsts */
965 /* unfortunately the assembler/linker doesn't support -symconst */
969 if(get_SymConst_kind(symconst) != symconst_addr_ent)
971 symconst_ent = get_SymConst_entity(symconst);
973 if(cnst == NULL && symconst == NULL)
976 if(offset_sign && offset != NULL) {
977 offset = tarval_neg(offset);
980 new_node = create_Immediate(symconst_ent, symconst_sign, val);