2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
35 #include "../beirg_t.h"
37 #include "ia32_architecture.h"
38 #include "ia32_common_transform.h"
39 #include "ia32_new_nodes.h"
41 #include "gen_ia32_new_nodes.h"
42 #include "gen_ia32_regalloc_if.h"
44 /** hold the current code generator during transformation */
45 ia32_code_gen_t *env_cg = NULL;
47 heights_t *heights = NULL;
49 static const arch_register_req_t no_register_req = {
50 arch_register_req_type_none,
52 NULL, /* limit bitset */
57 static int check_immediate_constraint(long val, char immediate_constraint_type)
59 switch (immediate_constraint_type) {
63 case 'I': return 0 <= val && val <= 31;
64 case 'J': return 0 <= val && val <= 63;
65 case 'K': return -128 <= val && val <= 127;
66 case 'L': return val == 0xff || val == 0xffff;
67 case 'M': return 0 <= val && val <= 3;
68 case 'N': return 0 <= val && val <= 255;
69 case 'O': return 0 <= val && val <= 127;
71 default: panic("Invalid immediate constraint found");
75 /* creates a unique ident by adding a number to a tag */
76 ident *ia32_unique_id(const char *tag)
78 static unsigned id = 0;
81 snprintf(str, sizeof(str), tag, ++id);
82 return new_id_from_str(str);
86 * Get a primitive type for a mode with alignment 16.
88 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
90 pmap_entry *e = pmap_find(types, mode);
95 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
96 res = new_type_primitive(new_id_from_str(buf), mode);
97 if (get_mode_size_bits(mode) >= 80) {
98 set_type_alignment_bytes(res, 16);
100 pmap_insert(types, mode, res);
107 ir_entity *create_float_const_entity(ir_node *cnst)
109 ia32_isa_t *isa = env_cg->isa;
110 tarval *key = get_Const_tarval(cnst);
111 pmap_entry *e = pmap_find(isa->tv_ent, key);
117 ir_mode *mode = get_tarval_mode(tv);
120 if (! ia32_cg_config.use_sse2) {
121 /* try to reduce the mode to produce smaller sized entities */
122 if (mode != mode_F) {
123 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
125 tv = tarval_convert_to(tv, mode);
126 } else if (mode != mode_D) {
127 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
129 tv = tarval_convert_to(tv, mode);
135 if (mode == get_irn_mode(cnst)) {
136 /* mode was not changed */
137 tp = get_Const_type(cnst);
138 if (tp == firm_unknown_type)
139 tp = ia32_get_prim_type(isa->types, mode);
141 tp = ia32_get_prim_type(isa->types, mode);
143 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
145 set_entity_ld_ident(res, get_entity_ident(res));
146 set_entity_visibility(res, visibility_local);
147 set_entity_variability(res, variability_constant);
148 set_entity_allocation(res, allocation_static);
150 /* we create a new entity here: It's initialization must resist on the
152 rem = current_ir_graph;
153 current_ir_graph = get_const_code_irg();
154 set_atomic_ent_value(res, new_Const_type(tv, tp));
155 current_ir_graph = rem;
157 pmap_insert(isa->tv_ent, key, res);
165 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
167 ir_graph *irg = current_ir_graph;
168 ir_node *start_block = get_irg_start_block(irg);
169 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
171 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
176 const arch_register_t *ia32_get_clobber_register(const char *clobber)
178 const arch_register_t *reg = NULL;
181 const arch_register_class_t *cls;
183 /* TODO: construct a hashmap instead of doing linear search for clobber
185 for(c = 0; c < N_CLASSES; ++c) {
186 cls = & ia32_reg_classes[c];
187 for(r = 0; r < cls->n_regs; ++r) {
188 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
189 if (strcmp(temp_reg->name, clobber) == 0
190 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
202 int ia32_mode_needs_gp_reg(ir_mode *mode) {
203 if (mode == mode_fpcw)
205 if (get_mode_size_bits(mode) > 32)
207 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
210 static void parse_asm_constraints(constraint_t *constraint, const char *c,
213 char immediate_type = '\0';
214 unsigned limited = 0;
215 const arch_register_class_t *cls = NULL;
216 int memory_possible = 0;
217 int all_registers_allowed = 0;
221 memset(constraint, 0, sizeof(constraint[0]));
222 constraint->same_as = -1;
225 /* a memory constraint: no need to do anything in backend about it
226 * (the dependencies are already respected by the memory edge of
231 /* TODO: improve error messages with node and source info. (As users can
232 * easily hit these) */
240 /* Skip out/in-out marker */
250 while(*c != 0 && *c != ',')
255 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
256 cls = &ia32_reg_classes[CLASS_ia32_gp];
257 limited |= 1 << REG_EAX;
260 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
261 cls = &ia32_reg_classes[CLASS_ia32_gp];
262 limited |= 1 << REG_EBX;
265 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
266 cls = &ia32_reg_classes[CLASS_ia32_gp];
267 limited |= 1 << REG_ECX;
270 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
271 cls = &ia32_reg_classes[CLASS_ia32_gp];
272 limited |= 1 << REG_EDX;
275 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
276 cls = &ia32_reg_classes[CLASS_ia32_gp];
277 limited |= 1 << REG_EDI;
280 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
281 cls = &ia32_reg_classes[CLASS_ia32_gp];
282 limited |= 1 << REG_ESI;
286 /* q means lower part of the regs only, this makes no
287 * difference to Q for us (we only assign whole registers) */
288 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
289 cls = &ia32_reg_classes[CLASS_ia32_gp];
290 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
294 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
295 cls = &ia32_reg_classes[CLASS_ia32_gp];
296 limited |= 1 << REG_EAX | 1 << REG_EDX;
299 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
300 cls = &ia32_reg_classes[CLASS_ia32_gp];
301 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
302 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
309 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
310 panic("multiple register classes not supported");
311 cls = &ia32_reg_classes[CLASS_ia32_gp];
312 all_registers_allowed = 1;
318 /* TODO: mark values so the x87 simulator knows about t and u */
319 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
320 panic("multiple register classes not supported");
321 cls = &ia32_reg_classes[CLASS_ia32_vfp];
322 all_registers_allowed = 1;
327 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
328 panic("multiple register classes not supproted");
329 cls = &ia32_reg_classes[CLASS_ia32_xmm];
330 all_registers_allowed = 1;
340 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
341 panic("multiple register classes not supported");
342 if (immediate_type != '\0')
343 panic("multiple immediate types not supported");
344 cls = &ia32_reg_classes[CLASS_ia32_gp];
349 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
350 panic("multiple register classes not supported");
351 if (immediate_type != '\0')
352 panic("multiple immediate types not supported");
353 cls = &ia32_reg_classes[CLASS_ia32_gp];
354 immediate_type = 'i';
359 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
360 panic("multiple register classes not supported");
361 if (immediate_type != '\0')
362 panic("multiple immediate types not supported");
363 immediate_type = 'i';
364 cls = &ia32_reg_classes[CLASS_ia32_gp];
365 all_registers_allowed = 1;
380 panic("can only specify same constraint on input");
382 sscanf(c, "%d%n", &same_as, &p);
392 /* memory constraint no need to do anything in backend about it
393 * (the dependencies are already respected by the memory edge of
398 case 'E': /* no float consts yet */
399 case 'F': /* no float consts yet */
400 case 's': /* makes no sense on x86 */
401 case '<': /* no autodecrement on x86 */
402 case '>': /* no autoincrement on x86 */
403 case 'C': /* sse constant not supported yet */
404 case 'G': /* 80387 constant not supported yet */
405 case 'y': /* we don't support mmx registers yet */
406 case 'Z': /* not available in 32 bit mode */
407 case 'e': /* not available in 32 bit mode */
408 panic("unsupported asm constraint '%c' found in (%+F)",
409 *c, current_ir_graph);
412 panic("unknown asm constraint '%c' found in (%+F)", *c,
421 panic("same as and register constraint not supported");
422 if (immediate_type != '\0')
423 panic("same as and immediate constraint not supported");
426 if (cls == NULL && same_as < 0) {
427 if (!memory_possible)
428 panic("no constraint specified for assembler input");
431 constraint->same_as = same_as;
432 constraint->cls = cls;
433 constraint->allowed_registers = limited;
434 constraint->all_registers_allowed = all_registers_allowed;
435 constraint->memory_possible = memory_possible;
436 constraint->immediate_type = immediate_type;
439 ir_node *gen_ASM(ir_node *node)
441 ir_node *block = NULL;
442 ir_node *new_block = NULL;
443 dbg_info *dbgi = get_irn_dbg_info(node);
449 int n_out_constraints;
451 const arch_register_req_t **out_reg_reqs;
452 const arch_register_req_t **in_reg_reqs;
453 ia32_asm_reg_t *register_map;
454 unsigned reg_map_size = 0;
455 struct obstack *obst;
456 const ir_asm_constraint *in_constraints;
457 const ir_asm_constraint *out_constraints;
459 int clobbers_flags = 0;
460 unsigned clobber_bits[N_CLASSES];
462 memset(&clobber_bits, 0, sizeof(clobber_bits));
464 switch (be_transformer) {
465 case TRANSFORMER_DEFAULT:
466 block = get_nodes_block(node);
467 new_block = be_transform_node(block);
471 case TRANSFORMER_PBQP:
472 case TRANSFORMER_RAND:
473 new_block = get_nodes_block(node);
478 panic("invalid transformer");
481 /* workaround for lots of buggy code out there as most people think volatile
482 * asm is enough for everything and forget the flags (linux kernel, etc.)
484 if (get_irn_pinned(node) == op_pin_state_pinned) {
488 arity = get_irn_arity(node);
489 in = ALLOCANZ(ir_node*, arity);
491 clobbers = get_ASM_clobbers(node);
493 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
494 const arch_register_req_t *req;
495 const char *c = get_id_str(clobbers[i]);
497 if (strcmp(c, "memory") == 0)
499 if (strcmp(c, "cc") == 0) {
504 req = parse_clobber(c);
505 clobber_bits[req->cls->index] |= *req->limited;
509 n_out_constraints = get_ASM_n_output_constraints(node);
510 out_arity = n_out_constraints + n_clobbers;
512 in_constraints = get_ASM_input_constraints(node);
513 out_constraints = get_ASM_output_constraints(node);
515 /* determine size of register_map */
516 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
517 const ir_asm_constraint *constraint = &out_constraints[out_idx];
518 if (constraint->pos > reg_map_size)
519 reg_map_size = constraint->pos;
521 for (i = 0; i < arity; ++i) {
522 const ir_asm_constraint *constraint = &in_constraints[i];
523 if (constraint->pos > reg_map_size)
524 reg_map_size = constraint->pos;
528 obst = get_irg_obstack(current_ir_graph);
529 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
530 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
532 /* construct output constraints */
533 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
535 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
536 const ir_asm_constraint *constraint = &out_constraints[out_idx];
537 const char *c = get_id_str(constraint->constraint);
538 unsigned pos = constraint->pos;
539 constraint_t parsed_constraint;
540 const arch_register_req_t *req;
542 parse_asm_constraints(&parsed_constraint, c, 1);
543 req = make_register_req(&parsed_constraint, n_out_constraints,
544 out_reg_reqs, out_idx);
545 out_reg_reqs[out_idx] = req;
547 register_map[pos].use_input = 0;
548 register_map[pos].valid = 1;
549 register_map[pos].memory = 0;
550 register_map[pos].inout_pos = out_idx;
551 register_map[pos].mode = constraint->mode;
554 /* inputs + input constraints */
555 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
556 for (i = 0; i < arity; ++i) {
557 ir_node *pred = get_irn_n(node, i);
558 const ir_asm_constraint *constraint = &in_constraints[i];
559 ident *constr_id = constraint->constraint;
560 const char *c = get_id_str(constr_id);
561 unsigned pos = constraint->pos;
562 int is_memory_op = 0;
563 ir_node *input = NULL;
564 unsigned r_clobber_bits;
565 constraint_t parsed_constraint;
566 const arch_register_req_t *req;
568 parse_asm_constraints(&parsed_constraint, c, 0);
569 if (parsed_constraint.cls != NULL) {
570 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
571 if (r_clobber_bits != 0) {
572 if (parsed_constraint.all_registers_allowed) {
573 parsed_constraint.all_registers_allowed = 0;
574 be_abi_set_non_ignore_regs(env_cg->birg->abi,
575 parsed_constraint.cls,
576 &parsed_constraint.allowed_registers);
578 parsed_constraint.allowed_registers &= ~r_clobber_bits;
582 req = make_register_req(&parsed_constraint, n_out_constraints,
584 in_reg_reqs[i] = req;
586 if (parsed_constraint.immediate_type != '\0') {
587 char imm_type = parsed_constraint.immediate_type;
588 input = try_create_Immediate(pred, imm_type);
592 ir_node *pred = NULL;
593 switch (be_transformer) {
594 case TRANSFORMER_DEFAULT:
595 pred = get_irn_n(node, i);
596 input = be_transform_node(pred);
600 case TRANSFORMER_PBQP:
601 case TRANSFORMER_RAND:
602 input = get_irn_n(node, i);
606 default: panic("invalid transformer");
609 if (parsed_constraint.cls == NULL
610 && parsed_constraint.same_as < 0) {
612 } else if (parsed_constraint.memory_possible) {
613 /* TODO: match Load or Load/Store if memory possible is set */
618 register_map[pos].use_input = 1;
619 register_map[pos].valid = 1;
620 register_map[pos].memory = is_memory_op;
621 register_map[pos].inout_pos = i;
622 register_map[pos].mode = constraint->mode;
626 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
627 const char *c = get_id_str(clobbers[i]);
628 const arch_register_req_t *req;
630 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
633 req = parse_clobber(c);
634 out_reg_reqs[out_idx] = req;
638 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
639 get_ASM_text(node), register_map);
642 be_dep_on_frame(new_node);
644 set_ia32_out_req_all(new_node, out_reg_reqs);
645 set_ia32_in_req_all(new_node, in_reg_reqs);
647 SET_IA32_ORIG_NODE(new_node, node);
652 ir_node *gen_CopyB(ir_node *node) {
653 ir_node *block = NULL;
655 ir_node *new_src = NULL;
657 ir_node *new_dst = NULL;
659 ir_node *new_mem = NULL;
661 dbg_info *dbgi = get_irn_dbg_info(node);
662 int size = get_type_size_bytes(get_CopyB_type(node));
665 switch (be_transformer) {
666 case TRANSFORMER_DEFAULT:
667 block = be_transform_node(get_nodes_block(node));
668 src = get_CopyB_src(node);
669 new_src = be_transform_node(src);
670 dst = get_CopyB_dst(node);
671 new_dst = be_transform_node(dst);
672 mem = get_CopyB_mem(node);
673 new_mem = be_transform_node(mem);
677 case TRANSFORMER_PBQP:
678 case TRANSFORMER_RAND:
679 block = get_nodes_block(node);
680 new_src = get_CopyB_src(node);
681 new_dst = get_CopyB_dst(node);
682 new_mem = get_CopyB_mem(node);
686 default: panic("invalid transformer");
689 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
690 /* then we need the size explicitly in ECX. */
691 if (size >= 32 * 4) {
692 rem = size & 0x3; /* size % 4 */
695 res = new_bd_ia32_Const(dbgi, block, NULL, 0, size);
696 be_dep_on_frame(res);
698 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
701 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
704 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
707 SET_IA32_ORIG_NODE(res, node);
712 ir_node *gen_Proj_tls(ir_node *node) {
713 ir_node *block = NULL;
714 dbg_info *dbgi = NULL;
717 switch (be_transformer) {
718 case TRANSFORMER_DEFAULT:
719 block = be_transform_node(get_nodes_block(node));
723 case TRANSFORMER_PBQP:
724 case TRANSFORMER_RAND:
725 block = get_nodes_block(node);
729 default: panic("invalid transformer");
732 res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
737 ir_node *gen_Unknown(ir_node *node)
739 ir_mode *mode = get_irn_mode(node);
741 if (mode_is_float(mode)) {
742 if (ia32_cg_config.use_sse2) {
743 return ia32_new_Unknown_xmm(env_cg);
745 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
746 ir_graph *irg = current_ir_graph;
747 dbg_info *dbgi = get_irn_dbg_info(node);
748 ir_node *block = get_irg_start_block(irg);
749 ir_node *ret = new_bd_ia32_vfldz(dbgi, block);
751 be_dep_on_frame(ret);
754 } else if (ia32_mode_needs_gp_reg(mode)) {
755 return ia32_new_Unknown_gp(env_cg);
757 panic("unsupported Unknown-Mode");
762 const arch_register_req_t *make_register_req(const constraint_t *constraint,
763 int n_outs, const arch_register_req_t **out_reqs, int pos)
765 struct obstack *obst = get_irg_obstack(current_ir_graph);
766 int same_as = constraint->same_as;
767 arch_register_req_t *req;
770 const arch_register_req_t *other_constr;
772 if (same_as >= n_outs)
773 panic("invalid output number in same_as constraint");
775 other_constr = out_reqs[same_as];
777 req = obstack_alloc(obst, sizeof(req[0]));
778 *req = *other_constr;
779 req->type |= arch_register_req_type_should_be_same;
780 req->other_same = 1U << pos;
782 /* switch constraints. This is because in firm we have same_as
783 * constraints on the output constraints while in the gcc asm syntax
784 * they are specified on the input constraints */
785 out_reqs[same_as] = req;
789 /* pure memory ops */
790 if (constraint->cls == NULL) {
791 return &no_register_req;
794 if (constraint->allowed_registers != 0
795 && !constraint->all_registers_allowed) {
796 unsigned *limited_ptr;
798 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
799 memset(req, 0, sizeof(req[0]));
800 limited_ptr = (unsigned*) (req+1);
802 req->type = arch_register_req_type_limited;
803 *limited_ptr = constraint->allowed_registers;
804 req->limited = limited_ptr;
806 req = obstack_alloc(obst, sizeof(req[0]));
807 memset(req, 0, sizeof(req[0]));
808 req->type = arch_register_req_type_normal;
810 req->cls = constraint->cls;
815 const arch_register_req_t *parse_clobber(const char *clobber)
817 struct obstack *obst = get_irg_obstack(current_ir_graph);
818 const arch_register_t *reg = ia32_get_clobber_register(clobber);
819 arch_register_req_t *req;
823 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
826 assert(reg->index < 32);
828 limited = obstack_alloc(obst, sizeof(limited[0]));
829 *limited = 1 << reg->index;
831 req = obstack_alloc(obst, sizeof(req[0]));
832 memset(req, 0, sizeof(req[0]));
833 req->type = arch_register_req_type_limited;
834 req->cls = arch_register_get_class(reg);
835 req->limited = limited;
841 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
842 ir_node *const other)
844 if (get_nodes_block(other) != block)
847 if (is_Sync(other)) {
850 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
851 ir_node *const pred = get_Sync_pred(other, i);
853 if (get_nodes_block(pred) != block)
856 /* Do not block ourselves from getting eaten */
857 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
860 if (!heights_reachable_in_block(heights, pred, am_candidate))
868 /* Do not block ourselves from getting eaten */
869 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
872 if (!heights_reachable_in_block(heights, other, am_candidate))
879 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
882 tarval *offset = NULL;
885 ir_entity *symconst_ent = NULL;
886 int symconst_sign = 0;
888 ir_node *cnst = NULL;
889 ir_node *symconst = NULL;
892 mode = get_irn_mode(node);
893 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
897 if (is_Minus(node)) {
899 node = get_Minus_op(node);
902 if (is_Const(node)) {
906 } else if (is_SymConst(node)) {
909 symconst_sign = minus;
910 } else if (is_Add(node)) {
911 ir_node *left = get_Add_left(node);
912 ir_node *right = get_Add_right(node);
913 if (is_Const(left) && is_SymConst(right)) {
916 symconst_sign = minus;
918 } else if (is_SymConst(left) && is_Const(right)) {
921 symconst_sign = minus;
924 } else if (is_Sub(node)) {
925 ir_node *left = get_Sub_left(node);
926 ir_node *right = get_Sub_right(node);
927 if (is_Const(left) && is_SymConst(right)) {
930 symconst_sign = !minus;
932 } else if (is_SymConst(left) && is_Const(right)) {
935 symconst_sign = minus;
936 offset_sign = !minus;
943 offset = get_Const_tarval(cnst);
944 if (tarval_is_long(offset)) {
945 val = get_tarval_long(offset);
947 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
952 if (!check_immediate_constraint(val, immediate_constraint_type))
955 if (symconst != NULL) {
956 if (immediate_constraint_type != 0) {
957 /* we need full 32bits for symconsts */
961 /* unfortunately the assembler/linker doesn't support -symconst */
965 if (get_SymConst_kind(symconst) != symconst_addr_ent)
967 symconst_ent = get_SymConst_entity(symconst);
969 if (cnst == NULL && symconst == NULL)
972 if (offset_sign && offset != NULL) {
973 offset = tarval_neg(offset);
976 new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val);