2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
36 #include "betranshlp.h"
40 #include "ia32_architecture.h"
41 #include "ia32_common_transform.h"
42 #include "ia32_new_nodes.h"
44 #include "gen_ia32_new_nodes.h"
45 #include "gen_ia32_regalloc_if.h"
47 ir_heights_t *ia32_heights = NULL;
49 static int check_immediate_constraint(long val, char immediate_constraint_type)
51 switch (immediate_constraint_type) {
55 case 'I': return 0 <= val && val <= 31;
56 case 'J': return 0 <= val && val <= 63;
57 case 'K': return -128 <= val && val <= 127;
58 case 'L': return val == 0xff || val == 0xffff;
59 case 'M': return 0 <= val && val <= 3;
60 case 'N': return 0 <= val && val <= 255;
61 case 'O': return 0 <= val && val <= 127;
63 default: panic("Invalid immediate constraint found");
67 ir_type *ia32_get_prim_type(const ir_mode *mode)
69 if (mode == ia32_mode_E) {
72 return get_type_for_mode(mode);
76 ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
79 ir_entity *res = (ir_entity*)pmap_get(isa->tv_ent, tv);
80 ir_initializer_t *initializer;
87 mode = get_tarval_mode(tv);
89 if (! ia32_cg_config.use_sse2) {
90 /* try to reduce the mode to produce smaller sized entities */
92 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
94 tv = tarval_convert_to(tv, mode);
95 } else if (mode != mode_D) {
96 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
98 tv = tarval_convert_to(tv, mode);
105 name = id_unique("C%u");
107 tp = ia32_get_prim_type(mode);
108 res = new_entity(get_glob_type(), name, tp);
109 set_entity_ld_ident(res, get_entity_ident(res));
110 set_entity_visibility(res, ir_visibility_private);
111 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
113 initializer = create_initializer_tarval(tv);
114 set_entity_initializer(res, initializer);
116 pmap_insert(isa->tv_ent, tv, res);
120 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
122 ir_graph *irg = current_ir_graph;
123 ir_node *start_block = get_irg_start_block(irg);
124 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
125 symconst_sign, ia32_no_pic_adjust, val);
126 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
131 const arch_register_t *ia32_get_clobber_register(const char *clobber)
133 const arch_register_t *reg = NULL;
136 const arch_register_class_t *cls;
138 /* TODO: construct a hashmap instead of doing linear search for clobber
140 for (c = 0; c < N_IA32_CLASSES; ++c) {
141 cls = & ia32_reg_classes[c];
142 for (r = 0; r < cls->n_regs; ++r) {
143 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
144 if (strcmp(temp_reg->name, clobber) == 0
145 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
157 int ia32_mode_needs_gp_reg(ir_mode *mode)
159 if (mode == ia32_mode_fpcw)
161 if (get_mode_size_bits(mode) > 32)
163 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
166 static void parse_asm_constraints(constraint_t *constraint, const char *c,
169 char immediate_type = '\0';
170 unsigned limited = 0;
171 const arch_register_class_t *cls = NULL;
172 int memory_possible = 0;
173 int all_registers_allowed = 0;
177 memset(constraint, 0, sizeof(constraint[0]));
178 constraint->same_as = -1;
181 /* a memory constraint: no need to do anything in backend about it
182 * (the dependencies are already respected by the memory edge of
187 /* TODO: improve error messages with node and source info. (As users can
188 * easily hit these) */
196 /* Skip out/in-out marker */
206 while (*c != 0 && *c != ',')
211 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
212 cls = &ia32_reg_classes[CLASS_ia32_gp];
213 limited |= 1 << REG_GP_EAX;
216 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
217 cls = &ia32_reg_classes[CLASS_ia32_gp];
218 limited |= 1 << REG_GP_EBX;
221 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
222 cls = &ia32_reg_classes[CLASS_ia32_gp];
223 limited |= 1 << REG_GP_ECX;
226 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
227 cls = &ia32_reg_classes[CLASS_ia32_gp];
228 limited |= 1 << REG_GP_EDX;
231 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
232 cls = &ia32_reg_classes[CLASS_ia32_gp];
233 limited |= 1 << REG_GP_EDI;
236 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
237 cls = &ia32_reg_classes[CLASS_ia32_gp];
238 limited |= 1 << REG_GP_ESI;
242 /* q means lower part of the regs only, this makes no
243 * difference to Q for us (we only assign whole registers) */
244 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
245 cls = &ia32_reg_classes[CLASS_ia32_gp];
246 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
250 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
251 cls = &ia32_reg_classes[CLASS_ia32_gp];
252 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
255 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
256 cls = &ia32_reg_classes[CLASS_ia32_gp];
257 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
258 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
265 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
266 panic("multiple register classes not supported");
267 cls = &ia32_reg_classes[CLASS_ia32_gp];
268 all_registers_allowed = 1;
274 /* TODO: mark values so the x87 simulator knows about t and u */
275 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
276 panic("multiple register classes not supported");
277 cls = &ia32_reg_classes[CLASS_ia32_vfp];
278 all_registers_allowed = 1;
283 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
284 panic("multiple register classes not supproted");
285 cls = &ia32_reg_classes[CLASS_ia32_xmm];
286 all_registers_allowed = 1;
296 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
297 panic("multiple register classes not supported");
298 if (immediate_type != '\0')
299 panic("multiple immediate types not supported");
300 cls = &ia32_reg_classes[CLASS_ia32_gp];
305 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
306 panic("multiple register classes not supported");
307 if (immediate_type != '\0')
308 panic("multiple immediate types not supported");
309 cls = &ia32_reg_classes[CLASS_ia32_gp];
310 immediate_type = 'i';
315 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
316 panic("multiple register classes not supported");
317 if (immediate_type != '\0')
318 panic("multiple immediate types not supported");
319 immediate_type = 'i';
320 cls = &ia32_reg_classes[CLASS_ia32_gp];
321 all_registers_allowed = 1;
336 panic("can only specify same constraint on input");
338 sscanf(c, "%d%n", &same_as, &p);
348 /* memory constraint no need to do anything in backend about it
349 * (the dependencies are already respected by the memory edge of
354 case 'E': /* no float consts yet */
355 case 'F': /* no float consts yet */
356 case 's': /* makes no sense on x86 */
357 case '<': /* no autodecrement on x86 */
358 case '>': /* no autoincrement on x86 */
359 case 'C': /* sse constant not supported yet */
360 case 'G': /* 80387 constant not supported yet */
361 case 'y': /* we don't support mmx registers yet */
362 case 'Z': /* not available in 32 bit mode */
363 case 'e': /* not available in 32 bit mode */
364 panic("unsupported asm constraint '%c' found in (%+F)",
365 *c, current_ir_graph);
367 panic("unknown asm constraint '%c' found in (%+F)", *c,
375 panic("same as and register constraint not supported");
376 if (immediate_type != '\0')
377 panic("same as and immediate constraint not supported");
380 if (cls == NULL && same_as < 0) {
381 if (!memory_possible)
382 panic("no constraint specified for assembler input");
385 constraint->same_as = same_as;
386 constraint->cls = cls;
387 constraint->allowed_registers = limited;
388 constraint->all_registers_allowed = all_registers_allowed;
389 constraint->memory_possible = memory_possible;
390 constraint->immediate_type = immediate_type;
393 static bool can_match(const arch_register_req_t *in,
394 const arch_register_req_t *out)
396 if (in->cls != out->cls)
398 if ( (in->type & arch_register_req_type_limited) == 0
399 || (out->type & arch_register_req_type_limited) == 0 )
402 return (*in->limited & *out->limited) != 0;
405 static inline ir_node *get_new_node(ir_node *node)
408 if (be_transformer == TRANSFORMER_DEFAULT) {
409 return be_transform_node(node);
414 return be_transform_node(node);
418 ir_node *ia32_gen_ASM(ir_node *node)
420 ir_node *block = get_nodes_block(node);
421 ir_node *new_block = get_new_node(block);
422 dbg_info *dbgi = get_irn_dbg_info(node);
429 int n_out_constraints;
431 const arch_register_req_t **out_reg_reqs;
432 const arch_register_req_t **in_reg_reqs;
433 ia32_asm_reg_t *register_map;
434 unsigned reg_map_size = 0;
435 struct obstack *obst;
436 const ir_asm_constraint *in_constraints;
437 const ir_asm_constraint *out_constraints;
439 unsigned clobber_bits[N_IA32_CLASSES];
441 backend_info_t *info;
443 memset(&clobber_bits, 0, sizeof(clobber_bits));
445 arity = get_irn_arity(node);
446 in = ALLOCANZ(ir_node*, arity);
448 clobbers = get_ASM_clobbers(node);
450 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
451 const arch_register_req_t *req;
452 const char *c = get_id_str(clobbers[i]);
454 if (strcmp(c, "memory") == 0)
456 if (strcmp(c, "cc") == 0) {
460 req = ia32_parse_clobber(c);
461 clobber_bits[req->cls->index] |= *req->limited;
465 n_out_constraints = get_ASM_n_output_constraints(node);
466 out_arity = n_out_constraints + n_clobbers;
468 in_constraints = get_ASM_input_constraints(node);
469 out_constraints = get_ASM_output_constraints(node);
471 /* determine size of register_map */
472 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
473 const ir_asm_constraint *constraint = &out_constraints[out_idx];
474 if (constraint->pos > reg_map_size)
475 reg_map_size = constraint->pos;
477 for (i = 0; i < arity; ++i) {
478 const ir_asm_constraint *constraint = &in_constraints[i];
479 if (constraint->pos > reg_map_size)
480 reg_map_size = constraint->pos;
484 obst = get_irg_obstack(current_ir_graph);
485 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
486 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
488 /* construct output constraints */
489 out_size = out_arity + 1;
490 out_reg_reqs = OALLOCN(obst, const arch_register_req_t*, out_size);
492 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
493 const ir_asm_constraint *constraint = &out_constraints[out_idx];
494 const char *c = get_id_str(constraint->constraint);
495 unsigned pos = constraint->pos;
496 constraint_t parsed_constraint;
497 const arch_register_req_t *req;
499 parse_asm_constraints(&parsed_constraint, c, 1);
500 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
501 out_reg_reqs, out_idx);
502 out_reg_reqs[out_idx] = req;
504 /* multiple constraints for same pos. This can happen for example when
505 * a =A constraint gets lowered to two constraints: =a and =d for the
507 if (register_map[pos].valid)
510 register_map[pos].use_input = 0;
511 register_map[pos].valid = 1;
512 register_map[pos].memory = 0;
513 register_map[pos].inout_pos = out_idx;
514 register_map[pos].mode = constraint->mode;
517 /* inputs + input constraints */
518 in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, arity);
519 for (i = 0; i < arity; ++i) {
520 ir_node *pred = get_irn_n(node, i);
521 const ir_asm_constraint *constraint = &in_constraints[i];
522 ident *constr_id = constraint->constraint;
523 const char *c = get_id_str(constr_id);
524 unsigned pos = constraint->pos;
525 int is_memory_op = 0;
526 ir_node *input = NULL;
527 unsigned r_clobber_bits;
528 constraint_t parsed_constraint;
529 const arch_register_req_t *req;
531 parse_asm_constraints(&parsed_constraint, c, 0);
532 if (parsed_constraint.cls != NULL) {
533 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
534 if (r_clobber_bits != 0) {
535 if (parsed_constraint.all_registers_allowed) {
536 parsed_constraint.all_registers_allowed = 0;
537 be_set_allocatable_regs(current_ir_graph,
538 parsed_constraint.cls,
539 &parsed_constraint.allowed_registers);
541 parsed_constraint.allowed_registers &= ~r_clobber_bits;
545 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
547 in_reg_reqs[i] = req;
549 if (parsed_constraint.immediate_type != '\0') {
550 char imm_type = parsed_constraint.immediate_type;
551 input = ia32_try_create_Immediate(pred, imm_type);
555 input = get_new_node(pred);
557 if (parsed_constraint.cls == NULL
558 && parsed_constraint.same_as < 0) {
560 } else if (parsed_constraint.memory_possible) {
561 /* TODO: match Load or Load/Store if memory possible is set */
566 register_map[pos].use_input = 1;
567 register_map[pos].valid = 1;
568 register_map[pos].memory = is_memory_op;
569 register_map[pos].inout_pos = i;
570 register_map[pos].mode = constraint->mode;
574 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
575 const char *c = get_id_str(clobbers[i]);
576 const arch_register_req_t *req;
578 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
581 req = ia32_parse_clobber(c);
582 out_reg_reqs[out_idx] = req;
586 /* count inputs which are real values (and not memory) */
588 for (i = 0; i < arity; ++i) {
589 ir_node *node_in = get_irn_n(node, i);
590 if (get_irn_mode(node_in) == mode_M)
595 /* Attempt to make ASM node register pressure faithful.
596 * (This does not work for complicated cases yet!)
598 * Algorithm: Check if there are fewer inputs or outputs (I will call this
599 * the smaller list). Then try to match each constraint of the smaller list
600 * to 1 of the other list. If we can't match it, then we have to add a dummy
601 * input/output to the other list
603 * FIXME: This is still broken in lots of cases. But at least better than
605 * FIXME: need to do this per register class...
607 if (out_arity <= value_arity) {
608 int orig_arity = arity;
611 bitset_t *used_ins = bitset_alloca(arity);
612 for (o = 0; o < out_arity; ++o) {
613 const arch_register_req_t *outreq = out_reg_reqs[o];
615 if (outreq->cls == NULL) {
619 for (i = 0; i < orig_arity; ++i) {
620 const arch_register_req_t *inreq;
621 if (bitset_is_set(used_ins, i))
623 inreq = in_reg_reqs[i];
624 if (!can_match(outreq, inreq))
626 bitset_set(used_ins, i);
629 /* did we find any match? */
633 /* we might need more space in the input arrays */
634 if (arity >= in_size) {
635 const arch_register_req_t **new_in_reg_reqs;
639 new_in_reg_reqs = OALLOCN(obst, const arch_register_req_t*,
641 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
642 new_in = ALLOCANZ(ir_node*, in_size);
643 memcpy(new_in, in, arity*sizeof(new_in[0]));
645 in_reg_reqs = new_in_reg_reqs;
649 /* add a new (dummy) input which occupies the register */
650 assert(outreq->type & arch_register_req_type_limited);
651 in_reg_reqs[arity] = outreq;
652 in[arity] = new_bd_ia32_ProduceVal(NULL, block);
656 bitset_t *used_outs = bitset_alloca(out_arity);
657 int orig_out_arity = out_arity;
658 for (i = 0; i < arity; ++i) {
660 const arch_register_req_t *inreq = in_reg_reqs[i];
662 if (inreq->cls == NULL) {
666 for (o = 0; o < orig_out_arity; ++o) {
667 const arch_register_req_t *outreq;
668 if (bitset_is_set(used_outs, o))
670 outreq = out_reg_reqs[o];
671 if (!can_match(outreq, inreq))
673 bitset_set(used_outs, i);
676 /* did we find any match? */
677 if (o < orig_out_arity)
680 /* we might need more space in the output arrays */
681 if (out_arity >= out_size) {
682 const arch_register_req_t **new_out_reg_reqs;
686 = OALLOCN(obst, const arch_register_req_t*, out_size);
687 memcpy(new_out_reg_reqs, out_reg_reqs,
688 out_arity * sizeof(new_out_reg_reqs[0]));
689 out_reg_reqs = new_out_reg_reqs;
692 /* add a new (dummy) output which occupies the register */
693 assert(inreq->type & arch_register_req_type_limited);
694 out_reg_reqs[out_arity] = inreq;
699 /* append none register requirement for the memory output */
700 if (out_arity + 1 >= out_size) {
701 const arch_register_req_t **new_out_reg_reqs;
703 out_size = out_arity + 1;
705 = OALLOCN(obst, const arch_register_req_t*, out_size);
706 memcpy(new_out_reg_reqs, out_reg_reqs,
707 out_arity * sizeof(new_out_reg_reqs[0]));
708 out_reg_reqs = new_out_reg_reqs;
711 /* add a new (dummy) output which occupies the register */
712 out_reg_reqs[out_arity] = arch_no_register_req;
715 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
716 get_ASM_text(node), register_map);
718 info = be_get_info(new_node);
719 for (i = 0; i < out_arity; ++i) {
720 info->out_infos[i].req = out_reg_reqs[i];
722 arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
724 SET_IA32_ORIG_NODE(new_node, node);
729 ir_node *ia32_gen_CopyB(ir_node *node)
731 ir_node *block = get_new_node(get_nodes_block(node));
732 ir_node *src = get_CopyB_src(node);
733 ir_node *new_src = get_new_node(src);
734 ir_node *dst = get_CopyB_dst(node);
735 ir_node *new_dst = get_new_node(dst);
736 ir_node *mem = get_CopyB_mem(node);
737 ir_node *new_mem = get_new_node(mem);
739 dbg_info *dbgi = get_irn_dbg_info(node);
740 int size = get_type_size_bytes(get_CopyB_type(node));
741 int throws_exception = ir_throws_exception(node);
744 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
745 /* then we need the size explicitly in ECX. */
746 if (size >= 32 * 4) {
747 rem = size & 0x3; /* size % 4 */
750 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
752 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
755 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
758 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
760 ir_set_throws_exception(res, throws_exception);
762 SET_IA32_ORIG_NODE(res, node);
767 ir_node *ia32_gen_Proj_tls(ir_node *node)
769 ir_node *block = get_new_node(get_nodes_block(node));
770 ir_node *res = new_bd_ia32_LdTls(NULL, block);
774 ir_node *ia32_gen_Unknown(ir_node *node)
776 ir_mode *mode = get_irn_mode(node);
777 ir_graph *irg = current_ir_graph;
778 dbg_info *dbgi = get_irn_dbg_info(node);
779 ir_node *block = get_irg_start_block(irg);
782 if (mode_is_float(mode)) {
783 if (ia32_cg_config.use_sse2) {
784 res = new_bd_ia32_xUnknown(dbgi, block);
786 res = new_bd_ia32_vfldz(dbgi, block);
788 } else if (ia32_mode_needs_gp_reg(mode)) {
789 res = new_bd_ia32_Unknown(dbgi, block);
791 panic("unsupported Unknown-Mode");
797 const arch_register_req_t *ia32_make_register_req(const constraint_t *constraint,
798 int n_outs, const arch_register_req_t **out_reqs, int pos)
800 struct obstack *obst = get_irg_obstack(current_ir_graph);
801 int same_as = constraint->same_as;
802 arch_register_req_t *req;
805 const arch_register_req_t *other_constr;
807 if (same_as >= n_outs)
808 panic("invalid output number in same_as constraint");
810 other_constr = out_reqs[same_as];
812 req = OALLOC(obst, arch_register_req_t);
813 *req = *other_constr;
814 req->type |= arch_register_req_type_should_be_same;
815 req->other_same = 1U << pos;
818 /* switch constraints. This is because in firm we have same_as
819 * constraints on the output constraints while in the gcc asm syntax
820 * they are specified on the input constraints */
821 out_reqs[same_as] = req;
825 /* pure memory ops */
826 if (constraint->cls == NULL) {
827 return arch_no_register_req;
830 if (constraint->allowed_registers != 0
831 && !constraint->all_registers_allowed) {
832 unsigned *limited_ptr;
834 req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
835 memset(req, 0, sizeof(req[0]));
836 limited_ptr = (unsigned*) (req+1);
838 req->type = arch_register_req_type_limited;
839 *limited_ptr = constraint->allowed_registers;
840 req->limited = limited_ptr;
842 req = OALLOCZ(obst, arch_register_req_t);
843 req->type = arch_register_req_type_normal;
845 req->cls = constraint->cls;
851 const arch_register_req_t *ia32_parse_clobber(const char *clobber)
853 struct obstack *obst = get_irg_obstack(current_ir_graph);
854 const arch_register_t *reg = ia32_get_clobber_register(clobber);
855 arch_register_req_t *req;
859 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
862 assert(reg->index < 32);
864 limited = OALLOC(obst, unsigned);
865 *limited = 1 << reg->index;
867 req = OALLOCZ(obst, arch_register_req_t);
868 req->type = arch_register_req_type_limited;
869 req->cls = arch_register_get_class(reg);
870 req->limited = limited;
877 int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
878 ir_node *const other)
880 if (get_nodes_block(other) != block)
883 if (is_Sync(other)) {
886 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
887 ir_node *const pred = get_Sync_pred(other, i);
889 if (get_nodes_block(pred) != block)
892 /* Do not block ourselves from getting eaten */
893 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
896 if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
904 /* Do not block ourselves from getting eaten */
905 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
908 if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
915 ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
918 ir_entity *symconst_ent = NULL;
920 ir_node *cnst = NULL;
921 ir_node *symconst = NULL;
924 mode = get_irn_mode(node);
925 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
929 if (is_Const(node)) {
932 } else if (is_SymConst_addr_ent(node)
933 && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
936 } else if (is_Add(node)) {
937 ir_node *left = get_Add_left(node);
938 ir_node *right = get_Add_right(node);
939 if (is_Const(left) && is_SymConst_addr_ent(right)) {
942 } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
951 ir_tarval *offset = get_Const_tarval(cnst);
952 if (!tarval_is_long(offset)) {
953 ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
957 val = get_tarval_long(offset);
958 if (!check_immediate_constraint(val, immediate_constraint_type))
961 if (symconst != NULL) {
962 if (immediate_constraint_type != 0) {
963 /* we need full 32bits for symconsts */
967 symconst_ent = get_SymConst_entity(symconst);
969 if (cnst == NULL && symconst == NULL)
972 new_node = ia32_create_Immediate(symconst_ent, 0, val);