2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
35 #include "betranshlp.h"
39 #include "ia32_architecture.h"
40 #include "ia32_common_transform.h"
41 #include "ia32_new_nodes.h"
43 #include "gen_ia32_new_nodes.h"
44 #include "gen_ia32_regalloc_if.h"
46 ir_heights_t *ia32_heights = NULL;
48 static int check_immediate_constraint(long val, char immediate_constraint_type)
50 switch (immediate_constraint_type) {
54 case 'I': return 0 <= val && val <= 31;
55 case 'J': return 0 <= val && val <= 63;
56 case 'K': return -128 <= val && val <= 127;
57 case 'L': return val == 0xff || val == 0xffff;
58 case 'M': return 0 <= val && val <= 3;
59 case 'N': return 0 <= val && val <= 255;
60 case 'O': return 0 <= val && val <= 127;
62 default: panic("Invalid immediate constraint found");
66 ir_type *ia32_get_prim_type(const ir_mode *mode)
68 if (mode == ia32_mode_E) {
71 return get_type_for_mode(mode);
75 ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
78 ir_entity *res = (ir_entity*)pmap_get(isa->tv_ent, tv);
79 ir_initializer_t *initializer;
86 mode = get_tarval_mode(tv);
88 if (! ia32_cg_config.use_sse2) {
89 /* try to reduce the mode to produce smaller sized entities */
91 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
93 tv = tarval_convert_to(tv, mode);
94 } else if (mode != mode_D) {
95 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
97 tv = tarval_convert_to(tv, mode);
104 name = id_unique("C%u");
106 tp = ia32_get_prim_type(mode);
107 res = new_entity(get_glob_type(), name, tp);
108 set_entity_ld_ident(res, get_entity_ident(res));
109 set_entity_visibility(res, ir_visibility_private);
110 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
112 initializer = create_initializer_tarval(tv);
113 set_entity_initializer(res, initializer);
115 pmap_insert(isa->tv_ent, tv, res);
119 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
121 ir_graph *irg = current_ir_graph;
122 ir_node *start_block = get_irg_start_block(irg);
123 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
124 symconst_sign, ia32_no_pic_adjust, val);
125 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
130 const arch_register_t *ia32_get_clobber_register(const char *clobber)
132 const arch_register_t *reg = NULL;
135 const arch_register_class_t *cls;
137 /* TODO: construct a hashmap instead of doing linear search for clobber
139 for (c = 0; c < N_IA32_CLASSES; ++c) {
140 cls = & ia32_reg_classes[c];
141 for (r = 0; r < cls->n_regs; ++r) {
142 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
143 if (strcmp(temp_reg->name, clobber) == 0
144 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
156 int ia32_mode_needs_gp_reg(ir_mode *mode)
158 if (mode == ia32_mode_fpcw)
160 if (get_mode_size_bits(mode) > 32)
162 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
165 static void parse_asm_constraints(constraint_t *constraint, const char *c,
168 char immediate_type = '\0';
169 unsigned limited = 0;
170 const arch_register_class_t *cls = NULL;
171 int memory_possible = 0;
172 int all_registers_allowed = 0;
176 memset(constraint, 0, sizeof(constraint[0]));
177 constraint->same_as = -1;
180 /* a memory constraint: no need to do anything in backend about it
181 * (the dependencies are already respected by the memory edge of
186 /* TODO: improve error messages with node and source info. (As users can
187 * easily hit these) */
195 /* Skip out/in-out marker */
205 while (*c != 0 && *c != ',')
210 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
211 cls = &ia32_reg_classes[CLASS_ia32_gp];
212 limited |= 1 << REG_GP_EAX;
215 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
216 cls = &ia32_reg_classes[CLASS_ia32_gp];
217 limited |= 1 << REG_GP_EBX;
220 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
221 cls = &ia32_reg_classes[CLASS_ia32_gp];
222 limited |= 1 << REG_GP_ECX;
225 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
226 cls = &ia32_reg_classes[CLASS_ia32_gp];
227 limited |= 1 << REG_GP_EDX;
230 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
231 cls = &ia32_reg_classes[CLASS_ia32_gp];
232 limited |= 1 << REG_GP_EDI;
235 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
236 cls = &ia32_reg_classes[CLASS_ia32_gp];
237 limited |= 1 << REG_GP_ESI;
241 /* q means lower part of the regs only, this makes no
242 * difference to Q for us (we only assign whole registers) */
243 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
244 cls = &ia32_reg_classes[CLASS_ia32_gp];
245 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
249 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
250 cls = &ia32_reg_classes[CLASS_ia32_gp];
251 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
254 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
255 cls = &ia32_reg_classes[CLASS_ia32_gp];
256 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
257 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
264 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
265 panic("multiple register classes not supported");
266 cls = &ia32_reg_classes[CLASS_ia32_gp];
267 all_registers_allowed = 1;
273 /* TODO: mark values so the x87 simulator knows about t and u */
274 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
275 panic("multiple register classes not supported");
276 cls = &ia32_reg_classes[CLASS_ia32_vfp];
277 all_registers_allowed = 1;
282 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
283 panic("multiple register classes not supproted");
284 cls = &ia32_reg_classes[CLASS_ia32_xmm];
285 all_registers_allowed = 1;
295 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
296 panic("multiple register classes not supported");
297 if (immediate_type != '\0')
298 panic("multiple immediate types not supported");
299 cls = &ia32_reg_classes[CLASS_ia32_gp];
304 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
305 panic("multiple register classes not supported");
306 if (immediate_type != '\0')
307 panic("multiple immediate types not supported");
308 cls = &ia32_reg_classes[CLASS_ia32_gp];
309 immediate_type = 'i';
314 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
315 panic("multiple register classes not supported");
316 if (immediate_type != '\0')
317 panic("multiple immediate types not supported");
318 immediate_type = 'i';
319 cls = &ia32_reg_classes[CLASS_ia32_gp];
320 all_registers_allowed = 1;
335 panic("can only specify same constraint on input");
337 sscanf(c, "%d%n", &same_as, &p);
347 /* memory constraint no need to do anything in backend about it
348 * (the dependencies are already respected by the memory edge of
353 case 'E': /* no float consts yet */
354 case 'F': /* no float consts yet */
355 case 's': /* makes no sense on x86 */
356 case '<': /* no autodecrement on x86 */
357 case '>': /* no autoincrement on x86 */
358 case 'C': /* sse constant not supported yet */
359 case 'G': /* 80387 constant not supported yet */
360 case 'y': /* we don't support mmx registers yet */
361 case 'Z': /* not available in 32 bit mode */
362 case 'e': /* not available in 32 bit mode */
363 panic("unsupported asm constraint '%c' found in (%+F)",
364 *c, current_ir_graph);
366 panic("unknown asm constraint '%c' found in (%+F)", *c,
374 panic("same as and register constraint not supported");
375 if (immediate_type != '\0')
376 panic("same as and immediate constraint not supported");
379 if (cls == NULL && same_as < 0) {
380 if (!memory_possible)
381 panic("no constraint specified for assembler input");
384 constraint->same_as = same_as;
385 constraint->cls = cls;
386 constraint->allowed_registers = limited;
387 constraint->all_registers_allowed = all_registers_allowed;
388 constraint->memory_possible = memory_possible;
389 constraint->immediate_type = immediate_type;
392 static bool can_match(const arch_register_req_t *in,
393 const arch_register_req_t *out)
395 if (in->cls != out->cls)
397 if ( (in->type & arch_register_req_type_limited) == 0
398 || (out->type & arch_register_req_type_limited) == 0 )
401 return (*in->limited & *out->limited) != 0;
404 static inline ir_node *get_new_node(ir_node *node)
407 if (be_transformer == TRANSFORMER_DEFAULT) {
408 return be_transform_node(node);
413 return be_transform_node(node);
417 ir_node *ia32_gen_ASM(ir_node *node)
419 ir_node *block = get_nodes_block(node);
420 ir_node *new_block = get_new_node(block);
421 dbg_info *dbgi = get_irn_dbg_info(node);
428 size_t n_out_constraints;
430 const arch_register_req_t **out_reg_reqs;
431 const arch_register_req_t **in_reg_reqs;
432 ia32_asm_reg_t *register_map;
433 unsigned reg_map_size = 0;
434 struct obstack *obst;
435 const ir_asm_constraint *in_constraints;
436 const ir_asm_constraint *out_constraints;
438 unsigned clobber_bits[N_IA32_CLASSES];
440 backend_info_t *info;
445 memset(&clobber_bits, 0, sizeof(clobber_bits));
447 arity = get_irn_arity(node);
448 in = ALLOCANZ(ir_node*, arity);
450 clobbers = get_ASM_clobbers(node);
452 for (c = 0; c < get_ASM_n_clobbers(node); ++c) {
453 const arch_register_req_t *req;
454 const char *clobber = get_id_str(clobbers[c]);
456 if (strcmp(clobber, "memory") == 0)
458 if (strcmp(clobber, "cc") == 0) {
462 req = ia32_parse_clobber(clobber);
463 clobber_bits[req->cls->index] |= *req->limited;
467 n_out_constraints = get_ASM_n_output_constraints(node);
468 out_arity = n_out_constraints + n_clobbers;
470 in_constraints = get_ASM_input_constraints(node);
471 out_constraints = get_ASM_output_constraints(node);
473 /* determine size of register_map */
474 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
475 const ir_asm_constraint *constraint = &out_constraints[out_idx];
476 if (constraint->pos > reg_map_size)
477 reg_map_size = constraint->pos;
479 for (i = 0; i < arity; ++i) {
480 const ir_asm_constraint *constraint = &in_constraints[i];
481 if (constraint->pos > reg_map_size)
482 reg_map_size = constraint->pos;
486 obst = get_irg_obstack(current_ir_graph);
487 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
488 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
490 /* construct output constraints */
491 out_size = out_arity + 1;
492 out_reg_reqs = OALLOCN(obst, const arch_register_req_t*, out_size);
494 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
495 const ir_asm_constraint *constraint = &out_constraints[out_idx];
496 const char *c = get_id_str(constraint->constraint);
497 unsigned pos = constraint->pos;
498 constraint_t parsed_constraint;
499 const arch_register_req_t *req;
501 parse_asm_constraints(&parsed_constraint, c, true);
502 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
503 out_reg_reqs, out_idx);
504 out_reg_reqs[out_idx] = req;
506 /* multiple constraints for same pos. This can happen for example when
507 * a =A constraint gets lowered to two constraints: =a and =d for the
509 if (register_map[pos].valid)
512 register_map[pos].use_input = 0;
513 register_map[pos].valid = 1;
514 register_map[pos].memory = 0;
515 register_map[pos].inout_pos = out_idx;
516 register_map[pos].mode = constraint->mode;
519 /* inputs + input constraints */
520 in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, arity);
521 for (i = 0; i < arity; ++i) {
522 ir_node *pred = get_irn_n(node, i);
523 const ir_asm_constraint *constraint = &in_constraints[i];
524 ident *constr_id = constraint->constraint;
525 const char *c = get_id_str(constr_id);
526 unsigned pos = constraint->pos;
527 int is_memory_op = 0;
528 ir_node *input = NULL;
529 unsigned r_clobber_bits;
530 constraint_t parsed_constraint;
531 const arch_register_req_t *req;
533 parse_asm_constraints(&parsed_constraint, c, false);
534 if (parsed_constraint.cls != NULL) {
535 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
536 if (r_clobber_bits != 0) {
537 if (parsed_constraint.all_registers_allowed) {
538 parsed_constraint.all_registers_allowed = 0;
539 be_set_allocatable_regs(current_ir_graph,
540 parsed_constraint.cls,
541 &parsed_constraint.allowed_registers);
543 parsed_constraint.allowed_registers &= ~r_clobber_bits;
547 req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
549 in_reg_reqs[i] = req;
551 if (parsed_constraint.immediate_type != '\0') {
552 char imm_type = parsed_constraint.immediate_type;
553 input = ia32_try_create_Immediate(pred, imm_type);
557 input = get_new_node(pred);
559 if (parsed_constraint.cls == NULL
560 && parsed_constraint.same_as < 0) {
562 } else if (parsed_constraint.memory_possible) {
563 /* TODO: match Load or Load/Store if memory possible is set */
568 register_map[pos].use_input = 1;
569 register_map[pos].valid = 1;
570 register_map[pos].memory = is_memory_op;
571 register_map[pos].inout_pos = i;
572 register_map[pos].mode = constraint->mode;
576 for (c = 0; c < get_ASM_n_clobbers(node); ++c) {
577 const char *clobber = get_id_str(clobbers[c]);
578 const arch_register_req_t *req;
580 if (strcmp(clobber, "memory") == 0 || strcmp(clobber, "cc") == 0)
583 req = ia32_parse_clobber(clobber);
584 out_reg_reqs[out_idx] = req;
588 /* count inputs which are real values (and not memory) */
590 for (i = 0; i < arity; ++i) {
591 ir_node *node_in = get_irn_n(node, i);
592 if (get_irn_mode(node_in) == mode_M)
597 /* Attempt to make ASM node register pressure faithful.
598 * (This does not work for complicated cases yet!)
600 * Algorithm: Check if there are fewer inputs or outputs (I will call this
601 * the smaller list). Then try to match each constraint of the smaller list
602 * to 1 of the other list. If we can't match it, then we have to add a dummy
603 * input/output to the other list
605 * FIXME: This is still broken in lots of cases. But at least better than
607 * FIXME: need to do this per register class...
609 if (out_arity <= value_arity) {
610 int orig_arity = arity;
612 bitset_t *used_ins = bitset_alloca(arity);
614 for (o = 0; o < out_arity; ++o) {
615 const arch_register_req_t *outreq = out_reg_reqs[o];
617 if (outreq->cls == NULL) {
621 for (i = 0; i < orig_arity; ++i) {
622 const arch_register_req_t *inreq;
623 if (bitset_is_set(used_ins, i))
625 inreq = in_reg_reqs[i];
626 if (!can_match(outreq, inreq))
628 bitset_set(used_ins, i);
631 /* did we find any match? */
635 /* we might need more space in the input arrays */
636 if (arity >= in_size) {
637 const arch_register_req_t **new_in_reg_reqs;
641 new_in_reg_reqs = OALLOCN(obst, const arch_register_req_t*,
643 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
644 new_in = ALLOCANZ(ir_node*, in_size);
645 memcpy(new_in, in, arity*sizeof(new_in[0]));
647 in_reg_reqs = new_in_reg_reqs;
651 /* add a new (dummy) input which occupies the register */
652 assert(outreq->type & arch_register_req_type_limited);
653 in_reg_reqs[arity] = outreq;
654 in[arity] = new_bd_ia32_ProduceVal(NULL, block);
658 bitset_t *used_outs = bitset_alloca(out_arity);
659 size_t orig_out_arity = out_arity;
660 for (i = 0; i < arity; ++i) {
661 const arch_register_req_t *inreq = in_reg_reqs[i];
664 if (inreq->cls == NULL) {
668 for (o = 0; o < orig_out_arity; ++o) {
669 const arch_register_req_t *outreq;
670 if (bitset_is_set(used_outs, o))
672 outreq = out_reg_reqs[o];
673 if (!can_match(outreq, inreq))
675 bitset_set(used_outs, i);
678 /* did we find any match? */
679 if (o < orig_out_arity)
682 /* we might need more space in the output arrays */
683 if (out_arity >= out_size) {
684 const arch_register_req_t **new_out_reg_reqs;
688 = OALLOCN(obst, const arch_register_req_t*, out_size);
689 memcpy(new_out_reg_reqs, out_reg_reqs,
690 out_arity * sizeof(new_out_reg_reqs[0]));
691 out_reg_reqs = new_out_reg_reqs;
694 /* add a new (dummy) output which occupies the register */
695 assert(inreq->type & arch_register_req_type_limited);
696 out_reg_reqs[out_arity] = inreq;
701 /* append none register requirement for the memory output */
702 if (out_arity + 1 >= out_size) {
703 const arch_register_req_t **new_out_reg_reqs;
705 out_size = out_arity + 1;
707 = OALLOCN(obst, const arch_register_req_t*, out_size);
708 memcpy(new_out_reg_reqs, out_reg_reqs,
709 out_arity * sizeof(new_out_reg_reqs[0]));
710 out_reg_reqs = new_out_reg_reqs;
713 /* add a new (dummy) output which occupies the register */
714 out_reg_reqs[out_arity] = arch_no_register_req;
717 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
718 get_ASM_text(node), register_map);
720 info = be_get_info(new_node);
721 for (o = 0; o < out_arity; ++o) {
722 info->out_infos[o].req = out_reg_reqs[o];
724 arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
726 SET_IA32_ORIG_NODE(new_node, node);
731 ir_node *ia32_gen_CopyB(ir_node *node)
733 ir_node *block = get_new_node(get_nodes_block(node));
734 ir_node *src = get_CopyB_src(node);
735 ir_node *new_src = get_new_node(src);
736 ir_node *dst = get_CopyB_dst(node);
737 ir_node *new_dst = get_new_node(dst);
738 ir_node *mem = get_CopyB_mem(node);
739 ir_node *new_mem = get_new_node(mem);
741 dbg_info *dbgi = get_irn_dbg_info(node);
742 int size = get_type_size_bytes(get_CopyB_type(node));
743 int throws_exception = ir_throws_exception(node);
746 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
747 /* then we need the size explicitly in ECX. */
748 if (size >= 32 * 4) {
749 rem = size & 0x3; /* size % 4 */
752 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
754 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
757 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
760 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
762 ir_set_throws_exception(res, throws_exception);
764 SET_IA32_ORIG_NODE(res, node);
769 ir_node *ia32_gen_Proj_tls(ir_node *node)
771 ir_node *block = get_new_node(get_nodes_block(node));
772 ir_node *res = new_bd_ia32_LdTls(NULL, block);
776 ir_node *ia32_gen_Unknown(ir_node *node)
778 ir_mode *mode = get_irn_mode(node);
779 ir_graph *irg = current_ir_graph;
780 dbg_info *dbgi = get_irn_dbg_info(node);
781 ir_node *block = get_irg_start_block(irg);
784 if (mode_is_float(mode)) {
785 if (ia32_cg_config.use_sse2) {
786 res = new_bd_ia32_xUnknown(dbgi, block);
788 res = new_bd_ia32_vfldz(dbgi, block);
790 } else if (ia32_mode_needs_gp_reg(mode)) {
791 res = new_bd_ia32_Unknown(dbgi, block);
793 panic("unsupported Unknown-Mode");
799 const arch_register_req_t *ia32_make_register_req(const constraint_t *constraint,
800 int n_outs, const arch_register_req_t **out_reqs, int pos)
802 struct obstack *obst = get_irg_obstack(current_ir_graph);
803 int same_as = constraint->same_as;
804 arch_register_req_t *req;
807 const arch_register_req_t *other_constr;
809 if (same_as >= n_outs)
810 panic("invalid output number in same_as constraint");
812 other_constr = out_reqs[same_as];
814 req = OALLOC(obst, arch_register_req_t);
815 *req = *other_constr;
816 req->type |= arch_register_req_type_should_be_same;
817 req->other_same = 1U << pos;
820 /* switch constraints. This is because in firm we have same_as
821 * constraints on the output constraints while in the gcc asm syntax
822 * they are specified on the input constraints */
823 out_reqs[same_as] = req;
827 /* pure memory ops */
828 if (constraint->cls == NULL) {
829 return arch_no_register_req;
832 if (constraint->allowed_registers != 0
833 && !constraint->all_registers_allowed) {
834 unsigned *limited_ptr;
836 req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
837 memset(req, 0, sizeof(req[0]));
838 limited_ptr = (unsigned*) (req+1);
840 req->type = arch_register_req_type_limited;
841 *limited_ptr = constraint->allowed_registers;
842 req->limited = limited_ptr;
844 req = OALLOCZ(obst, arch_register_req_t);
845 req->type = arch_register_req_type_normal;
847 req->cls = constraint->cls;
853 const arch_register_req_t *ia32_parse_clobber(const char *clobber)
855 struct obstack *obst = get_irg_obstack(current_ir_graph);
856 const arch_register_t *reg = ia32_get_clobber_register(clobber);
857 arch_register_req_t *req;
861 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
864 assert(reg->index < 32);
866 limited = OALLOC(obst, unsigned);
867 *limited = 1 << reg->index;
869 req = OALLOCZ(obst, arch_register_req_t);
870 req->type = arch_register_req_type_limited;
871 req->cls = arch_register_get_class(reg);
872 req->limited = limited;
879 int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
880 ir_node *const other)
882 if (get_nodes_block(other) != block)
885 if (is_Sync(other)) {
888 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
889 ir_node *const pred = get_Sync_pred(other, i);
891 if (get_nodes_block(pred) != block)
894 /* Do not block ourselves from getting eaten */
895 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
898 if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
906 /* Do not block ourselves from getting eaten */
907 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
910 if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
917 ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
920 ir_entity *symconst_ent = NULL;
922 ir_node *cnst = NULL;
923 ir_node *symconst = NULL;
926 mode = get_irn_mode(node);
927 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
931 if (is_Const(node)) {
934 } else if (is_SymConst_addr_ent(node)
935 && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
938 } else if (is_Add(node)) {
939 ir_node *left = get_Add_left(node);
940 ir_node *right = get_Add_right(node);
941 if (is_Const(left) && is_SymConst_addr_ent(right)) {
944 } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
953 ir_tarval *offset = get_Const_tarval(cnst);
954 if (!tarval_is_long(offset)) {
955 ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
959 val = get_tarval_long(offset);
960 if (!check_immediate_constraint(val, immediate_constraint_type))
963 if (symconst != NULL) {
964 if (immediate_constraint_type != 0) {
965 /* we need full 32bits for symconsts */
969 symconst_ent = get_SymConst_entity(symconst);
971 if (cnst == NULL && symconst == NULL)
974 new_node = ia32_create_Immediate(symconst_ent, 0, val);