2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
36 #include "ia32_architecture.h"
37 #include "ia32_common_transform.h"
38 #include "ia32_new_nodes.h"
40 #include "gen_ia32_new_nodes.h"
41 #include "gen_ia32_regalloc_if.h"
43 /** hold the current code generator during transformation */
44 ia32_code_gen_t *env_cg = NULL;
46 heights_t *heights = NULL;
48 static const arch_register_req_t no_register_req = {
49 arch_register_req_type_none,
51 NULL, /* limit bitset */
56 static int check_immediate_constraint(long val, char immediate_constraint_type)
58 switch (immediate_constraint_type) {
62 case 'I': return 0 <= val && val <= 31;
63 case 'J': return 0 <= val && val <= 63;
64 case 'K': return -128 <= val && val <= 127;
65 case 'L': return val == 0xff || val == 0xffff;
66 case 'M': return 0 <= val && val <= 3;
67 case 'N': return 0 <= val && val <= 255;
68 case 'O': return 0 <= val && val <= 127;
70 default: panic("Invalid immediate constraint found");
75 * creates a unique ident by adding a number to a tag
77 * @param tag the tag string, must contain a %d if a number
80 static ident *unique_id(const char *tag)
82 static unsigned id = 0;
85 snprintf(str, sizeof(str), tag, ++id);
86 return new_id_from_str(str);
90 * Get a primitive type for a mode.
92 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
94 pmap_entry *e = pmap_find(types, mode);
99 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
100 res = new_type_primitive(new_id_from_str(buf), mode);
101 set_type_alignment_bytes(res, 16);
102 pmap_insert(types, mode, res);
109 ir_entity *create_float_const_entity(ir_node *cnst)
111 ia32_isa_t *isa = env_cg->isa;
112 tarval *key = get_Const_tarval(cnst);
113 pmap_entry *e = pmap_find(isa->tv_ent, key);
119 ir_mode *mode = get_tarval_mode(tv);
122 if (! ia32_cg_config.use_sse2) {
123 /* try to reduce the mode to produce smaller sized entities */
124 if (mode != mode_F) {
125 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
127 tv = tarval_convert_to(tv, mode);
128 } else if (mode != mode_D) {
129 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
131 tv = tarval_convert_to(tv, mode);
137 if (mode == get_irn_mode(cnst)) {
138 /* mode was not changed */
139 tp = get_Const_type(cnst);
140 if (tp == firm_unknown_type)
141 tp = ia32_get_prim_type(isa->types, mode);
143 tp = ia32_get_prim_type(isa->types, mode);
145 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
147 set_entity_ld_ident(res, get_entity_ident(res));
148 set_entity_visibility(res, visibility_local);
149 set_entity_variability(res, variability_constant);
150 set_entity_allocation(res, allocation_static);
152 /* we create a new entity here: It's initialization must resist on the
154 rem = current_ir_graph;
155 current_ir_graph = get_const_code_irg();
156 set_atomic_ent_value(res, new_Const_type(tv, tp));
157 current_ir_graph = rem;
159 pmap_insert(isa->tv_ent, key, res);
167 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
169 ir_graph *irg = current_ir_graph;
170 ir_node *start_block = get_irg_start_block(irg);
171 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
172 symconst, symconst_sign, val);
173 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
178 const arch_register_t *ia32_get_clobber_register(const char *clobber)
180 const arch_register_t *reg = NULL;
183 const arch_register_class_t *cls;
185 /* TODO: construct a hashmap instead of doing linear search for clobber
187 for(c = 0; c < N_CLASSES; ++c) {
188 cls = & ia32_reg_classes[c];
189 for(r = 0; r < cls->n_regs; ++r) {
190 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
191 if(strcmp(temp_reg->name, clobber) == 0
192 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
205 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
206 ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
208 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
209 obstack_1grow(isa->name_obst, 0);
210 return obstack_finish(isa->name_obst);
214 int ia32_mode_needs_gp_reg(ir_mode *mode) {
215 if(mode == mode_fpcw)
217 if(get_mode_size_bits(mode) > 32)
219 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
222 static void parse_asm_constraints(constraint_t *constraint, const char *c,
225 asm_constraint_flags_t flags = 0;
226 char immediate_type = '\0';
227 unsigned limited = 0;
228 const arch_register_class_t *cls = NULL;
229 int memory_possible = 0;
230 int all_registers_allowed = 0;
234 memset(constraint, 0, sizeof(constraint[0]));
235 constraint->same_as = -1;
238 /* a memory constraint: no need to do anything in backend about it
239 * (the dependencies are already respected by the memory edge of
244 /* TODO: improve error messages with node and source info. (As users can
245 * easily hit these) */
254 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
255 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
259 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
260 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
267 while(*c != 0 && *c != ',')
272 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
273 cls = &ia32_reg_classes[CLASS_ia32_gp];
274 limited |= 1 << REG_EAX;
277 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
278 cls = &ia32_reg_classes[CLASS_ia32_gp];
279 limited |= 1 << REG_EBX;
282 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
283 cls = &ia32_reg_classes[CLASS_ia32_gp];
284 limited |= 1 << REG_ECX;
287 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
288 cls = &ia32_reg_classes[CLASS_ia32_gp];
289 limited |= 1 << REG_EDX;
292 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
293 cls = &ia32_reg_classes[CLASS_ia32_gp];
294 limited |= 1 << REG_EDI;
297 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
298 cls = &ia32_reg_classes[CLASS_ia32_gp];
299 limited |= 1 << REG_ESI;
303 /* q means lower part of the regs only, this makes no
304 * difference to Q for us (we only assign whole registers) */
305 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
306 cls = &ia32_reg_classes[CLASS_ia32_gp];
307 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
311 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
312 cls = &ia32_reg_classes[CLASS_ia32_gp];
313 limited |= 1 << REG_EAX | 1 << REG_EDX;
316 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
317 cls = &ia32_reg_classes[CLASS_ia32_gp];
318 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
319 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
326 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
327 panic("multiple register classes not supported");
328 cls = &ia32_reg_classes[CLASS_ia32_gp];
329 all_registers_allowed = 1;
335 /* TODO: mark values so the x87 simulator knows about t and u */
336 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
337 panic("multiple register classes not supported");
338 cls = &ia32_reg_classes[CLASS_ia32_vfp];
339 all_registers_allowed = 1;
344 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
345 panic("multiple register classes not supproted");
346 cls = &ia32_reg_classes[CLASS_ia32_xmm];
347 all_registers_allowed = 1;
357 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
358 panic("multiple register classes not supported");
359 if (immediate_type != '\0')
360 panic("multiple immediate types not supported");
361 cls = &ia32_reg_classes[CLASS_ia32_gp];
366 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
367 panic("multiple register classes not supported");
368 if (immediate_type != '\0')
369 panic("multiple immediate types not supported");
370 cls = &ia32_reg_classes[CLASS_ia32_gp];
371 immediate_type = 'i';
376 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
377 panic("multiple register classes not supported");
378 if (immediate_type != '\0')
379 panic("multiple immediate types not supported");
380 immediate_type = 'i';
381 cls = &ia32_reg_classes[CLASS_ia32_gp];
382 all_registers_allowed = 1;
397 panic("can only specify same constraint on input");
399 sscanf(c, "%d%n", &same_as, &p);
409 /* memory constraint no need to do anything in backend about it
410 * (the dependencies are already respected by the memory edge of
415 case 'E': /* no float consts yet */
416 case 'F': /* no float consts yet */
417 case 's': /* makes no sense on x86 */
418 case '<': /* no autodecrement on x86 */
419 case '>': /* no autoincrement on x86 */
420 case 'C': /* sse constant not supported yet */
421 case 'G': /* 80387 constant not supported yet */
422 case 'y': /* we don't support mmx registers yet */
423 case 'Z': /* not available in 32 bit mode */
424 case 'e': /* not available in 32 bit mode */
425 panic("unsupported asm constraint '%c' found in (%+F)",
426 *c, current_ir_graph);
429 panic("unknown asm constraint '%c' found in (%+F)", *c,
438 panic("same as and register constraint not supported");
439 if (immediate_type != '\0')
440 panic("same as and immediate constraint not supported");
443 if (cls == NULL && same_as < 0) {
444 if (!memory_possible)
445 panic("no constraint specified for assembler input");
448 constraint->same_as = same_as;
449 constraint->cls = cls;
450 constraint->allowed_registers = limited;
451 constraint->all_registers_allowed = all_registers_allowed;
452 constraint->memory_possible = memory_possible;
453 constraint->immediate_type = immediate_type;
456 ir_node *gen_ASM(ir_node *node)
458 ir_graph *irg = current_ir_graph;
459 ir_node *block = get_nodes_block(node);
460 ir_node *new_block = be_transform_node(block);
461 dbg_info *dbgi = get_irn_dbg_info(node);
467 int n_out_constraints;
469 const arch_register_req_t **out_reg_reqs;
470 const arch_register_req_t **in_reg_reqs;
471 ia32_asm_reg_t *register_map;
472 unsigned reg_map_size = 0;
473 struct obstack *obst;
474 const ir_asm_constraint *in_constraints;
475 const ir_asm_constraint *out_constraints;
477 int clobbers_flags = 0;
479 /* workaround for lots of buggy code out there as most people think volatile
480 * asm is enough for everything and forget the flags (linux kernel, etc.)
482 if (get_irn_pinned(node) == op_pin_state_pinned) {
486 arity = get_irn_arity(node);
487 in = alloca(arity * sizeof(in[0]));
488 memset(in, 0, arity * sizeof(in[0]));
490 clobbers = get_ASM_clobbers(node);
492 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
493 const char *c = get_id_str(clobbers[i]);
494 if (strcmp(c, "memory") == 0)
496 if (strcmp(c, "cc") == 0) {
502 n_out_constraints = get_ASM_n_output_constraints(node);
503 out_arity = n_out_constraints + n_clobbers;
505 in_constraints = get_ASM_input_constraints(node);
506 out_constraints = get_ASM_output_constraints(node);
508 /* determine size of register_map */
509 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
510 const ir_asm_constraint *constraint = &out_constraints[out_idx];
511 if (constraint->pos > reg_map_size)
512 reg_map_size = constraint->pos;
514 for(i = 0; i < arity; ++i) {
515 const ir_asm_constraint *constraint = &in_constraints[i];
516 if(constraint->pos > reg_map_size)
517 reg_map_size = constraint->pos;
521 obst = get_irg_obstack(irg);
522 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
523 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
525 /* construct output constraints */
526 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
528 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
529 const ir_asm_constraint *constraint = &out_constraints[out_idx];
530 const char *c = get_id_str(constraint->constraint);
531 unsigned pos = constraint->pos;
532 constraint_t parsed_constraint;
533 const arch_register_req_t *req;
535 parse_asm_constraints(&parsed_constraint, c, 1);
536 req = make_register_req(&parsed_constraint, n_out_constraints,
537 out_reg_reqs, out_idx);
538 out_reg_reqs[out_idx] = req;
540 register_map[pos].use_input = 0;
541 register_map[pos].valid = 1;
542 register_map[pos].memory = 0;
543 register_map[pos].inout_pos = out_idx;
544 register_map[pos].mode = constraint->mode;
547 /* inputs + input constraints */
548 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
549 for(i = 0; i < arity; ++i) {
550 ir_node *pred = get_irn_n(node, i);
551 const ir_asm_constraint *constraint = &in_constraints[i];
552 ident *constr_id = constraint->constraint;
553 const char *c = get_id_str(constr_id);
554 unsigned pos = constraint->pos;
555 int is_memory_op = 0;
556 ir_node *input = NULL;
557 constraint_t parsed_constraint;
558 const arch_register_req_t *req;
560 parse_asm_constraints(&parsed_constraint, c, 0);
561 req = make_register_req(&parsed_constraint, n_out_constraints,
563 in_reg_reqs[i] = req;
565 if (parsed_constraint.immediate_type != '\0') {
566 char imm_type = parsed_constraint.immediate_type;
567 input = try_create_Immediate(pred, imm_type);
571 ir_node *pred = get_irn_n(node, i);
572 input = be_transform_node(pred);
574 if (parsed_constraint.cls == NULL
575 && parsed_constraint.same_as < 0) {
577 } else if(parsed_constraint.memory_possible) {
578 /* TODO: match Load or Load/Store if memory possible is set */
583 register_map[pos].use_input = 1;
584 register_map[pos].valid = 1;
585 register_map[pos].memory = is_memory_op;
586 register_map[pos].inout_pos = i;
587 register_map[pos].mode = constraint->mode;
591 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
592 const char *c = get_id_str(clobbers[i]);
593 const arch_register_req_t *req;
595 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
598 req = parse_clobber(c);
599 out_reg_reqs[out_idx] = req;
603 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
604 get_ASM_text(node), register_map);
606 set_ia32_out_req_all(new_node, out_reg_reqs);
607 set_ia32_in_req_all(new_node, in_reg_reqs);
609 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
614 ir_node *gen_Unknown(ir_node *node)
616 ir_mode *mode = get_irn_mode(node);
618 if (mode_is_float(mode)) {
619 if (ia32_cg_config.use_sse2) {
620 return ia32_new_Unknown_xmm(env_cg);
622 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
623 ir_graph *irg = current_ir_graph;
624 dbg_info *dbgi = get_irn_dbg_info(node);
625 ir_node *block = get_irg_start_block(irg);
626 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
628 /* Const Nodes before the initial IncSP are a bad idea, because
629 * they could be spilled and we have no SP ready at that point yet.
630 * So add a dependency to the initial frame pointer calculation to
631 * avoid that situation.
633 add_irn_dep(ret, get_irg_frame(irg));
636 } else if (ia32_mode_needs_gp_reg(mode)) {
637 return ia32_new_Unknown_gp(env_cg);
639 panic("unsupported Unknown-Mode");
644 const arch_register_req_t *make_register_req(const constraint_t *constraint,
645 int n_outs, const arch_register_req_t **out_reqs, int pos)
647 struct obstack *obst = get_irg_obstack(current_ir_graph);
648 int same_as = constraint->same_as;
649 arch_register_req_t *req;
652 const arch_register_req_t *other_constr;
654 if (same_as >= n_outs)
655 panic("invalid output number in same_as constraint");
657 other_constr = out_reqs[same_as];
659 req = obstack_alloc(obst, sizeof(req[0]));
660 req->cls = other_constr->cls;
661 req->type = arch_register_req_type_should_be_same;
663 req->other_same = 1U << pos;
664 req->other_different = 0;
666 /* switch constraints. This is because in firm we have same_as
667 * constraints on the output constraints while in the gcc asm syntax
668 * they are specified on the input constraints */
669 out_reqs[same_as] = req;
673 /* pure memory ops */
674 if (constraint->cls == NULL) {
675 return &no_register_req;
678 if (constraint->allowed_registers != 0
679 && !constraint->all_registers_allowed) {
680 unsigned *limited_ptr;
682 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
683 memset(req, 0, sizeof(req[0]));
684 limited_ptr = (unsigned*) (req+1);
686 req->type = arch_register_req_type_limited;
687 *limited_ptr = constraint->allowed_registers;
688 req->limited = limited_ptr;
690 req = obstack_alloc(obst, sizeof(req[0]));
691 memset(req, 0, sizeof(req[0]));
692 req->type = arch_register_req_type_normal;
694 req->cls = constraint->cls;
699 const arch_register_req_t *parse_clobber(const char *clobber)
701 struct obstack *obst = get_irg_obstack(current_ir_graph);
702 const arch_register_t *reg = ia32_get_clobber_register(clobber);
703 arch_register_req_t *req;
707 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
710 assert(reg->index < 32);
712 limited = obstack_alloc(obst, sizeof(limited[0]));
713 *limited = 1 << reg->index;
715 req = obstack_alloc(obst, sizeof(req[0]));
716 memset(req, 0, sizeof(req[0]));
717 req->type = arch_register_req_type_limited;
718 req->cls = arch_register_get_class(reg);
719 req->limited = limited;
724 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
727 tarval *offset = NULL;
730 ir_entity *symconst_ent = NULL;
731 int symconst_sign = 0;
733 ir_node *cnst = NULL;
734 ir_node *symconst = NULL;
737 mode = get_irn_mode(node);
738 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
744 node = get_Minus_op(node);
751 } else if(is_SymConst(node)) {
754 symconst_sign = minus;
755 } else if(is_Add(node)) {
756 ir_node *left = get_Add_left(node);
757 ir_node *right = get_Add_right(node);
758 if(is_Const(left) && is_SymConst(right)) {
761 symconst_sign = minus;
763 } else if(is_SymConst(left) && is_Const(right)) {
766 symconst_sign = minus;
769 } else if(is_Sub(node)) {
770 ir_node *left = get_Sub_left(node);
771 ir_node *right = get_Sub_right(node);
772 if(is_Const(left) && is_SymConst(right)) {
775 symconst_sign = !minus;
777 } else if(is_SymConst(left) && is_Const(right)) {
780 symconst_sign = minus;
781 offset_sign = !minus;
788 offset = get_Const_tarval(cnst);
789 if(tarval_is_long(offset)) {
790 val = get_tarval_long(offset);
792 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
797 if(!check_immediate_constraint(val, immediate_constraint_type))
800 if(symconst != NULL) {
801 if(immediate_constraint_type != 0) {
802 /* we need full 32bits for symconsts */
806 /* unfortunately the assembler/linker doesn't support -symconst */
810 if(get_SymConst_kind(symconst) != symconst_addr_ent)
812 symconst_ent = get_SymConst_entity(symconst);
814 if(cnst == NULL && symconst == NULL)
817 if(offset_sign && offset != NULL) {
818 offset = tarval_neg(offset);
821 new_node = create_Immediate(symconst_ent, symconst_sign, val);