2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
37 #include "../betranshlp.h"
38 #include "../beirg_t.h"
40 #include "ia32_architecture.h"
41 #include "ia32_common_transform.h"
42 #include "ia32_new_nodes.h"
44 #include "gen_ia32_new_nodes.h"
45 #include "gen_ia32_regalloc_if.h"
47 /** hold the current code generator during transformation */
48 ia32_code_gen_t *env_cg = NULL;
50 heights_t *heights = NULL;
52 static const arch_register_req_t no_register_req = {
53 arch_register_req_type_none,
55 NULL, /* limit bitset */
60 static int check_immediate_constraint(long val, char immediate_constraint_type)
62 switch (immediate_constraint_type) {
66 case 'I': return 0 <= val && val <= 31;
67 case 'J': return 0 <= val && val <= 63;
68 case 'K': return -128 <= val && val <= 127;
69 case 'L': return val == 0xff || val == 0xffff;
70 case 'M': return 0 <= val && val <= 3;
71 case 'N': return 0 <= val && val <= 255;
72 case 'O': return 0 <= val && val <= 127;
74 default: panic("Invalid immediate constraint found");
79 * creates a unique ident by adding a number to a tag
81 * @param tag the tag string, must contain a %d if a number
84 static ident *unique_id(const char *tag)
86 static unsigned id = 0;
89 snprintf(str, sizeof(str), tag, ++id);
90 return new_id_from_str(str);
94 * Get a primitive type for a mode.
96 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
98 pmap_entry *e = pmap_find(types, mode);
103 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
104 res = new_type_primitive(new_id_from_str(buf), mode);
105 set_type_alignment_bytes(res, 16);
106 pmap_insert(types, mode, res);
113 ir_entity *create_float_const_entity(ir_node *cnst)
115 ia32_isa_t *isa = env_cg->isa;
116 tarval *key = get_Const_tarval(cnst);
117 pmap_entry *e = pmap_find(isa->tv_ent, key);
123 ir_mode *mode = get_tarval_mode(tv);
126 if (! ia32_cg_config.use_sse2) {
127 /* try to reduce the mode to produce smaller sized entities */
128 if (mode != mode_F) {
129 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
131 tv = tarval_convert_to(tv, mode);
132 } else if (mode != mode_D) {
133 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
135 tv = tarval_convert_to(tv, mode);
141 if (mode == get_irn_mode(cnst)) {
142 /* mode was not changed */
143 tp = get_Const_type(cnst);
144 if (tp == firm_unknown_type)
145 tp = ia32_get_prim_type(isa->types, mode);
147 tp = ia32_get_prim_type(isa->types, mode);
149 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
151 set_entity_ld_ident(res, get_entity_ident(res));
152 set_entity_visibility(res, visibility_local);
153 set_entity_variability(res, variability_constant);
154 set_entity_allocation(res, allocation_static);
156 /* we create a new entity here: It's initialization must resist on the
158 rem = current_ir_graph;
159 current_ir_graph = get_const_code_irg();
160 set_atomic_ent_value(res, new_Const_type(tv, tp));
161 current_ir_graph = rem;
163 pmap_insert(isa->tv_ent, key, res);
171 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
173 ir_graph *irg = current_ir_graph;
174 ir_node *start_block = get_irg_start_block(irg);
175 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
176 symconst, symconst_sign, val);
177 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
182 const arch_register_t *ia32_get_clobber_register(const char *clobber)
184 const arch_register_t *reg = NULL;
187 const arch_register_class_t *cls;
189 /* TODO: construct a hashmap instead of doing linear search for clobber
191 for(c = 0; c < N_CLASSES; ++c) {
192 cls = & ia32_reg_classes[c];
193 for(r = 0; r < cls->n_regs; ++r) {
194 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
195 if(strcmp(temp_reg->name, clobber) == 0
196 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
209 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
210 ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
212 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
213 obstack_1grow(isa->name_obst, 0);
214 return obstack_finish(isa->name_obst);
218 int ia32_mode_needs_gp_reg(ir_mode *mode) {
219 if(mode == mode_fpcw)
221 if(get_mode_size_bits(mode) > 32)
223 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
226 static void parse_asm_constraints(constraint_t *constraint, const char *c,
229 asm_constraint_flags_t flags = 0;
230 char immediate_type = '\0';
231 unsigned limited = 0;
232 const arch_register_class_t *cls = NULL;
233 int memory_possible = 0;
234 int all_registers_allowed = 0;
238 memset(constraint, 0, sizeof(constraint[0]));
239 constraint->same_as = -1;
242 /* a memory constraint: no need to do anything in backend about it
243 * (the dependencies are already respected by the memory edge of
248 /* TODO: improve error messages with node and source info. (As users can
249 * easily hit these) */
258 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
259 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
263 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
264 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
271 while(*c != 0 && *c != ',')
276 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
277 cls = &ia32_reg_classes[CLASS_ia32_gp];
278 limited |= 1 << REG_EAX;
281 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
282 cls = &ia32_reg_classes[CLASS_ia32_gp];
283 limited |= 1 << REG_EBX;
286 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
287 cls = &ia32_reg_classes[CLASS_ia32_gp];
288 limited |= 1 << REG_ECX;
291 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
292 cls = &ia32_reg_classes[CLASS_ia32_gp];
293 limited |= 1 << REG_EDX;
296 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
297 cls = &ia32_reg_classes[CLASS_ia32_gp];
298 limited |= 1 << REG_EDI;
301 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
302 cls = &ia32_reg_classes[CLASS_ia32_gp];
303 limited |= 1 << REG_ESI;
307 /* q means lower part of the regs only, this makes no
308 * difference to Q for us (we only assign whole registers) */
309 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
310 cls = &ia32_reg_classes[CLASS_ia32_gp];
311 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
315 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
316 cls = &ia32_reg_classes[CLASS_ia32_gp];
317 limited |= 1 << REG_EAX | 1 << REG_EDX;
320 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
321 cls = &ia32_reg_classes[CLASS_ia32_gp];
322 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
323 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
330 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
331 panic("multiple register classes not supported");
332 cls = &ia32_reg_classes[CLASS_ia32_gp];
333 all_registers_allowed = 1;
339 /* TODO: mark values so the x87 simulator knows about t and u */
340 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
341 panic("multiple register classes not supported");
342 cls = &ia32_reg_classes[CLASS_ia32_vfp];
343 all_registers_allowed = 1;
348 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
349 panic("multiple register classes not supproted");
350 cls = &ia32_reg_classes[CLASS_ia32_xmm];
351 all_registers_allowed = 1;
361 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
362 panic("multiple register classes not supported");
363 if (immediate_type != '\0')
364 panic("multiple immediate types not supported");
365 cls = &ia32_reg_classes[CLASS_ia32_gp];
370 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
371 panic("multiple register classes not supported");
372 if (immediate_type != '\0')
373 panic("multiple immediate types not supported");
374 cls = &ia32_reg_classes[CLASS_ia32_gp];
375 immediate_type = 'i';
380 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
381 panic("multiple register classes not supported");
382 if (immediate_type != '\0')
383 panic("multiple immediate types not supported");
384 immediate_type = 'i';
385 cls = &ia32_reg_classes[CLASS_ia32_gp];
386 all_registers_allowed = 1;
401 panic("can only specify same constraint on input");
403 sscanf(c, "%d%n", &same_as, &p);
413 /* memory constraint no need to do anything in backend about it
414 * (the dependencies are already respected by the memory edge of
419 case 'E': /* no float consts yet */
420 case 'F': /* no float consts yet */
421 case 's': /* makes no sense on x86 */
422 case '<': /* no autodecrement on x86 */
423 case '>': /* no autoincrement on x86 */
424 case 'C': /* sse constant not supported yet */
425 case 'G': /* 80387 constant not supported yet */
426 case 'y': /* we don't support mmx registers yet */
427 case 'Z': /* not available in 32 bit mode */
428 case 'e': /* not available in 32 bit mode */
429 panic("unsupported asm constraint '%c' found in (%+F)",
430 *c, current_ir_graph);
433 panic("unknown asm constraint '%c' found in (%+F)", *c,
442 panic("same as and register constraint not supported");
443 if (immediate_type != '\0')
444 panic("same as and immediate constraint not supported");
447 if (cls == NULL && same_as < 0) {
448 if (!memory_possible)
449 panic("no constraint specified for assembler input");
452 constraint->same_as = same_as;
453 constraint->cls = cls;
454 constraint->allowed_registers = limited;
455 constraint->all_registers_allowed = all_registers_allowed;
456 constraint->memory_possible = memory_possible;
457 constraint->immediate_type = immediate_type;
460 ir_node *gen_ASM(ir_node *node)
462 ir_graph *irg = current_ir_graph;
463 ir_node *block = NULL;
464 ir_node *new_block = NULL;
465 dbg_info *dbgi = get_irn_dbg_info(node);
471 int n_out_constraints;
473 const arch_register_req_t **out_reg_reqs;
474 const arch_register_req_t **in_reg_reqs;
475 ia32_asm_reg_t *register_map;
476 unsigned reg_map_size = 0;
477 struct obstack *obst;
478 const ir_asm_constraint *in_constraints;
479 const ir_asm_constraint *out_constraints;
481 int clobbers_flags = 0;
482 unsigned clobber_bits[N_CLASSES];
484 memset(&clobber_bits, 0, sizeof(clobber_bits));
486 switch (be_transformer) {
487 case TRANSFORMER_DEFAULT:
488 block = get_nodes_block(node);
489 new_block = be_transform_node(block);
493 case TRANSFORMER_PBQP:
494 new_block = get_nodes_block(node);
499 panic("invalid transformer");
502 /* workaround for lots of buggy code out there as most people think volatile
503 * asm is enough for everything and forget the flags (linux kernel, etc.)
505 if (get_irn_pinned(node) == op_pin_state_pinned) {
509 arity = get_irn_arity(node);
510 in = alloca(arity * sizeof(in[0]));
511 memset(in, 0, arity * sizeof(in[0]));
513 clobbers = get_ASM_clobbers(node);
515 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
516 const arch_register_req_t *req;
517 const char *c = get_id_str(clobbers[i]);
519 if (strcmp(c, "memory") == 0)
521 if (strcmp(c, "cc") == 0) {
526 req = parse_clobber(c);
527 clobber_bits[req->cls->index] |= *req->limited;
531 n_out_constraints = get_ASM_n_output_constraints(node);
532 out_arity = n_out_constraints + n_clobbers;
534 in_constraints = get_ASM_input_constraints(node);
535 out_constraints = get_ASM_output_constraints(node);
537 /* determine size of register_map */
538 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
539 const ir_asm_constraint *constraint = &out_constraints[out_idx];
540 if (constraint->pos > reg_map_size)
541 reg_map_size = constraint->pos;
543 for (i = 0; i < arity; ++i) {
544 const ir_asm_constraint *constraint = &in_constraints[i];
545 if(constraint->pos > reg_map_size)
546 reg_map_size = constraint->pos;
550 obst = get_irg_obstack(irg);
551 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
552 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
554 /* construct output constraints */
555 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
557 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
558 const ir_asm_constraint *constraint = &out_constraints[out_idx];
559 const char *c = get_id_str(constraint->constraint);
560 unsigned pos = constraint->pos;
561 constraint_t parsed_constraint;
562 const arch_register_req_t *req;
564 parse_asm_constraints(&parsed_constraint, c, 1);
565 req = make_register_req(&parsed_constraint, n_out_constraints,
566 out_reg_reqs, out_idx);
567 out_reg_reqs[out_idx] = req;
569 register_map[pos].use_input = 0;
570 register_map[pos].valid = 1;
571 register_map[pos].memory = 0;
572 register_map[pos].inout_pos = out_idx;
573 register_map[pos].mode = constraint->mode;
576 /* inputs + input constraints */
577 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
578 for (i = 0; i < arity; ++i) {
579 ir_node *pred = get_irn_n(node, i);
580 const ir_asm_constraint *constraint = &in_constraints[i];
581 ident *constr_id = constraint->constraint;
582 const char *c = get_id_str(constr_id);
583 unsigned pos = constraint->pos;
584 int is_memory_op = 0;
585 ir_node *input = NULL;
586 unsigned r_clobber_bits;
587 constraint_t parsed_constraint;
588 const arch_register_req_t *req;
590 parse_asm_constraints(&parsed_constraint, c, 0);
591 if (parsed_constraint.cls != NULL) {
592 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
593 if (r_clobber_bits != 0) {
594 if (parsed_constraint.all_registers_allowed) {
595 parsed_constraint.all_registers_allowed = 0;
596 be_abi_set_non_ignore_regs(env_cg->birg->abi,
597 parsed_constraint.cls,
598 &parsed_constraint.allowed_registers);
600 parsed_constraint.allowed_registers &= ~r_clobber_bits;
604 req = make_register_req(&parsed_constraint, n_out_constraints,
606 in_reg_reqs[i] = req;
608 if (parsed_constraint.immediate_type != '\0') {
609 char imm_type = parsed_constraint.immediate_type;
610 input = try_create_Immediate(pred, imm_type);
614 ir_node *pred = NULL;
615 switch (be_transformer) {
616 case TRANSFORMER_DEFAULT:
617 pred = get_irn_n(node, i);
618 input = be_transform_node(pred);
622 case TRANSFORMER_PBQP:
623 input = get_irn_n(node, i);
627 default: panic("invalid transformer");
630 if (parsed_constraint.cls == NULL
631 && parsed_constraint.same_as < 0) {
633 } else if(parsed_constraint.memory_possible) {
634 /* TODO: match Load or Load/Store if memory possible is set */
639 register_map[pos].use_input = 1;
640 register_map[pos].valid = 1;
641 register_map[pos].memory = is_memory_op;
642 register_map[pos].inout_pos = i;
643 register_map[pos].mode = constraint->mode;
647 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
648 const char *c = get_id_str(clobbers[i]);
649 const arch_register_req_t *req;
651 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
654 req = parse_clobber(c);
655 out_reg_reqs[out_idx] = req;
659 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
660 get_ASM_text(node), register_map);
662 set_ia32_out_req_all(new_node, out_reg_reqs);
663 set_ia32_in_req_all(new_node, in_reg_reqs);
665 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
670 ir_node *gen_CopyB(ir_node *node) {
671 ir_node *block = NULL;
673 ir_node *new_src = NULL;
675 ir_node *new_dst = NULL;
677 ir_node *new_mem = NULL;
679 ir_graph *irg = current_ir_graph;
680 dbg_info *dbgi = get_irn_dbg_info(node);
681 int size = get_type_size_bytes(get_CopyB_type(node));
684 switch (be_transformer) {
685 case TRANSFORMER_DEFAULT:
686 block = be_transform_node(get_nodes_block(node));
687 src = get_CopyB_src(node);
688 new_src = be_transform_node(src);
689 dst = get_CopyB_dst(node);
690 new_dst = be_transform_node(dst);
691 mem = get_CopyB_mem(node);
692 new_mem = be_transform_node(mem);
696 case TRANSFORMER_PBQP:
697 block = get_nodes_block(node);
698 new_src = get_CopyB_src(node);
699 new_dst = get_CopyB_dst(node);
700 new_mem = get_CopyB_mem(node);
704 default: panic("invalid transformer");
707 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
708 /* then we need the size explicitly in ECX. */
709 if (size >= 32 * 4) {
710 rem = size & 0x3; /* size % 4 */
713 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
714 add_irn_dep(res, get_irg_frame(irg));
716 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
719 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
722 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
725 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
730 ir_node *gen_Unknown(ir_node *node)
732 ir_mode *mode = get_irn_mode(node);
734 if (mode_is_float(mode)) {
735 if (ia32_cg_config.use_sse2) {
736 return ia32_new_Unknown_xmm(env_cg);
738 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
739 ir_graph *irg = current_ir_graph;
740 dbg_info *dbgi = get_irn_dbg_info(node);
741 ir_node *block = get_irg_start_block(irg);
742 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
744 /* Const Nodes before the initial IncSP are a bad idea, because
745 * they could be spilled and we have no SP ready at that point yet.
746 * So add a dependency to the initial frame pointer calculation to
747 * avoid that situation.
749 add_irn_dep(ret, get_irg_frame(irg));
752 } else if (ia32_mode_needs_gp_reg(mode)) {
753 return ia32_new_Unknown_gp(env_cg);
755 panic("unsupported Unknown-Mode");
760 const arch_register_req_t *make_register_req(const constraint_t *constraint,
761 int n_outs, const arch_register_req_t **out_reqs, int pos)
763 struct obstack *obst = get_irg_obstack(current_ir_graph);
764 int same_as = constraint->same_as;
765 arch_register_req_t *req;
768 const arch_register_req_t *other_constr;
770 if (same_as >= n_outs)
771 panic("invalid output number in same_as constraint");
773 other_constr = out_reqs[same_as];
775 req = obstack_alloc(obst, sizeof(req[0]));
776 req->cls = other_constr->cls;
777 req->type = arch_register_req_type_should_be_same;
779 req->other_same = 1U << pos;
780 req->other_different = 0;
782 /* switch constraints. This is because in firm we have same_as
783 * constraints on the output constraints while in the gcc asm syntax
784 * they are specified on the input constraints */
785 out_reqs[same_as] = req;
789 /* pure memory ops */
790 if (constraint->cls == NULL) {
791 return &no_register_req;
794 if (constraint->allowed_registers != 0
795 && !constraint->all_registers_allowed) {
796 unsigned *limited_ptr;
798 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
799 memset(req, 0, sizeof(req[0]));
800 limited_ptr = (unsigned*) (req+1);
802 req->type = arch_register_req_type_limited;
803 *limited_ptr = constraint->allowed_registers;
804 req->limited = limited_ptr;
806 req = obstack_alloc(obst, sizeof(req[0]));
807 memset(req, 0, sizeof(req[0]));
808 req->type = arch_register_req_type_normal;
810 req->cls = constraint->cls;
815 const arch_register_req_t *parse_clobber(const char *clobber)
817 struct obstack *obst = get_irg_obstack(current_ir_graph);
818 const arch_register_t *reg = ia32_get_clobber_register(clobber);
819 arch_register_req_t *req;
823 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
826 assert(reg->index < 32);
828 limited = obstack_alloc(obst, sizeof(limited[0]));
829 *limited = 1 << reg->index;
831 req = obstack_alloc(obst, sizeof(req[0]));
832 memset(req, 0, sizeof(req[0]));
833 req->type = arch_register_req_type_limited;
834 req->cls = arch_register_get_class(reg);
835 req->limited = limited;
840 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
843 tarval *offset = NULL;
846 ir_entity *symconst_ent = NULL;
847 int symconst_sign = 0;
849 ir_node *cnst = NULL;
850 ir_node *symconst = NULL;
853 mode = get_irn_mode(node);
854 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
860 node = get_Minus_op(node);
867 } else if(is_SymConst(node)) {
870 symconst_sign = minus;
871 } else if(is_Add(node)) {
872 ir_node *left = get_Add_left(node);
873 ir_node *right = get_Add_right(node);
874 if(is_Const(left) && is_SymConst(right)) {
877 symconst_sign = minus;
879 } else if(is_SymConst(left) && is_Const(right)) {
882 symconst_sign = minus;
885 } else if(is_Sub(node)) {
886 ir_node *left = get_Sub_left(node);
887 ir_node *right = get_Sub_right(node);
888 if(is_Const(left) && is_SymConst(right)) {
891 symconst_sign = !minus;
893 } else if(is_SymConst(left) && is_Const(right)) {
896 symconst_sign = minus;
897 offset_sign = !minus;
904 offset = get_Const_tarval(cnst);
905 if(tarval_is_long(offset)) {
906 val = get_tarval_long(offset);
908 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
913 if(!check_immediate_constraint(val, immediate_constraint_type))
916 if(symconst != NULL) {
917 if(immediate_constraint_type != 0) {
918 /* we need full 32bits for symconsts */
922 /* unfortunately the assembler/linker doesn't support -symconst */
926 if(get_SymConst_kind(symconst) != symconst_addr_ent)
928 symconst_ent = get_SymConst_entity(symconst);
930 if(cnst == NULL && symconst == NULL)
933 if(offset_sign && offset != NULL) {
934 offset = tarval_neg(offset);
937 new_node = create_Immediate(symconst_ent, symconst_sign, val);