2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
37 #include "../betranshlp.h"
38 #include "../beirg_t.h"
40 #include "ia32_architecture.h"
41 #include "ia32_common_transform.h"
42 #include "ia32_new_nodes.h"
44 #include "gen_ia32_new_nodes.h"
45 #include "gen_ia32_regalloc_if.h"
47 /** hold the current code generator during transformation */
48 ia32_code_gen_t *env_cg = NULL;
50 heights_t *heights = NULL;
52 static const arch_register_req_t no_register_req = {
53 arch_register_req_type_none,
55 NULL, /* limit bitset */
60 static int check_immediate_constraint(long val, char immediate_constraint_type)
62 switch (immediate_constraint_type) {
66 case 'I': return 0 <= val && val <= 31;
67 case 'J': return 0 <= val && val <= 63;
68 case 'K': return -128 <= val && val <= 127;
69 case 'L': return val == 0xff || val == 0xffff;
70 case 'M': return 0 <= val && val <= 3;
71 case 'N': return 0 <= val && val <= 255;
72 case 'O': return 0 <= val && val <= 127;
74 default: panic("Invalid immediate constraint found");
79 * creates a unique ident by adding a number to a tag
81 * @param tag the tag string, must contain a %d if a number
84 static ident *unique_id(const char *tag)
86 static unsigned id = 0;
89 snprintf(str, sizeof(str), tag, ++id);
90 return new_id_from_str(str);
94 * Get a primitive type for a mode.
96 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
98 pmap_entry *e = pmap_find(types, mode);
103 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
104 res = new_type_primitive(new_id_from_str(buf), mode);
105 set_type_alignment_bytes(res, 16);
106 pmap_insert(types, mode, res);
113 ir_entity *create_float_const_entity(ir_node *cnst)
115 ia32_isa_t *isa = env_cg->isa;
116 tarval *key = get_Const_tarval(cnst);
117 pmap_entry *e = pmap_find(isa->tv_ent, key);
123 ir_mode *mode = get_tarval_mode(tv);
126 if (! ia32_cg_config.use_sse2) {
127 /* try to reduce the mode to produce smaller sized entities */
128 if (mode != mode_F) {
129 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
131 tv = tarval_convert_to(tv, mode);
132 } else if (mode != mode_D) {
133 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
135 tv = tarval_convert_to(tv, mode);
141 if (mode == get_irn_mode(cnst)) {
142 /* mode was not changed */
143 tp = get_Const_type(cnst);
144 if (tp == firm_unknown_type)
145 tp = ia32_get_prim_type(isa->types, mode);
147 tp = ia32_get_prim_type(isa->types, mode);
149 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
151 set_entity_ld_ident(res, get_entity_ident(res));
152 set_entity_visibility(res, visibility_local);
153 set_entity_variability(res, variability_constant);
154 set_entity_allocation(res, allocation_static);
156 /* we create a new entity here: It's initialization must resist on the
158 rem = current_ir_graph;
159 current_ir_graph = get_const_code_irg();
160 set_atomic_ent_value(res, new_Const_type(tv, tp));
161 current_ir_graph = rem;
163 pmap_insert(isa->tv_ent, key, res);
171 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
173 ir_graph *irg = current_ir_graph;
174 ir_node *start_block = get_irg_start_block(irg);
175 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
176 symconst, symconst_sign, val);
177 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
182 const arch_register_t *ia32_get_clobber_register(const char *clobber)
184 const arch_register_t *reg = NULL;
187 const arch_register_class_t *cls;
189 /* TODO: construct a hashmap instead of doing linear search for clobber
191 for(c = 0; c < N_CLASSES; ++c) {
192 cls = & ia32_reg_classes[c];
193 for(r = 0; r < cls->n_regs; ++r) {
194 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
195 if(strcmp(temp_reg->name, clobber) == 0
196 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
209 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
210 ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
212 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
213 obstack_1grow(isa->name_obst, 0);
214 return obstack_finish(isa->name_obst);
218 int ia32_mode_needs_gp_reg(ir_mode *mode) {
219 if(mode == mode_fpcw)
221 if(get_mode_size_bits(mode) > 32)
223 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
226 static void parse_asm_constraints(constraint_t *constraint, const char *c,
229 char immediate_type = '\0';
230 unsigned limited = 0;
231 const arch_register_class_t *cls = NULL;
232 int memory_possible = 0;
233 int all_registers_allowed = 0;
237 memset(constraint, 0, sizeof(constraint[0]));
238 constraint->same_as = -1;
241 /* a memory constraint: no need to do anything in backend about it
242 * (the dependencies are already respected by the memory edge of
247 /* TODO: improve error messages with node and source info. (As users can
248 * easily hit these) */
256 /* Skip out/in-out marker */
264 while(*c != 0 && *c != ',')
269 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
270 cls = &ia32_reg_classes[CLASS_ia32_gp];
271 limited |= 1 << REG_EAX;
274 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
275 cls = &ia32_reg_classes[CLASS_ia32_gp];
276 limited |= 1 << REG_EBX;
279 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
280 cls = &ia32_reg_classes[CLASS_ia32_gp];
281 limited |= 1 << REG_ECX;
284 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
285 cls = &ia32_reg_classes[CLASS_ia32_gp];
286 limited |= 1 << REG_EDX;
289 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
290 cls = &ia32_reg_classes[CLASS_ia32_gp];
291 limited |= 1 << REG_EDI;
294 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
295 cls = &ia32_reg_classes[CLASS_ia32_gp];
296 limited |= 1 << REG_ESI;
300 /* q means lower part of the regs only, this makes no
301 * difference to Q for us (we only assign whole registers) */
302 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
303 cls = &ia32_reg_classes[CLASS_ia32_gp];
304 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
308 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
309 cls = &ia32_reg_classes[CLASS_ia32_gp];
310 limited |= 1 << REG_EAX | 1 << REG_EDX;
313 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
314 cls = &ia32_reg_classes[CLASS_ia32_gp];
315 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
316 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
323 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
324 panic("multiple register classes not supported");
325 cls = &ia32_reg_classes[CLASS_ia32_gp];
326 all_registers_allowed = 1;
332 /* TODO: mark values so the x87 simulator knows about t and u */
333 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
334 panic("multiple register classes not supported");
335 cls = &ia32_reg_classes[CLASS_ia32_vfp];
336 all_registers_allowed = 1;
341 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
342 panic("multiple register classes not supproted");
343 cls = &ia32_reg_classes[CLASS_ia32_xmm];
344 all_registers_allowed = 1;
354 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
355 panic("multiple register classes not supported");
356 if (immediate_type != '\0')
357 panic("multiple immediate types not supported");
358 cls = &ia32_reg_classes[CLASS_ia32_gp];
363 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
364 panic("multiple register classes not supported");
365 if (immediate_type != '\0')
366 panic("multiple immediate types not supported");
367 cls = &ia32_reg_classes[CLASS_ia32_gp];
368 immediate_type = 'i';
373 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
374 panic("multiple register classes not supported");
375 if (immediate_type != '\0')
376 panic("multiple immediate types not supported");
377 immediate_type = 'i';
378 cls = &ia32_reg_classes[CLASS_ia32_gp];
379 all_registers_allowed = 1;
394 panic("can only specify same constraint on input");
396 sscanf(c, "%d%n", &same_as, &p);
406 /* memory constraint no need to do anything in backend about it
407 * (the dependencies are already respected by the memory edge of
412 case 'E': /* no float consts yet */
413 case 'F': /* no float consts yet */
414 case 's': /* makes no sense on x86 */
415 case '<': /* no autodecrement on x86 */
416 case '>': /* no autoincrement on x86 */
417 case 'C': /* sse constant not supported yet */
418 case 'G': /* 80387 constant not supported yet */
419 case 'y': /* we don't support mmx registers yet */
420 case 'Z': /* not available in 32 bit mode */
421 case 'e': /* not available in 32 bit mode */
422 panic("unsupported asm constraint '%c' found in (%+F)",
423 *c, current_ir_graph);
426 panic("unknown asm constraint '%c' found in (%+F)", *c,
435 panic("same as and register constraint not supported");
436 if (immediate_type != '\0')
437 panic("same as and immediate constraint not supported");
440 if (cls == NULL && same_as < 0) {
441 if (!memory_possible)
442 panic("no constraint specified for assembler input");
445 constraint->same_as = same_as;
446 constraint->cls = cls;
447 constraint->allowed_registers = limited;
448 constraint->all_registers_allowed = all_registers_allowed;
449 constraint->memory_possible = memory_possible;
450 constraint->immediate_type = immediate_type;
453 ir_node *gen_ASM(ir_node *node)
455 ir_graph *irg = current_ir_graph;
456 ir_node *block = NULL;
457 ir_node *new_block = NULL;
458 dbg_info *dbgi = get_irn_dbg_info(node);
464 int n_out_constraints;
466 const arch_register_req_t **out_reg_reqs;
467 const arch_register_req_t **in_reg_reqs;
468 ia32_asm_reg_t *register_map;
469 unsigned reg_map_size = 0;
470 struct obstack *obst;
471 const ir_asm_constraint *in_constraints;
472 const ir_asm_constraint *out_constraints;
474 int clobbers_flags = 0;
475 unsigned clobber_bits[N_CLASSES];
477 memset(&clobber_bits, 0, sizeof(clobber_bits));
479 switch (be_transformer) {
480 case TRANSFORMER_DEFAULT:
481 block = get_nodes_block(node);
482 new_block = be_transform_node(block);
486 case TRANSFORMER_PBQP:
487 new_block = get_nodes_block(node);
492 panic("invalid transformer");
495 /* workaround for lots of buggy code out there as most people think volatile
496 * asm is enough for everything and forget the flags (linux kernel, etc.)
498 if (get_irn_pinned(node) == op_pin_state_pinned) {
502 arity = get_irn_arity(node);
503 in = alloca(arity * sizeof(in[0]));
504 memset(in, 0, arity * sizeof(in[0]));
506 clobbers = get_ASM_clobbers(node);
508 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
509 const arch_register_req_t *req;
510 const char *c = get_id_str(clobbers[i]);
512 if (strcmp(c, "memory") == 0)
514 if (strcmp(c, "cc") == 0) {
519 req = parse_clobber(c);
520 clobber_bits[req->cls->index] |= *req->limited;
524 n_out_constraints = get_ASM_n_output_constraints(node);
525 out_arity = n_out_constraints + n_clobbers;
527 in_constraints = get_ASM_input_constraints(node);
528 out_constraints = get_ASM_output_constraints(node);
530 /* determine size of register_map */
531 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
532 const ir_asm_constraint *constraint = &out_constraints[out_idx];
533 if (constraint->pos > reg_map_size)
534 reg_map_size = constraint->pos;
536 for (i = 0; i < arity; ++i) {
537 const ir_asm_constraint *constraint = &in_constraints[i];
538 if(constraint->pos > reg_map_size)
539 reg_map_size = constraint->pos;
543 obst = get_irg_obstack(irg);
544 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
545 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
547 /* construct output constraints */
548 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
550 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
551 const ir_asm_constraint *constraint = &out_constraints[out_idx];
552 const char *c = get_id_str(constraint->constraint);
553 unsigned pos = constraint->pos;
554 constraint_t parsed_constraint;
555 const arch_register_req_t *req;
557 parse_asm_constraints(&parsed_constraint, c, 1);
558 req = make_register_req(&parsed_constraint, n_out_constraints,
559 out_reg_reqs, out_idx);
560 out_reg_reqs[out_idx] = req;
562 register_map[pos].use_input = 0;
563 register_map[pos].valid = 1;
564 register_map[pos].memory = 0;
565 register_map[pos].inout_pos = out_idx;
566 register_map[pos].mode = constraint->mode;
569 /* inputs + input constraints */
570 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
571 for (i = 0; i < arity; ++i) {
572 ir_node *pred = get_irn_n(node, i);
573 const ir_asm_constraint *constraint = &in_constraints[i];
574 ident *constr_id = constraint->constraint;
575 const char *c = get_id_str(constr_id);
576 unsigned pos = constraint->pos;
577 int is_memory_op = 0;
578 ir_node *input = NULL;
579 unsigned r_clobber_bits;
580 constraint_t parsed_constraint;
581 const arch_register_req_t *req;
583 parse_asm_constraints(&parsed_constraint, c, 0);
584 if (parsed_constraint.cls != NULL) {
585 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
586 if (r_clobber_bits != 0) {
587 if (parsed_constraint.all_registers_allowed) {
588 parsed_constraint.all_registers_allowed = 0;
589 be_abi_set_non_ignore_regs(env_cg->birg->abi,
590 parsed_constraint.cls,
591 &parsed_constraint.allowed_registers);
593 parsed_constraint.allowed_registers &= ~r_clobber_bits;
597 req = make_register_req(&parsed_constraint, n_out_constraints,
599 in_reg_reqs[i] = req;
601 if (parsed_constraint.immediate_type != '\0') {
602 char imm_type = parsed_constraint.immediate_type;
603 input = try_create_Immediate(pred, imm_type);
607 ir_node *pred = NULL;
608 switch (be_transformer) {
609 case TRANSFORMER_DEFAULT:
610 pred = get_irn_n(node, i);
611 input = be_transform_node(pred);
615 case TRANSFORMER_PBQP:
616 input = get_irn_n(node, i);
620 default: panic("invalid transformer");
623 if (parsed_constraint.cls == NULL
624 && parsed_constraint.same_as < 0) {
626 } else if(parsed_constraint.memory_possible) {
627 /* TODO: match Load or Load/Store if memory possible is set */
632 register_map[pos].use_input = 1;
633 register_map[pos].valid = 1;
634 register_map[pos].memory = is_memory_op;
635 register_map[pos].inout_pos = i;
636 register_map[pos].mode = constraint->mode;
640 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
641 const char *c = get_id_str(clobbers[i]);
642 const arch_register_req_t *req;
644 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
647 req = parse_clobber(c);
648 out_reg_reqs[out_idx] = req;
652 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
653 get_ASM_text(node), register_map);
655 /* Prevent the ASM node from being scheduled before the Barrier, if it has
657 if (arity == 0 && get_irg_start_block(irg) == new_block) {
658 add_irn_dep(new_node, get_irg_frame(irg));
661 set_ia32_out_req_all(new_node, out_reg_reqs);
662 set_ia32_in_req_all(new_node, in_reg_reqs);
664 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
669 ir_node *gen_CopyB(ir_node *node) {
670 ir_node *block = NULL;
672 ir_node *new_src = NULL;
674 ir_node *new_dst = NULL;
676 ir_node *new_mem = NULL;
678 ir_graph *irg = current_ir_graph;
679 dbg_info *dbgi = get_irn_dbg_info(node);
680 int size = get_type_size_bytes(get_CopyB_type(node));
683 switch (be_transformer) {
684 case TRANSFORMER_DEFAULT:
685 block = be_transform_node(get_nodes_block(node));
686 src = get_CopyB_src(node);
687 new_src = be_transform_node(src);
688 dst = get_CopyB_dst(node);
689 new_dst = be_transform_node(dst);
690 mem = get_CopyB_mem(node);
691 new_mem = be_transform_node(mem);
695 case TRANSFORMER_PBQP:
696 block = get_nodes_block(node);
697 new_src = get_CopyB_src(node);
698 new_dst = get_CopyB_dst(node);
699 new_mem = get_CopyB_mem(node);
703 default: panic("invalid transformer");
706 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
707 /* then we need the size explicitly in ECX. */
708 if (size >= 32 * 4) {
709 rem = size & 0x3; /* size % 4 */
712 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
713 add_irn_dep(res, get_irg_frame(irg));
715 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
718 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
721 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
724 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
729 ir_node *gen_Proj_tls(ir_node *node) {
730 ir_node *block = NULL;
731 ir_graph *irg = current_ir_graph;
732 dbg_info *dbgi = NULL;
735 switch (be_transformer) {
736 case TRANSFORMER_DEFAULT:
737 block = be_transform_node(get_nodes_block(node));
741 case TRANSFORMER_PBQP:
742 block = get_nodes_block(node);
746 default: panic("invalid transformer");
749 res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
754 ir_node *gen_Unknown(ir_node *node)
756 ir_mode *mode = get_irn_mode(node);
758 if (mode_is_float(mode)) {
759 if (ia32_cg_config.use_sse2) {
760 return ia32_new_Unknown_xmm(env_cg);
762 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
763 ir_graph *irg = current_ir_graph;
764 dbg_info *dbgi = get_irn_dbg_info(node);
765 ir_node *block = get_irg_start_block(irg);
766 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
768 /* Const Nodes before the initial IncSP are a bad idea, because
769 * they could be spilled and we have no SP ready at that point yet.
770 * So add a dependency to the initial frame pointer calculation to
771 * avoid that situation.
773 add_irn_dep(ret, get_irg_frame(irg));
776 } else if (ia32_mode_needs_gp_reg(mode)) {
777 return ia32_new_Unknown_gp(env_cg);
779 panic("unsupported Unknown-Mode");
784 const arch_register_req_t *make_register_req(const constraint_t *constraint,
785 int n_outs, const arch_register_req_t **out_reqs, int pos)
787 struct obstack *obst = get_irg_obstack(current_ir_graph);
788 int same_as = constraint->same_as;
789 arch_register_req_t *req;
792 const arch_register_req_t *other_constr;
794 if (same_as >= n_outs)
795 panic("invalid output number in same_as constraint");
797 other_constr = out_reqs[same_as];
799 req = obstack_alloc(obst, sizeof(req[0]));
800 *req = *other_constr;
801 req->type |= arch_register_req_type_should_be_same;
802 req->other_same = 1U << pos;
804 /* switch constraints. This is because in firm we have same_as
805 * constraints on the output constraints while in the gcc asm syntax
806 * they are specified on the input constraints */
807 out_reqs[same_as] = req;
811 /* pure memory ops */
812 if (constraint->cls == NULL) {
813 return &no_register_req;
816 if (constraint->allowed_registers != 0
817 && !constraint->all_registers_allowed) {
818 unsigned *limited_ptr;
820 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
821 memset(req, 0, sizeof(req[0]));
822 limited_ptr = (unsigned*) (req+1);
824 req->type = arch_register_req_type_limited;
825 *limited_ptr = constraint->allowed_registers;
826 req->limited = limited_ptr;
828 req = obstack_alloc(obst, sizeof(req[0]));
829 memset(req, 0, sizeof(req[0]));
830 req->type = arch_register_req_type_normal;
832 req->cls = constraint->cls;
837 const arch_register_req_t *parse_clobber(const char *clobber)
839 struct obstack *obst = get_irg_obstack(current_ir_graph);
840 const arch_register_t *reg = ia32_get_clobber_register(clobber);
841 arch_register_req_t *req;
845 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
848 assert(reg->index < 32);
850 limited = obstack_alloc(obst, sizeof(limited[0]));
851 *limited = 1 << reg->index;
853 req = obstack_alloc(obst, sizeof(req[0]));
854 memset(req, 0, sizeof(req[0]));
855 req->type = arch_register_req_type_limited;
856 req->cls = arch_register_get_class(reg);
857 req->limited = limited;
862 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
865 tarval *offset = NULL;
868 ir_entity *symconst_ent = NULL;
869 int symconst_sign = 0;
871 ir_node *cnst = NULL;
872 ir_node *symconst = NULL;
875 mode = get_irn_mode(node);
876 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
882 node = get_Minus_op(node);
889 } else if(is_SymConst(node)) {
892 symconst_sign = minus;
893 } else if(is_Add(node)) {
894 ir_node *left = get_Add_left(node);
895 ir_node *right = get_Add_right(node);
896 if(is_Const(left) && is_SymConst(right)) {
899 symconst_sign = minus;
901 } else if(is_SymConst(left) && is_Const(right)) {
904 symconst_sign = minus;
907 } else if(is_Sub(node)) {
908 ir_node *left = get_Sub_left(node);
909 ir_node *right = get_Sub_right(node);
910 if(is_Const(left) && is_SymConst(right)) {
913 symconst_sign = !minus;
915 } else if(is_SymConst(left) && is_Const(right)) {
918 symconst_sign = minus;
919 offset_sign = !minus;
926 offset = get_Const_tarval(cnst);
927 if(tarval_is_long(offset)) {
928 val = get_tarval_long(offset);
930 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
935 if(!check_immediate_constraint(val, immediate_constraint_type))
938 if(symconst != NULL) {
939 if(immediate_constraint_type != 0) {
940 /* we need full 32bits for symconsts */
944 /* unfortunately the assembler/linker doesn't support -symconst */
948 if(get_SymConst_kind(symconst) != symconst_addr_ent)
950 symconst_ent = get_SymConst_entity(symconst);
952 if(cnst == NULL && symconst == NULL)
955 if(offset_sign && offset != NULL) {
956 offset = tarval_neg(offset);
959 new_node = create_Immediate(symconst_ent, symconst_sign, val);