2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
35 #include "betranshlp.h"
38 #include "ia32_architecture.h"
39 #include "ia32_common_transform.h"
40 #include "ia32_new_nodes.h"
42 #include "gen_ia32_new_nodes.h"
43 #include "gen_ia32_regalloc_if.h"
45 ir_heights_t *ia32_heights = NULL;
47 static int check_immediate_constraint(long val, char immediate_constraint_type)
49 switch (immediate_constraint_type) {
53 case 'I': return 0 <= val && val <= 31;
54 case 'J': return 0 <= val && val <= 63;
55 case 'K': return -128 <= val && val <= 127;
56 case 'L': return val == 0xff || val == 0xffff;
57 case 'M': return 0 <= val && val <= 3;
58 case 'N': return 0 <= val && val <= 255;
59 case 'O': return 0 <= val && val <= 127;
61 default: panic("Invalid immediate constraint found");
65 ir_type *ia32_get_prim_type(const ir_mode *mode)
67 if (mode == ia32_mode_E) {
70 return get_type_for_mode(mode);
74 ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
77 ir_entity *res = pmap_get(ir_entity, isa->tv_ent, tv);
78 ir_initializer_t *initializer;
85 mode = get_tarval_mode(tv);
87 if (! ia32_cg_config.use_sse2) {
88 /* try to reduce the mode to produce smaller sized entities */
90 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
92 tv = tarval_convert_to(tv, mode);
93 } else if (mode != mode_D) {
94 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
96 tv = tarval_convert_to(tv, mode);
103 name = id_unique("C%u");
105 tp = ia32_get_prim_type(mode);
106 res = new_entity(get_glob_type(), name, tp);
107 set_entity_ld_ident(res, get_entity_ident(res));
108 set_entity_visibility(res, ir_visibility_private);
109 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
111 initializer = create_initializer_tarval(tv);
112 set_entity_initializer(res, initializer);
114 pmap_insert(isa->tv_ent, tv, res);
118 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
120 ir_graph *irg = current_ir_graph;
121 ir_node *start_block = get_irg_start_block(irg);
122 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
123 symconst_sign, ia32_no_pic_adjust, val);
124 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
129 const arch_register_t *ia32_get_clobber_register(const char *clobber)
131 const arch_register_t *reg = NULL;
134 const arch_register_class_t *cls;
136 /* TODO: construct a hashmap instead of doing linear search for clobber
138 for (c = 0; c < N_IA32_CLASSES; ++c) {
139 cls = & ia32_reg_classes[c];
140 for (r = 0; r < cls->n_regs; ++r) {
141 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
142 if (strcmp(temp_reg->name, clobber) == 0
143 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
155 int ia32_mode_needs_gp_reg(ir_mode *mode)
157 if (mode == ia32_mode_fpcw)
159 if (get_mode_size_bits(mode) > 32)
161 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
164 static void parse_asm_constraints(constraint_t *constraint, const char *c,
167 char immediate_type = '\0';
168 unsigned limited = 0;
169 const arch_register_class_t *cls = NULL;
170 int memory_possible = 0;
171 int all_registers_allowed = 0;
175 memset(constraint, 0, sizeof(constraint[0]));
176 constraint->same_as = -1;
179 /* a memory constraint: no need to do anything in backend about it
180 * (the dependencies are already respected by the memory edge of
185 /* TODO: improve error messages with node and source info. (As users can
186 * easily hit these) */
194 /* Skip out/in-out marker */
204 while (*c != 0 && *c != ',')
209 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
210 cls = &ia32_reg_classes[CLASS_ia32_gp];
211 limited |= 1 << REG_GP_EAX;
214 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
215 cls = &ia32_reg_classes[CLASS_ia32_gp];
216 limited |= 1 << REG_GP_EBX;
219 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
220 cls = &ia32_reg_classes[CLASS_ia32_gp];
221 limited |= 1 << REG_GP_ECX;
224 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
225 cls = &ia32_reg_classes[CLASS_ia32_gp];
226 limited |= 1 << REG_GP_EDX;
229 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
230 cls = &ia32_reg_classes[CLASS_ia32_gp];
231 limited |= 1 << REG_GP_EDI;
234 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
235 cls = &ia32_reg_classes[CLASS_ia32_gp];
236 limited |= 1 << REG_GP_ESI;
240 /* q means lower part of the regs only, this makes no
241 * difference to Q for us (we only assign whole registers) */
242 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
243 cls = &ia32_reg_classes[CLASS_ia32_gp];
244 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
248 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
249 cls = &ia32_reg_classes[CLASS_ia32_gp];
250 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
253 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
254 cls = &ia32_reg_classes[CLASS_ia32_gp];
255 limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
256 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
263 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
264 panic("multiple register classes not supported");
265 cls = &ia32_reg_classes[CLASS_ia32_gp];
266 all_registers_allowed = 1;
272 /* TODO: mark values so the x87 simulator knows about t and u */
273 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_fp])
274 panic("multiple register classes not supported");
275 cls = &ia32_reg_classes[CLASS_ia32_fp];
276 all_registers_allowed = 1;
281 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
282 panic("multiple register classes not supproted");
283 cls = &ia32_reg_classes[CLASS_ia32_xmm];
284 all_registers_allowed = 1;
294 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
295 panic("multiple register classes not supported");
296 if (immediate_type != '\0')
297 panic("multiple immediate types not supported");
298 cls = &ia32_reg_classes[CLASS_ia32_gp];
303 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
304 panic("multiple register classes not supported");
305 if (immediate_type != '\0')
306 panic("multiple immediate types not supported");
307 cls = &ia32_reg_classes[CLASS_ia32_gp];
308 immediate_type = 'i';
313 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
314 panic("multiple register classes not supported");
315 if (immediate_type != '\0')
316 panic("multiple immediate types not supported");
317 immediate_type = 'i';
318 cls = &ia32_reg_classes[CLASS_ia32_gp];
319 all_registers_allowed = 1;
334 panic("can only specify same constraint on input");
336 sscanf(c, "%d%n", &same_as, &p);
346 /* memory constraint no need to do anything in backend about it
347 * (the dependencies are already respected by the memory edge of
352 case 'E': /* no float consts yet */
353 case 'F': /* no float consts yet */
354 case 's': /* makes no sense on x86 */
355 case '<': /* no autodecrement on x86 */
356 case '>': /* no autoincrement on x86 */
357 case 'C': /* sse constant not supported yet */
358 case 'G': /* 80387 constant not supported yet */
359 case 'y': /* we don't support mmx registers yet */
360 case 'Z': /* not available in 32 bit mode */
361 case 'e': /* not available in 32 bit mode */
362 panic("unsupported asm constraint '%c' found in (%+F)",
363 *c, current_ir_graph);
365 panic("unknown asm constraint '%c' found in (%+F)", *c,
373 panic("same as and register constraint not supported");
374 if (immediate_type != '\0')
375 panic("same as and immediate constraint not supported");
378 if (cls == NULL && same_as < 0) {
379 if (!memory_possible)
380 panic("no constraint specified for assembler input");
383 constraint->same_as = same_as;
384 constraint->cls = cls;
385 constraint->allowed_registers = limited;
386 constraint->all_registers_allowed = all_registers_allowed;
387 constraint->memory_possible = memory_possible;
388 constraint->immediate_type = immediate_type;
391 static bool can_match(const arch_register_req_t *in,
392 const arch_register_req_t *out)
394 if (in->cls != out->cls)
396 if (!arch_register_req_is(in, limited) ||
397 !arch_register_req_is(out, limited))
400 return (*in->limited & *out->limited) != 0;
403 static inline ir_node *get_new_node(ir_node *node)
406 if (be_transformer == TRANSFORMER_DEFAULT) {
407 return be_transform_node(node);
412 return be_transform_node(node);
416 static arch_register_req_t const *ia32_make_register_req(constraint_t const *constraint, int n_outs, arch_register_req_t const **out_reqs, int pos);
418 ir_node *ia32_gen_ASM(ir_node *node)
420 ir_node *block = get_nodes_block(node);
421 ir_node *new_block = get_new_node(block);
422 dbg_info *dbgi = get_irn_dbg_info(node);
423 int n_inputs = get_ASM_n_inputs(node);
424 int n_ins = n_inputs+1;
425 ir_node **in = ALLOCANZ(ir_node*, n_ins);
426 size_t n_clobbers = 0;
427 ident **clobbers = get_ASM_clobbers(node);
428 unsigned reg_map_size = 0;
429 ir_graph *irg = get_irn_irg(node);
430 struct obstack *obst = get_irg_obstack(irg);
431 unsigned clobber_bits[N_IA32_CLASSES];
432 memset(&clobber_bits, 0, sizeof(clobber_bits));
434 for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
435 const char *clobber = get_id_str(clobbers[c]);
436 const arch_register_req_t *req = ia32_parse_clobber(clobber);
440 clobber_bits[req->cls->index] |= *req->limited;
441 assert(req->cls->n_regs <= sizeof(unsigned)*8);
444 size_t n_out_constraints = get_ASM_n_output_constraints(node);
445 size_t out_arity = n_out_constraints + n_clobbers;
447 const ir_asm_constraint *in_constraints = get_ASM_input_constraints(node);
448 const ir_asm_constraint *out_constraints = get_ASM_output_constraints(node);
450 /* determine size of register_map */
451 for (size_t out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
452 const ir_asm_constraint *constraint = &out_constraints[out_idx];
453 if (constraint->pos+1 > reg_map_size)
454 reg_map_size = constraint->pos+1;
456 for (int i = 0; i < n_inputs; ++i) {
457 const ir_asm_constraint *constraint = &in_constraints[i];
458 if (constraint->pos+1 > reg_map_size)
459 reg_map_size = constraint->pos+1;
462 ia32_asm_reg_t *register_map
463 = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
464 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
466 /* construct output constraints */
467 size_t out_size = out_arity + 1;
468 const arch_register_req_t **out_reg_reqs
469 = OALLOCN(obst, const arch_register_req_t*, out_size);
472 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
473 constraint_t parsed_constraint;
474 const ir_asm_constraint *constraint = &out_constraints[out_idx];
475 const char *c = get_id_str(constraint->constraint);
476 unsigned pos = constraint->pos;
477 parse_asm_constraints(&parsed_constraint, c, true);
478 const arch_register_req_t *req
479 = ia32_make_register_req(&parsed_constraint, n_out_constraints,
480 out_reg_reqs, out_idx);
481 out_reg_reqs[out_idx] = req;
483 /* multiple constraints for same pos. This can happen for example when
484 * a =A constraint gets lowered to two constraints: =a and =d for the
486 if (register_map[pos].valid)
489 register_map[pos].use_input = 0;
490 register_map[pos].valid = 1;
491 register_map[pos].memory = 0;
492 register_map[pos].inout_pos = out_idx;
493 register_map[pos].mode = constraint->mode;
496 /* inputs + input constraints */
497 const arch_register_req_t **in_reg_reqs
498 = OALLOCN(obst, const arch_register_req_t*, n_ins);
499 for (int i = 0; i < n_inputs; ++i) {
500 constraint_t parsed_constraint;
501 ir_node *pred = get_ASM_input(node, i);
502 const ir_asm_constraint *constraint = &in_constraints[i];
503 ident *constr_id = constraint->constraint;
504 const char *c = get_id_str(constr_id);
505 unsigned pos = constraint->pos;
506 int is_memory_op = 0;
507 ir_node *input = NULL;
509 parse_asm_constraints(&parsed_constraint, c, false);
510 if (parsed_constraint.cls != NULL) {
511 unsigned r_clobber_bits
512 = clobber_bits[parsed_constraint.cls->index];
513 if (r_clobber_bits != 0) {
514 if (parsed_constraint.all_registers_allowed) {
515 parsed_constraint.all_registers_allowed = 0;
516 be_set_allocatable_regs(irg,
517 parsed_constraint.cls,
518 &parsed_constraint.allowed_registers);
520 parsed_constraint.allowed_registers &= ~r_clobber_bits;
524 const arch_register_req_t *req
525 = ia32_make_register_req(&parsed_constraint, n_out_constraints,
527 in_reg_reqs[i] = req;
529 if (parsed_constraint.immediate_type != '\0') {
530 char imm_type = parsed_constraint.immediate_type;
531 input = ia32_try_create_Immediate(pred, imm_type);
535 input = get_new_node(pred);
537 if (parsed_constraint.cls == NULL
538 && parsed_constraint.same_as < 0) {
540 in_reg_reqs[i] = ia32_reg_classes[CLASS_ia32_gp].class_req;
541 } else if (parsed_constraint.memory_possible) {
542 /* TODO: match Load or Load/Store if memory possible is set */
547 register_map[pos].use_input = 1;
548 register_map[pos].valid = 1;
549 register_map[pos].memory = is_memory_op;
550 register_map[pos].inout_pos = i;
551 register_map[pos].mode = constraint->mode;
554 assert(n_inputs == n_ins-1);
555 ir_node *mem = get_ASM_mem(node);
556 in[n_inputs] = be_transform_node(mem);
557 in_reg_reqs[n_inputs] = arch_no_register_req;
560 for (size_t c = 0; c < get_ASM_n_clobbers(node); ++c) {
561 const char *clobber = get_id_str(clobbers[c]);
562 const arch_register_req_t *req = ia32_parse_clobber(clobber);
565 out_reg_reqs[out_idx] = req;
569 /* Attempt to make ASM node register pressure faithful.
570 * (This does not work for complicated cases yet!)
572 * Algorithm: Check if there are fewer inputs or outputs (I will call this
573 * the smaller list). Then try to match each constraint of the smaller list
574 * to 1 of the other list. If we can't match it, then we have to add a dummy
575 * input/output to the other list
577 * FIXME: This is still broken in lots of cases. But at least better than
579 * FIXME: need to do this per register class...
581 if (out_arity <= (size_t)n_inputs) {
582 int orig_inputs = n_ins;
584 bitset_t *used_ins = bitset_alloca(n_ins);
585 for (size_t o = 0; o < out_arity; ++o) {
586 const arch_register_req_t *outreq = out_reg_reqs[o];
588 if (outreq->cls == NULL) {
593 for (i = 0; i < orig_inputs; ++i) {
594 if (bitset_is_set(used_ins, i))
596 const arch_register_req_t *inreq = in_reg_reqs[i];
597 if (!can_match(outreq, inreq))
599 bitset_set(used_ins, i);
602 /* did we find any match? */
606 /* we might need more space in the input arrays */
607 if (n_ins >= in_size) {
609 const arch_register_req_t **new_in_reg_reqs
610 = OALLOCN(obst, const arch_register_req_t*,
612 memcpy(new_in_reg_reqs, in_reg_reqs,
613 n_ins*sizeof(new_in_reg_reqs[0]));
614 ir_node **new_in = ALLOCANZ(ir_node*, in_size);
615 memcpy(new_in, in, n_ins*sizeof(new_in[0]));
617 in_reg_reqs = new_in_reg_reqs;
621 /* add a new (dummy) input which occupies the register */
622 assert(arch_register_req_is(outreq, limited));
623 in_reg_reqs[n_ins] = outreq;
624 in[n_ins] = new_bd_ia32_ProduceVal(NULL, block);
628 bitset_t *used_outs = bitset_alloca(out_arity);
629 size_t orig_out_arity = out_arity;
630 for (int i = 0; i < n_inputs; ++i) {
631 const arch_register_req_t *inreq = in_reg_reqs[i];
633 if (inreq->cls == NULL)
637 for (o = 0; o < orig_out_arity; ++o) {
638 const arch_register_req_t *outreq;
639 if (bitset_is_set(used_outs, o))
641 outreq = out_reg_reqs[o];
642 if (!can_match(outreq, inreq))
644 bitset_set(used_outs, i);
647 /* did we find any match? */
648 if (o < orig_out_arity)
651 /* we might need more space in the output arrays */
652 if (out_arity >= out_size) {
653 const arch_register_req_t **new_out_reg_reqs;
657 = OALLOCN(obst, const arch_register_req_t*, out_size);
658 memcpy(new_out_reg_reqs, out_reg_reqs,
659 out_arity * sizeof(new_out_reg_reqs[0]));
660 out_reg_reqs = new_out_reg_reqs;
663 /* add a new (dummy) output which occupies the register */
664 assert(arch_register_req_is(inreq, limited));
665 out_reg_reqs[out_arity] = inreq;
670 /* append none register requirement for the memory output */
671 if (out_arity + 1 >= out_size) {
672 const arch_register_req_t **new_out_reg_reqs;
674 out_size = out_arity + 1;
676 = OALLOCN(obst, const arch_register_req_t*, out_size);
677 memcpy(new_out_reg_reqs, out_reg_reqs,
678 out_arity * sizeof(new_out_reg_reqs[0]));
679 out_reg_reqs = new_out_reg_reqs;
682 /* add a new (dummy) output which occupies the register */
683 out_reg_reqs[out_arity] = arch_no_register_req;
686 ir_node *new_node = new_bd_ia32_Asm(dbgi, new_block, n_ins, in, out_arity,
687 get_ASM_text(node), register_map);
689 backend_info_t *info = be_get_info(new_node);
690 for (size_t o = 0; o < out_arity; ++o) {
691 info->out_infos[o].req = out_reg_reqs[o];
693 arch_set_irn_register_reqs_in(new_node, in_reg_reqs);
695 SET_IA32_ORIG_NODE(new_node, node);
700 ir_node *ia32_gen_CopyB(ir_node *node)
702 ir_node *block = get_new_node(get_nodes_block(node));
703 ir_node *src = get_CopyB_src(node);
704 ir_node *new_src = get_new_node(src);
705 ir_node *dst = get_CopyB_dst(node);
706 ir_node *new_dst = get_new_node(dst);
707 ir_node *mem = get_CopyB_mem(node);
708 ir_node *new_mem = get_new_node(mem);
710 dbg_info *dbgi = get_irn_dbg_info(node);
711 int size = get_type_size_bytes(get_CopyB_type(node));
712 int throws_exception = ir_throws_exception(node);
715 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
716 /* then we need the size explicitly in ECX. */
717 if (size >= 32 * 4) {
718 rem = size & 0x3; /* size % 4 */
721 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
723 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
726 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
729 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
731 ir_set_throws_exception(res, throws_exception);
733 SET_IA32_ORIG_NODE(res, node);
738 ir_node *ia32_gen_Proj_tls(ir_node *node)
740 ir_node *block = get_new_node(get_nodes_block(node));
741 ir_node *res = new_bd_ia32_LdTls(NULL, block);
745 ir_node *ia32_gen_Unknown(ir_node *node)
747 ir_mode *mode = get_irn_mode(node);
748 ir_graph *irg = current_ir_graph;
749 dbg_info *dbgi = get_irn_dbg_info(node);
750 ir_node *block = get_irg_start_block(irg);
753 if (mode_is_float(mode)) {
754 if (ia32_cg_config.use_sse2) {
755 res = new_bd_ia32_xUnknown(dbgi, block);
757 res = new_bd_ia32_fldz(dbgi, block);
759 } else if (ia32_mode_needs_gp_reg(mode)) {
760 res = new_bd_ia32_Unknown(dbgi, block);
762 panic("unsupported Unknown-Mode");
768 static arch_register_req_t const *ia32_make_register_req(constraint_t const *const constraint, int const n_outs, arch_register_req_t const **const out_reqs, int const pos)
770 struct obstack *obst = get_irg_obstack(current_ir_graph);
771 int same_as = constraint->same_as;
772 arch_register_req_t *req;
775 const arch_register_req_t *other_constr;
777 if (same_as >= n_outs)
778 panic("invalid output number in same_as constraint");
780 other_constr = out_reqs[same_as];
782 req = OALLOC(obst, arch_register_req_t);
783 *req = *other_constr;
784 req->type |= arch_register_req_type_should_be_same;
785 req->other_same = 1U << pos;
788 /* switch constraints. This is because in firm we have same_as
789 * constraints on the output constraints while in the gcc asm syntax
790 * they are specified on the input constraints */
791 out_reqs[same_as] = req;
795 /* pure memory ops */
796 if (constraint->cls == NULL) {
797 return arch_no_register_req;
800 if (constraint->allowed_registers != 0
801 && !constraint->all_registers_allowed) {
802 unsigned *limited_ptr;
804 req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
805 memset(req, 0, sizeof(req[0]));
806 limited_ptr = (unsigned*) (req+1);
808 req->type = arch_register_req_type_limited;
809 *limited_ptr = constraint->allowed_registers;
810 req->limited = limited_ptr;
812 req = OALLOCZ(obst, arch_register_req_t);
813 req->type = arch_register_req_type_normal;
815 req->cls = constraint->cls;
821 const arch_register_req_t *ia32_parse_clobber(const char *clobber)
823 if (strcmp(clobber, "memory") == 0 || strcmp(clobber, "cc") == 0)
826 struct obstack *obst = get_irg_obstack(current_ir_graph);
827 const arch_register_t *reg = ia32_get_clobber_register(clobber);
828 arch_register_req_t *req;
832 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
835 assert(reg->index < 32);
837 limited = OALLOC(obst, unsigned);
838 *limited = 1 << reg->index;
840 req = OALLOCZ(obst, arch_register_req_t);
841 req->type = arch_register_req_type_limited;
842 req->cls = reg->reg_class;
843 req->limited = limited;
850 int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
851 ir_node *const other)
853 if (get_nodes_block(other) != block)
856 if (is_Sync(other)) {
859 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
860 ir_node *const pred = get_Sync_pred(other, i);
862 if (get_nodes_block(pred) != block)
865 /* Do not block ourselves from getting eaten */
866 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
869 if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
877 /* Do not block ourselves from getting eaten */
878 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
881 if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
888 ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
891 ir_entity *symconst_ent = NULL;
893 ir_node *cnst = NULL;
894 ir_node *symconst = NULL;
897 mode = get_irn_mode(node);
898 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
902 if (is_Const(node)) {
905 } else if (is_SymConst_addr_ent(node)
906 && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
909 } else if (is_Add(node)) {
910 ir_node *left = get_Add_left(node);
911 ir_node *right = get_Add_right(node);
912 if (is_Const(left) && is_SymConst_addr_ent(right)) {
915 } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
924 ir_tarval *offset = get_Const_tarval(cnst);
925 if (!tarval_is_long(offset)) {
926 ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
930 val = get_tarval_long(offset);
931 if (!check_immediate_constraint(val, immediate_constraint_type))
934 if (symconst != NULL) {
935 if (immediate_constraint_type != 0) {
936 /* we need full 32bits for symconsts */
940 symconst_ent = get_SymConst_entity(symconst);
942 if (cnst == NULL && symconst == NULL)
945 new_node = ia32_create_Immediate(symconst_ent, 0, val);