2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
35 #include "../beirg_t.h"
37 #include "ia32_architecture.h"
38 #include "ia32_common_transform.h"
39 #include "ia32_new_nodes.h"
41 #include "gen_ia32_new_nodes.h"
42 #include "gen_ia32_regalloc_if.h"
44 /** hold the current code generator during transformation */
45 ia32_code_gen_t *env_cg = NULL;
47 heights_t *heights = NULL;
49 static const arch_register_req_t no_register_req = {
50 arch_register_req_type_none,
52 NULL, /* limit bitset */
57 static int check_immediate_constraint(long val, char immediate_constraint_type)
59 switch (immediate_constraint_type) {
63 case 'I': return 0 <= val && val <= 31;
64 case 'J': return 0 <= val && val <= 63;
65 case 'K': return -128 <= val && val <= 127;
66 case 'L': return val == 0xff || val == 0xffff;
67 case 'M': return 0 <= val && val <= 3;
68 case 'N': return 0 <= val && val <= 255;
69 case 'O': return 0 <= val && val <= 127;
71 default: panic("Invalid immediate constraint found");
75 /* creates a unique ident by adding a number to a tag */
76 ident *ia32_unique_id(const char *tag)
78 static unsigned id = 0;
81 snprintf(str, sizeof(str), tag, ++id);
82 return new_id_from_str(str);
86 * Get a primitive type for a mode with alignment 16.
88 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
90 pmap_entry *e = pmap_find(types, mode);
95 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
96 res = new_type_primitive(new_id_from_str(buf), mode);
97 /* FIXME: this is too much for most cases */
98 set_type_alignment_bytes(res, 16);
99 pmap_insert(types, mode, res);
106 ir_entity *create_float_const_entity(ir_node *cnst)
108 ia32_isa_t *isa = env_cg->isa;
109 tarval *key = get_Const_tarval(cnst);
110 pmap_entry *e = pmap_find(isa->tv_ent, key);
116 ir_mode *mode = get_tarval_mode(tv);
119 if (! ia32_cg_config.use_sse2) {
120 /* try to reduce the mode to produce smaller sized entities */
121 if (mode != mode_F) {
122 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
124 tv = tarval_convert_to(tv, mode);
125 } else if (mode != mode_D) {
126 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
128 tv = tarval_convert_to(tv, mode);
134 if (mode == get_irn_mode(cnst)) {
135 /* mode was not changed */
136 tp = get_Const_type(cnst);
137 if (tp == firm_unknown_type)
138 tp = ia32_get_prim_type(isa->types, mode);
140 tp = ia32_get_prim_type(isa->types, mode);
142 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
144 /* align mode_E at 16 byte for faster access */
145 if (get_mode_size_bits(mode) >= 80) {
146 set_entity_align(res, 16);
149 set_entity_ld_ident(res, get_entity_ident(res));
150 set_entity_visibility(res, visibility_local);
151 set_entity_variability(res, variability_constant);
152 set_entity_allocation(res, allocation_static);
154 /* we create a new entity here: It's initialization must resist on the
156 rem = current_ir_graph;
157 current_ir_graph = get_const_code_irg();
158 set_atomic_ent_value(res, new_Const_type(tv, tp));
159 current_ir_graph = rem;
161 pmap_insert(isa->tv_ent, key, res);
169 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
171 ir_graph *irg = current_ir_graph;
172 ir_node *start_block = get_irg_start_block(irg);
173 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
175 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
180 const arch_register_t *ia32_get_clobber_register(const char *clobber)
182 const arch_register_t *reg = NULL;
185 const arch_register_class_t *cls;
187 /* TODO: construct a hashmap instead of doing linear search for clobber
189 for(c = 0; c < N_CLASSES; ++c) {
190 cls = & ia32_reg_classes[c];
191 for(r = 0; r < cls->n_regs; ++r) {
192 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
193 if (strcmp(temp_reg->name, clobber) == 0
194 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
206 int ia32_mode_needs_gp_reg(ir_mode *mode) {
207 if (mode == mode_fpcw)
209 if (get_mode_size_bits(mode) > 32)
211 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
214 static void parse_asm_constraints(constraint_t *constraint, const char *c,
217 char immediate_type = '\0';
218 unsigned limited = 0;
219 const arch_register_class_t *cls = NULL;
220 int memory_possible = 0;
221 int all_registers_allowed = 0;
225 memset(constraint, 0, sizeof(constraint[0]));
226 constraint->same_as = -1;
229 /* a memory constraint: no need to do anything in backend about it
230 * (the dependencies are already respected by the memory edge of
235 /* TODO: improve error messages with node and source info. (As users can
236 * easily hit these) */
244 /* Skip out/in-out marker */
254 while(*c != 0 && *c != ',')
259 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
260 cls = &ia32_reg_classes[CLASS_ia32_gp];
261 limited |= 1 << REG_EAX;
264 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
265 cls = &ia32_reg_classes[CLASS_ia32_gp];
266 limited |= 1 << REG_EBX;
269 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
270 cls = &ia32_reg_classes[CLASS_ia32_gp];
271 limited |= 1 << REG_ECX;
274 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
275 cls = &ia32_reg_classes[CLASS_ia32_gp];
276 limited |= 1 << REG_EDX;
279 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
280 cls = &ia32_reg_classes[CLASS_ia32_gp];
281 limited |= 1 << REG_EDI;
284 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
285 cls = &ia32_reg_classes[CLASS_ia32_gp];
286 limited |= 1 << REG_ESI;
290 /* q means lower part of the regs only, this makes no
291 * difference to Q for us (we only assign whole registers) */
292 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
293 cls = &ia32_reg_classes[CLASS_ia32_gp];
294 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
298 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
299 cls = &ia32_reg_classes[CLASS_ia32_gp];
300 limited |= 1 << REG_EAX | 1 << REG_EDX;
303 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
304 cls = &ia32_reg_classes[CLASS_ia32_gp];
305 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
306 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
313 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
314 panic("multiple register classes not supported");
315 cls = &ia32_reg_classes[CLASS_ia32_gp];
316 all_registers_allowed = 1;
322 /* TODO: mark values so the x87 simulator knows about t and u */
323 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
324 panic("multiple register classes not supported");
325 cls = &ia32_reg_classes[CLASS_ia32_vfp];
326 all_registers_allowed = 1;
331 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
332 panic("multiple register classes not supproted");
333 cls = &ia32_reg_classes[CLASS_ia32_xmm];
334 all_registers_allowed = 1;
344 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
345 panic("multiple register classes not supported");
346 if (immediate_type != '\0')
347 panic("multiple immediate types not supported");
348 cls = &ia32_reg_classes[CLASS_ia32_gp];
353 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
354 panic("multiple register classes not supported");
355 if (immediate_type != '\0')
356 panic("multiple immediate types not supported");
357 cls = &ia32_reg_classes[CLASS_ia32_gp];
358 immediate_type = 'i';
363 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
364 panic("multiple register classes not supported");
365 if (immediate_type != '\0')
366 panic("multiple immediate types not supported");
367 immediate_type = 'i';
368 cls = &ia32_reg_classes[CLASS_ia32_gp];
369 all_registers_allowed = 1;
384 panic("can only specify same constraint on input");
386 sscanf(c, "%d%n", &same_as, &p);
396 /* memory constraint no need to do anything in backend about it
397 * (the dependencies are already respected by the memory edge of
402 case 'E': /* no float consts yet */
403 case 'F': /* no float consts yet */
404 case 's': /* makes no sense on x86 */
405 case '<': /* no autodecrement on x86 */
406 case '>': /* no autoincrement on x86 */
407 case 'C': /* sse constant not supported yet */
408 case 'G': /* 80387 constant not supported yet */
409 case 'y': /* we don't support mmx registers yet */
410 case 'Z': /* not available in 32 bit mode */
411 case 'e': /* not available in 32 bit mode */
412 panic("unsupported asm constraint '%c' found in (%+F)",
413 *c, current_ir_graph);
416 panic("unknown asm constraint '%c' found in (%+F)", *c,
425 panic("same as and register constraint not supported");
426 if (immediate_type != '\0')
427 panic("same as and immediate constraint not supported");
430 if (cls == NULL && same_as < 0) {
431 if (!memory_possible)
432 panic("no constraint specified for assembler input");
435 constraint->same_as = same_as;
436 constraint->cls = cls;
437 constraint->allowed_registers = limited;
438 constraint->all_registers_allowed = all_registers_allowed;
439 constraint->memory_possible = memory_possible;
440 constraint->immediate_type = immediate_type;
443 ir_node *gen_ASM(ir_node *node)
445 ir_node *block = NULL;
446 ir_node *new_block = NULL;
447 dbg_info *dbgi = get_irn_dbg_info(node);
453 int n_out_constraints;
455 const arch_register_req_t **out_reg_reqs;
456 const arch_register_req_t **in_reg_reqs;
457 ia32_asm_reg_t *register_map;
458 unsigned reg_map_size = 0;
459 struct obstack *obst;
460 const ir_asm_constraint *in_constraints;
461 const ir_asm_constraint *out_constraints;
463 int clobbers_flags = 0;
464 unsigned clobber_bits[N_CLASSES];
466 memset(&clobber_bits, 0, sizeof(clobber_bits));
468 switch (be_transformer) {
469 case TRANSFORMER_DEFAULT:
470 block = get_nodes_block(node);
471 new_block = be_transform_node(block);
475 case TRANSFORMER_PBQP:
476 case TRANSFORMER_RAND:
477 new_block = get_nodes_block(node);
482 panic("invalid transformer");
485 /* workaround for lots of buggy code out there as most people think volatile
486 * asm is enough for everything and forget the flags (linux kernel, etc.)
488 if (get_irn_pinned(node) == op_pin_state_pinned) {
492 arity = get_irn_arity(node);
493 in = ALLOCANZ(ir_node*, arity);
495 clobbers = get_ASM_clobbers(node);
497 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
498 const arch_register_req_t *req;
499 const char *c = get_id_str(clobbers[i]);
501 if (strcmp(c, "memory") == 0)
503 if (strcmp(c, "cc") == 0) {
508 req = parse_clobber(c);
509 clobber_bits[req->cls->index] |= *req->limited;
513 n_out_constraints = get_ASM_n_output_constraints(node);
514 out_arity = n_out_constraints + n_clobbers;
516 in_constraints = get_ASM_input_constraints(node);
517 out_constraints = get_ASM_output_constraints(node);
519 /* determine size of register_map */
520 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
521 const ir_asm_constraint *constraint = &out_constraints[out_idx];
522 if (constraint->pos > reg_map_size)
523 reg_map_size = constraint->pos;
525 for (i = 0; i < arity; ++i) {
526 const ir_asm_constraint *constraint = &in_constraints[i];
527 if (constraint->pos > reg_map_size)
528 reg_map_size = constraint->pos;
532 obst = get_irg_obstack(current_ir_graph);
533 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
534 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
536 /* construct output constraints */
537 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
539 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
540 const ir_asm_constraint *constraint = &out_constraints[out_idx];
541 const char *c = get_id_str(constraint->constraint);
542 unsigned pos = constraint->pos;
543 constraint_t parsed_constraint;
544 const arch_register_req_t *req;
546 parse_asm_constraints(&parsed_constraint, c, 1);
547 req = make_register_req(&parsed_constraint, n_out_constraints,
548 out_reg_reqs, out_idx);
549 out_reg_reqs[out_idx] = req;
551 register_map[pos].use_input = 0;
552 register_map[pos].valid = 1;
553 register_map[pos].memory = 0;
554 register_map[pos].inout_pos = out_idx;
555 register_map[pos].mode = constraint->mode;
558 /* inputs + input constraints */
559 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
560 for (i = 0; i < arity; ++i) {
561 ir_node *pred = get_irn_n(node, i);
562 const ir_asm_constraint *constraint = &in_constraints[i];
563 ident *constr_id = constraint->constraint;
564 const char *c = get_id_str(constr_id);
565 unsigned pos = constraint->pos;
566 int is_memory_op = 0;
567 ir_node *input = NULL;
568 unsigned r_clobber_bits;
569 constraint_t parsed_constraint;
570 const arch_register_req_t *req;
572 parse_asm_constraints(&parsed_constraint, c, 0);
573 if (parsed_constraint.cls != NULL) {
574 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
575 if (r_clobber_bits != 0) {
576 if (parsed_constraint.all_registers_allowed) {
577 parsed_constraint.all_registers_allowed = 0;
578 be_abi_set_non_ignore_regs(env_cg->birg->abi,
579 parsed_constraint.cls,
580 &parsed_constraint.allowed_registers);
582 parsed_constraint.allowed_registers &= ~r_clobber_bits;
586 req = make_register_req(&parsed_constraint, n_out_constraints,
588 in_reg_reqs[i] = req;
590 if (parsed_constraint.immediate_type != '\0') {
591 char imm_type = parsed_constraint.immediate_type;
592 input = try_create_Immediate(pred, imm_type);
596 ir_node *pred = NULL;
597 switch (be_transformer) {
598 case TRANSFORMER_DEFAULT:
599 pred = get_irn_n(node, i);
600 input = be_transform_node(pred);
604 case TRANSFORMER_PBQP:
605 case TRANSFORMER_RAND:
606 input = get_irn_n(node, i);
610 default: panic("invalid transformer");
613 if (parsed_constraint.cls == NULL
614 && parsed_constraint.same_as < 0) {
616 } else if (parsed_constraint.memory_possible) {
617 /* TODO: match Load or Load/Store if memory possible is set */
622 register_map[pos].use_input = 1;
623 register_map[pos].valid = 1;
624 register_map[pos].memory = is_memory_op;
625 register_map[pos].inout_pos = i;
626 register_map[pos].mode = constraint->mode;
630 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
631 const char *c = get_id_str(clobbers[i]);
632 const arch_register_req_t *req;
634 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
637 req = parse_clobber(c);
638 out_reg_reqs[out_idx] = req;
642 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
643 get_ASM_text(node), register_map);
646 be_dep_on_frame(new_node);
648 set_ia32_out_req_all(new_node, out_reg_reqs);
649 set_ia32_in_req_all(new_node, in_reg_reqs);
651 SET_IA32_ORIG_NODE(new_node, node);
656 ir_node *gen_CopyB(ir_node *node) {
657 ir_node *block = NULL;
659 ir_node *new_src = NULL;
661 ir_node *new_dst = NULL;
663 ir_node *new_mem = NULL;
665 dbg_info *dbgi = get_irn_dbg_info(node);
666 int size = get_type_size_bytes(get_CopyB_type(node));
669 switch (be_transformer) {
670 case TRANSFORMER_DEFAULT:
671 block = be_transform_node(get_nodes_block(node));
672 src = get_CopyB_src(node);
673 new_src = be_transform_node(src);
674 dst = get_CopyB_dst(node);
675 new_dst = be_transform_node(dst);
676 mem = get_CopyB_mem(node);
677 new_mem = be_transform_node(mem);
681 case TRANSFORMER_PBQP:
682 case TRANSFORMER_RAND:
683 block = get_nodes_block(node);
684 new_src = get_CopyB_src(node);
685 new_dst = get_CopyB_dst(node);
686 new_mem = get_CopyB_mem(node);
690 default: panic("invalid transformer");
693 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
694 /* then we need the size explicitly in ECX. */
695 if (size >= 32 * 4) {
696 rem = size & 0x3; /* size % 4 */
699 res = new_bd_ia32_Const(dbgi, block, NULL, 0, size);
700 be_dep_on_frame(res);
702 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
705 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
708 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
711 SET_IA32_ORIG_NODE(res, node);
716 ir_node *gen_Proj_tls(ir_node *node) {
717 ir_node *block = NULL;
718 dbg_info *dbgi = NULL;
721 switch (be_transformer) {
722 case TRANSFORMER_DEFAULT:
723 block = be_transform_node(get_nodes_block(node));
727 case TRANSFORMER_PBQP:
728 case TRANSFORMER_RAND:
729 block = get_nodes_block(node);
733 default: panic("invalid transformer");
736 res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
741 ir_node *gen_Unknown(ir_node *node)
743 ir_mode *mode = get_irn_mode(node);
745 if (mode_is_float(mode)) {
746 if (ia32_cg_config.use_sse2) {
747 return ia32_new_Unknown_xmm(env_cg);
749 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
750 ir_graph *irg = current_ir_graph;
751 dbg_info *dbgi = get_irn_dbg_info(node);
752 ir_node *block = get_irg_start_block(irg);
753 ir_node *ret = new_bd_ia32_vfldz(dbgi, block);
755 be_dep_on_frame(ret);
758 } else if (ia32_mode_needs_gp_reg(mode)) {
759 return ia32_new_Unknown_gp(env_cg);
761 panic("unsupported Unknown-Mode");
766 const arch_register_req_t *make_register_req(const constraint_t *constraint,
767 int n_outs, const arch_register_req_t **out_reqs, int pos)
769 struct obstack *obst = get_irg_obstack(current_ir_graph);
770 int same_as = constraint->same_as;
771 arch_register_req_t *req;
774 const arch_register_req_t *other_constr;
776 if (same_as >= n_outs)
777 panic("invalid output number in same_as constraint");
779 other_constr = out_reqs[same_as];
781 req = obstack_alloc(obst, sizeof(req[0]));
782 *req = *other_constr;
783 req->type |= arch_register_req_type_should_be_same;
784 req->other_same = 1U << pos;
786 /* switch constraints. This is because in firm we have same_as
787 * constraints on the output constraints while in the gcc asm syntax
788 * they are specified on the input constraints */
789 out_reqs[same_as] = req;
793 /* pure memory ops */
794 if (constraint->cls == NULL) {
795 return &no_register_req;
798 if (constraint->allowed_registers != 0
799 && !constraint->all_registers_allowed) {
800 unsigned *limited_ptr;
802 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
803 memset(req, 0, sizeof(req[0]));
804 limited_ptr = (unsigned*) (req+1);
806 req->type = arch_register_req_type_limited;
807 *limited_ptr = constraint->allowed_registers;
808 req->limited = limited_ptr;
810 req = obstack_alloc(obst, sizeof(req[0]));
811 memset(req, 0, sizeof(req[0]));
812 req->type = arch_register_req_type_normal;
814 req->cls = constraint->cls;
819 const arch_register_req_t *parse_clobber(const char *clobber)
821 struct obstack *obst = get_irg_obstack(current_ir_graph);
822 const arch_register_t *reg = ia32_get_clobber_register(clobber);
823 arch_register_req_t *req;
827 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
830 assert(reg->index < 32);
832 limited = obstack_alloc(obst, sizeof(limited[0]));
833 *limited = 1 << reg->index;
835 req = obstack_alloc(obst, sizeof(req[0]));
836 memset(req, 0, sizeof(req[0]));
837 req->type = arch_register_req_type_limited;
838 req->cls = arch_register_get_class(reg);
839 req->limited = limited;
845 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
846 ir_node *const other)
848 if (get_nodes_block(other) != block)
851 if (is_Sync(other)) {
854 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
855 ir_node *const pred = get_Sync_pred(other, i);
857 if (get_nodes_block(pred) != block)
860 /* Do not block ourselves from getting eaten */
861 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
864 if (!heights_reachable_in_block(heights, pred, am_candidate))
872 /* Do not block ourselves from getting eaten */
873 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
876 if (!heights_reachable_in_block(heights, other, am_candidate))
883 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
886 tarval *offset = NULL;
889 ir_entity *symconst_ent = NULL;
890 int symconst_sign = 0;
892 ir_node *cnst = NULL;
893 ir_node *symconst = NULL;
896 mode = get_irn_mode(node);
897 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
901 if (is_Minus(node)) {
903 node = get_Minus_op(node);
906 if (is_Const(node)) {
910 } else if (is_SymConst(node)) {
913 symconst_sign = minus;
914 } else if (is_Add(node)) {
915 ir_node *left = get_Add_left(node);
916 ir_node *right = get_Add_right(node);
917 if (is_Const(left) && is_SymConst(right)) {
920 symconst_sign = minus;
922 } else if (is_SymConst(left) && is_Const(right)) {
925 symconst_sign = minus;
928 } else if (is_Sub(node)) {
929 ir_node *left = get_Sub_left(node);
930 ir_node *right = get_Sub_right(node);
931 if (is_Const(left) && is_SymConst(right)) {
934 symconst_sign = !minus;
936 } else if (is_SymConst(left) && is_Const(right)) {
939 symconst_sign = minus;
940 offset_sign = !minus;
947 offset = get_Const_tarval(cnst);
948 if (tarval_is_long(offset)) {
949 val = get_tarval_long(offset);
951 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
956 if (!check_immediate_constraint(val, immediate_constraint_type))
959 if (symconst != NULL) {
960 if (immediate_constraint_type != 0) {
961 /* we need full 32bits for symconsts */
965 /* unfortunately the assembler/linker doesn't support -symconst */
969 if (get_SymConst_kind(symconst) != symconst_addr_ent)
971 symconst_ent = get_SymConst_entity(symconst);
973 if (cnst == NULL && symconst == NULL)
976 if (offset_sign && offset != NULL) {
977 offset = tarval_neg(offset);
980 new_node = create_Immediate(symconst_ent, symconst_sign, val);