2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
35 #include "../beirg_t.h"
37 #include "ia32_architecture.h"
38 #include "ia32_common_transform.h"
39 #include "ia32_new_nodes.h"
41 #include "gen_ia32_new_nodes.h"
42 #include "gen_ia32_regalloc_if.h"
44 /** hold the current code generator during transformation */
45 ia32_code_gen_t *env_cg = NULL;
47 heights_t *heights = NULL;
49 static const arch_register_req_t no_register_req = {
50 arch_register_req_type_none,
52 NULL, /* limit bitset */
57 static int check_immediate_constraint(long val, char immediate_constraint_type)
59 switch (immediate_constraint_type) {
63 case 'I': return 0 <= val && val <= 31;
64 case 'J': return 0 <= val && val <= 63;
65 case 'K': return -128 <= val && val <= 127;
66 case 'L': return val == 0xff || val == 0xffff;
67 case 'M': return 0 <= val && val <= 3;
68 case 'N': return 0 <= val && val <= 255;
69 case 'O': return 0 <= val && val <= 127;
71 default: panic("Invalid immediate constraint found");
76 * creates a unique ident by adding a number to a tag
78 * @param tag the tag string, must contain a %d if a number
81 static ident *unique_id(const char *tag)
83 static unsigned id = 0;
86 snprintf(str, sizeof(str), tag, ++id);
87 return new_id_from_str(str);
91 * Get a primitive type for a mode.
93 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
95 pmap_entry *e = pmap_find(types, mode);
100 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
101 res = new_type_primitive(new_id_from_str(buf), mode);
102 set_type_alignment_bytes(res, 16);
103 pmap_insert(types, mode, res);
110 ir_entity *create_float_const_entity(ir_node *cnst)
112 ia32_isa_t *isa = env_cg->isa;
113 tarval *key = get_Const_tarval(cnst);
114 pmap_entry *e = pmap_find(isa->tv_ent, key);
120 ir_mode *mode = get_tarval_mode(tv);
123 if (! ia32_cg_config.use_sse2) {
124 /* try to reduce the mode to produce smaller sized entities */
125 if (mode != mode_F) {
126 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
128 tv = tarval_convert_to(tv, mode);
129 } else if (mode != mode_D) {
130 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
132 tv = tarval_convert_to(tv, mode);
138 if (mode == get_irn_mode(cnst)) {
139 /* mode was not changed */
140 tp = get_Const_type(cnst);
141 if (tp == firm_unknown_type)
142 tp = ia32_get_prim_type(isa->types, mode);
144 tp = ia32_get_prim_type(isa->types, mode);
146 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
148 set_entity_ld_ident(res, get_entity_ident(res));
149 set_entity_visibility(res, visibility_local);
150 set_entity_variability(res, variability_constant);
151 set_entity_allocation(res, allocation_static);
153 /* we create a new entity here: It's initialization must resist on the
155 rem = current_ir_graph;
156 current_ir_graph = get_const_code_irg();
157 set_atomic_ent_value(res, new_Const_type(tv, tp));
158 current_ir_graph = rem;
160 pmap_insert(isa->tv_ent, key, res);
168 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
170 ir_graph *irg = current_ir_graph;
171 ir_node *start_block = get_irg_start_block(irg);
172 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
174 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
179 const arch_register_t *ia32_get_clobber_register(const char *clobber)
181 const arch_register_t *reg = NULL;
184 const arch_register_class_t *cls;
186 /* TODO: construct a hashmap instead of doing linear search for clobber
188 for(c = 0; c < N_CLASSES; ++c) {
189 cls = & ia32_reg_classes[c];
190 for(r = 0; r < cls->n_regs; ++r) {
191 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
192 if (strcmp(temp_reg->name, clobber) == 0
193 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
205 int ia32_mode_needs_gp_reg(ir_mode *mode) {
206 if (mode == mode_fpcw)
208 if (get_mode_size_bits(mode) > 32)
210 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
213 static void parse_asm_constraints(constraint_t *constraint, const char *c,
216 char immediate_type = '\0';
217 unsigned limited = 0;
218 const arch_register_class_t *cls = NULL;
219 int memory_possible = 0;
220 int all_registers_allowed = 0;
224 memset(constraint, 0, sizeof(constraint[0]));
225 constraint->same_as = -1;
228 /* a memory constraint: no need to do anything in backend about it
229 * (the dependencies are already respected by the memory edge of
234 /* TODO: improve error messages with node and source info. (As users can
235 * easily hit these) */
243 /* Skip out/in-out marker */
253 while(*c != 0 && *c != ',')
258 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
259 cls = &ia32_reg_classes[CLASS_ia32_gp];
260 limited |= 1 << REG_EAX;
263 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
264 cls = &ia32_reg_classes[CLASS_ia32_gp];
265 limited |= 1 << REG_EBX;
268 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
269 cls = &ia32_reg_classes[CLASS_ia32_gp];
270 limited |= 1 << REG_ECX;
273 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
274 cls = &ia32_reg_classes[CLASS_ia32_gp];
275 limited |= 1 << REG_EDX;
278 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
279 cls = &ia32_reg_classes[CLASS_ia32_gp];
280 limited |= 1 << REG_EDI;
283 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
284 cls = &ia32_reg_classes[CLASS_ia32_gp];
285 limited |= 1 << REG_ESI;
289 /* q means lower part of the regs only, this makes no
290 * difference to Q for us (we only assign whole registers) */
291 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
292 cls = &ia32_reg_classes[CLASS_ia32_gp];
293 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
297 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
298 cls = &ia32_reg_classes[CLASS_ia32_gp];
299 limited |= 1 << REG_EAX | 1 << REG_EDX;
302 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
303 cls = &ia32_reg_classes[CLASS_ia32_gp];
304 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
305 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
312 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
313 panic("multiple register classes not supported");
314 cls = &ia32_reg_classes[CLASS_ia32_gp];
315 all_registers_allowed = 1;
321 /* TODO: mark values so the x87 simulator knows about t and u */
322 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
323 panic("multiple register classes not supported");
324 cls = &ia32_reg_classes[CLASS_ia32_vfp];
325 all_registers_allowed = 1;
330 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
331 panic("multiple register classes not supproted");
332 cls = &ia32_reg_classes[CLASS_ia32_xmm];
333 all_registers_allowed = 1;
343 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
344 panic("multiple register classes not supported");
345 if (immediate_type != '\0')
346 panic("multiple immediate types not supported");
347 cls = &ia32_reg_classes[CLASS_ia32_gp];
352 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
353 panic("multiple register classes not supported");
354 if (immediate_type != '\0')
355 panic("multiple immediate types not supported");
356 cls = &ia32_reg_classes[CLASS_ia32_gp];
357 immediate_type = 'i';
362 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
363 panic("multiple register classes not supported");
364 if (immediate_type != '\0')
365 panic("multiple immediate types not supported");
366 immediate_type = 'i';
367 cls = &ia32_reg_classes[CLASS_ia32_gp];
368 all_registers_allowed = 1;
383 panic("can only specify same constraint on input");
385 sscanf(c, "%d%n", &same_as, &p);
395 /* memory constraint no need to do anything in backend about it
396 * (the dependencies are already respected by the memory edge of
401 case 'E': /* no float consts yet */
402 case 'F': /* no float consts yet */
403 case 's': /* makes no sense on x86 */
404 case '<': /* no autodecrement on x86 */
405 case '>': /* no autoincrement on x86 */
406 case 'C': /* sse constant not supported yet */
407 case 'G': /* 80387 constant not supported yet */
408 case 'y': /* we don't support mmx registers yet */
409 case 'Z': /* not available in 32 bit mode */
410 case 'e': /* not available in 32 bit mode */
411 panic("unsupported asm constraint '%c' found in (%+F)",
412 *c, current_ir_graph);
415 panic("unknown asm constraint '%c' found in (%+F)", *c,
424 panic("same as and register constraint not supported");
425 if (immediate_type != '\0')
426 panic("same as and immediate constraint not supported");
429 if (cls == NULL && same_as < 0) {
430 if (!memory_possible)
431 panic("no constraint specified for assembler input");
434 constraint->same_as = same_as;
435 constraint->cls = cls;
436 constraint->allowed_registers = limited;
437 constraint->all_registers_allowed = all_registers_allowed;
438 constraint->memory_possible = memory_possible;
439 constraint->immediate_type = immediate_type;
442 ir_node *gen_ASM(ir_node *node)
444 ir_node *block = NULL;
445 ir_node *new_block = NULL;
446 dbg_info *dbgi = get_irn_dbg_info(node);
452 int n_out_constraints;
454 const arch_register_req_t **out_reg_reqs;
455 const arch_register_req_t **in_reg_reqs;
456 ia32_asm_reg_t *register_map;
457 unsigned reg_map_size = 0;
458 struct obstack *obst;
459 const ir_asm_constraint *in_constraints;
460 const ir_asm_constraint *out_constraints;
462 int clobbers_flags = 0;
463 unsigned clobber_bits[N_CLASSES];
465 memset(&clobber_bits, 0, sizeof(clobber_bits));
467 switch (be_transformer) {
468 case TRANSFORMER_DEFAULT:
469 block = get_nodes_block(node);
470 new_block = be_transform_node(block);
474 case TRANSFORMER_PBQP:
475 case TRANSFORMER_RAND:
476 new_block = get_nodes_block(node);
481 panic("invalid transformer");
484 /* workaround for lots of buggy code out there as most people think volatile
485 * asm is enough for everything and forget the flags (linux kernel, etc.)
487 if (get_irn_pinned(node) == op_pin_state_pinned) {
491 arity = get_irn_arity(node);
492 in = ALLOCANZ(ir_node*, arity);
494 clobbers = get_ASM_clobbers(node);
496 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
497 const arch_register_req_t *req;
498 const char *c = get_id_str(clobbers[i]);
500 if (strcmp(c, "memory") == 0)
502 if (strcmp(c, "cc") == 0) {
507 req = parse_clobber(c);
508 clobber_bits[req->cls->index] |= *req->limited;
512 n_out_constraints = get_ASM_n_output_constraints(node);
513 out_arity = n_out_constraints + n_clobbers;
515 in_constraints = get_ASM_input_constraints(node);
516 out_constraints = get_ASM_output_constraints(node);
518 /* determine size of register_map */
519 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
520 const ir_asm_constraint *constraint = &out_constraints[out_idx];
521 if (constraint->pos > reg_map_size)
522 reg_map_size = constraint->pos;
524 for (i = 0; i < arity; ++i) {
525 const ir_asm_constraint *constraint = &in_constraints[i];
526 if (constraint->pos > reg_map_size)
527 reg_map_size = constraint->pos;
531 obst = get_irg_obstack(current_ir_graph);
532 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
533 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
535 /* construct output constraints */
536 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
538 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
539 const ir_asm_constraint *constraint = &out_constraints[out_idx];
540 const char *c = get_id_str(constraint->constraint);
541 unsigned pos = constraint->pos;
542 constraint_t parsed_constraint;
543 const arch_register_req_t *req;
545 parse_asm_constraints(&parsed_constraint, c, 1);
546 req = make_register_req(&parsed_constraint, n_out_constraints,
547 out_reg_reqs, out_idx);
548 out_reg_reqs[out_idx] = req;
550 register_map[pos].use_input = 0;
551 register_map[pos].valid = 1;
552 register_map[pos].memory = 0;
553 register_map[pos].inout_pos = out_idx;
554 register_map[pos].mode = constraint->mode;
557 /* inputs + input constraints */
558 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
559 for (i = 0; i < arity; ++i) {
560 ir_node *pred = get_irn_n(node, i);
561 const ir_asm_constraint *constraint = &in_constraints[i];
562 ident *constr_id = constraint->constraint;
563 const char *c = get_id_str(constr_id);
564 unsigned pos = constraint->pos;
565 int is_memory_op = 0;
566 ir_node *input = NULL;
567 unsigned r_clobber_bits;
568 constraint_t parsed_constraint;
569 const arch_register_req_t *req;
571 parse_asm_constraints(&parsed_constraint, c, 0);
572 if (parsed_constraint.cls != NULL) {
573 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
574 if (r_clobber_bits != 0) {
575 if (parsed_constraint.all_registers_allowed) {
576 parsed_constraint.all_registers_allowed = 0;
577 be_abi_set_non_ignore_regs(env_cg->birg->abi,
578 parsed_constraint.cls,
579 &parsed_constraint.allowed_registers);
581 parsed_constraint.allowed_registers &= ~r_clobber_bits;
585 req = make_register_req(&parsed_constraint, n_out_constraints,
587 in_reg_reqs[i] = req;
589 if (parsed_constraint.immediate_type != '\0') {
590 char imm_type = parsed_constraint.immediate_type;
591 input = try_create_Immediate(pred, imm_type);
595 ir_node *pred = NULL;
596 switch (be_transformer) {
597 case TRANSFORMER_DEFAULT:
598 pred = get_irn_n(node, i);
599 input = be_transform_node(pred);
603 case TRANSFORMER_PBQP:
604 case TRANSFORMER_RAND:
605 input = get_irn_n(node, i);
609 default: panic("invalid transformer");
612 if (parsed_constraint.cls == NULL
613 && parsed_constraint.same_as < 0) {
615 } else if (parsed_constraint.memory_possible) {
616 /* TODO: match Load or Load/Store if memory possible is set */
621 register_map[pos].use_input = 1;
622 register_map[pos].valid = 1;
623 register_map[pos].memory = is_memory_op;
624 register_map[pos].inout_pos = i;
625 register_map[pos].mode = constraint->mode;
629 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
630 const char *c = get_id_str(clobbers[i]);
631 const arch_register_req_t *req;
633 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
636 req = parse_clobber(c);
637 out_reg_reqs[out_idx] = req;
641 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
642 get_ASM_text(node), register_map);
645 be_dep_on_frame(new_node);
647 set_ia32_out_req_all(new_node, out_reg_reqs);
648 set_ia32_in_req_all(new_node, in_reg_reqs);
650 SET_IA32_ORIG_NODE(new_node, node);
655 ir_node *gen_CopyB(ir_node *node) {
656 ir_node *block = NULL;
658 ir_node *new_src = NULL;
660 ir_node *new_dst = NULL;
662 ir_node *new_mem = NULL;
664 dbg_info *dbgi = get_irn_dbg_info(node);
665 int size = get_type_size_bytes(get_CopyB_type(node));
668 switch (be_transformer) {
669 case TRANSFORMER_DEFAULT:
670 block = be_transform_node(get_nodes_block(node));
671 src = get_CopyB_src(node);
672 new_src = be_transform_node(src);
673 dst = get_CopyB_dst(node);
674 new_dst = be_transform_node(dst);
675 mem = get_CopyB_mem(node);
676 new_mem = be_transform_node(mem);
680 case TRANSFORMER_PBQP:
681 case TRANSFORMER_RAND:
682 block = get_nodes_block(node);
683 new_src = get_CopyB_src(node);
684 new_dst = get_CopyB_dst(node);
685 new_mem = get_CopyB_mem(node);
689 default: panic("invalid transformer");
692 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
693 /* then we need the size explicitly in ECX. */
694 if (size >= 32 * 4) {
695 rem = size & 0x3; /* size % 4 */
698 res = new_bd_ia32_Const(dbgi, block, NULL, 0, size);
699 be_dep_on_frame(res);
701 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
704 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
707 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
710 SET_IA32_ORIG_NODE(res, node);
715 ir_node *gen_Proj_tls(ir_node *node) {
716 ir_node *block = NULL;
717 dbg_info *dbgi = NULL;
720 switch (be_transformer) {
721 case TRANSFORMER_DEFAULT:
722 block = be_transform_node(get_nodes_block(node));
726 case TRANSFORMER_PBQP:
727 case TRANSFORMER_RAND:
728 block = get_nodes_block(node);
732 default: panic("invalid transformer");
735 res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
740 ir_node *gen_Unknown(ir_node *node)
742 ir_mode *mode = get_irn_mode(node);
744 if (mode_is_float(mode)) {
745 if (ia32_cg_config.use_sse2) {
746 return ia32_new_Unknown_xmm(env_cg);
748 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
749 ir_graph *irg = current_ir_graph;
750 dbg_info *dbgi = get_irn_dbg_info(node);
751 ir_node *block = get_irg_start_block(irg);
752 ir_node *ret = new_bd_ia32_vfldz(dbgi, block);
754 be_dep_on_frame(ret);
757 } else if (ia32_mode_needs_gp_reg(mode)) {
758 return ia32_new_Unknown_gp(env_cg);
760 panic("unsupported Unknown-Mode");
765 const arch_register_req_t *make_register_req(const constraint_t *constraint,
766 int n_outs, const arch_register_req_t **out_reqs, int pos)
768 struct obstack *obst = get_irg_obstack(current_ir_graph);
769 int same_as = constraint->same_as;
770 arch_register_req_t *req;
773 const arch_register_req_t *other_constr;
775 if (same_as >= n_outs)
776 panic("invalid output number in same_as constraint");
778 other_constr = out_reqs[same_as];
780 req = obstack_alloc(obst, sizeof(req[0]));
781 *req = *other_constr;
782 req->type |= arch_register_req_type_should_be_same;
783 req->other_same = 1U << pos;
785 /* switch constraints. This is because in firm we have same_as
786 * constraints on the output constraints while in the gcc asm syntax
787 * they are specified on the input constraints */
788 out_reqs[same_as] = req;
792 /* pure memory ops */
793 if (constraint->cls == NULL) {
794 return &no_register_req;
797 if (constraint->allowed_registers != 0
798 && !constraint->all_registers_allowed) {
799 unsigned *limited_ptr;
801 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
802 memset(req, 0, sizeof(req[0]));
803 limited_ptr = (unsigned*) (req+1);
805 req->type = arch_register_req_type_limited;
806 *limited_ptr = constraint->allowed_registers;
807 req->limited = limited_ptr;
809 req = obstack_alloc(obst, sizeof(req[0]));
810 memset(req, 0, sizeof(req[0]));
811 req->type = arch_register_req_type_normal;
813 req->cls = constraint->cls;
818 const arch_register_req_t *parse_clobber(const char *clobber)
820 struct obstack *obst = get_irg_obstack(current_ir_graph);
821 const arch_register_t *reg = ia32_get_clobber_register(clobber);
822 arch_register_req_t *req;
826 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
829 assert(reg->index < 32);
831 limited = obstack_alloc(obst, sizeof(limited[0]));
832 *limited = 1 << reg->index;
834 req = obstack_alloc(obst, sizeof(req[0]));
835 memset(req, 0, sizeof(req[0]));
836 req->type = arch_register_req_type_limited;
837 req->cls = arch_register_get_class(reg);
838 req->limited = limited;
844 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
845 ir_node *const other)
847 if (get_nodes_block(other) != block)
850 if (is_Sync(other)) {
853 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
854 ir_node *const pred = get_Sync_pred(other, i);
856 if (get_nodes_block(pred) != block)
859 /* Do not block ourselves from getting eaten */
860 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
863 if (!heights_reachable_in_block(heights, pred, am_candidate))
871 /* Do not block ourselves from getting eaten */
872 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
875 if (!heights_reachable_in_block(heights, other, am_candidate))
882 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
885 tarval *offset = NULL;
888 ir_entity *symconst_ent = NULL;
889 int symconst_sign = 0;
891 ir_node *cnst = NULL;
892 ir_node *symconst = NULL;
895 mode = get_irn_mode(node);
896 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
900 if (is_Minus(node)) {
902 node = get_Minus_op(node);
905 if (is_Const(node)) {
909 } else if (is_SymConst(node)) {
912 symconst_sign = minus;
913 } else if (is_Add(node)) {
914 ir_node *left = get_Add_left(node);
915 ir_node *right = get_Add_right(node);
916 if (is_Const(left) && is_SymConst(right)) {
919 symconst_sign = minus;
921 } else if (is_SymConst(left) && is_Const(right)) {
924 symconst_sign = minus;
927 } else if (is_Sub(node)) {
928 ir_node *left = get_Sub_left(node);
929 ir_node *right = get_Sub_right(node);
930 if (is_Const(left) && is_SymConst(right)) {
933 symconst_sign = !minus;
935 } else if (is_SymConst(left) && is_Const(right)) {
938 symconst_sign = minus;
939 offset_sign = !minus;
946 offset = get_Const_tarval(cnst);
947 if (tarval_is_long(offset)) {
948 val = get_tarval_long(offset);
950 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
955 if (!check_immediate_constraint(val, immediate_constraint_type))
958 if (symconst != NULL) {
959 if (immediate_constraint_type != 0) {
960 /* we need full 32bits for symconsts */
964 /* unfortunately the assembler/linker doesn't support -symconst */
968 if (get_SymConst_kind(symconst) != symconst_addr_ent)
970 symconst_ent = get_SymConst_entity(symconst);
972 if (cnst == NULL && symconst == NULL)
975 if (offset_sign && offset != NULL) {
976 offset = tarval_neg(offset);
979 new_node = create_Immediate(symconst_ent, symconst_sign, val);