2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Matthias Braun, Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
35 #include "../betranshlp.h"
39 #include "ia32_architecture.h"
40 #include "ia32_common_transform.h"
41 #include "ia32_new_nodes.h"
43 #include "gen_ia32_new_nodes.h"
44 #include "gen_ia32_regalloc_if.h"
46 /** hold the current code generator during transformation */
47 ia32_code_gen_t *env_cg = NULL;
49 heights_t *heights = NULL;
51 static const arch_register_req_t no_register_req = {
52 arch_register_req_type_none,
54 NULL, /* limit bitset */
59 static int check_immediate_constraint(long val, char immediate_constraint_type)
61 switch (immediate_constraint_type) {
65 case 'I': return 0 <= val && val <= 31;
66 case 'J': return 0 <= val && val <= 63;
67 case 'K': return -128 <= val && val <= 127;
68 case 'L': return val == 0xff || val == 0xffff;
69 case 'M': return 0 <= val && val <= 3;
70 case 'N': return 0 <= val && val <= 255;
71 case 'O': return 0 <= val && val <= 127;
73 default: panic("Invalid immediate constraint found");
77 /* creates a unique ident by adding a number to a tag */
78 ident *ia32_unique_id(const char *tag)
80 static unsigned id = 0;
83 snprintf(str, sizeof(str), tag, ++id);
84 return new_id_from_str(str);
88 * Get a primitive type for a mode with alignment 16.
90 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
92 pmap_entry *e = pmap_find(types, mode);
96 res = new_type_primitive(mode);
97 if (get_mode_size_bits(mode) >= 80) {
98 set_type_alignment_bytes(res, 16);
100 pmap_insert(types, mode, res);
107 ir_entity *create_float_const_entity(ir_node *cnst)
109 ia32_isa_t *isa = env_cg->isa;
110 tarval *key = get_Const_tarval(cnst);
111 pmap_entry *e = pmap_find(isa->tv_ent, key);
117 ir_mode *mode = get_tarval_mode(tv);
120 if (! ia32_cg_config.use_sse2) {
121 /* try to reduce the mode to produce smaller sized entities */
122 if (mode != mode_F) {
123 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
125 tv = tarval_convert_to(tv, mode);
126 } else if (mode != mode_D) {
127 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
129 tv = tarval_convert_to(tv, mode);
135 if (mode == get_irn_mode(cnst)) {
136 /* mode was not changed */
137 tp = get_Const_type(cnst);
138 if (tp == firm_unknown_type)
139 tp = ia32_get_prim_type(isa->types, mode);
141 tp = ia32_get_prim_type(isa->types, mode);
143 res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
145 set_entity_ld_ident(res, get_entity_ident(res));
146 set_entity_visibility(res, ir_visibility_local);
147 add_entity_linkage(res, IR_LINKAGE_CONSTANT);
149 /* we create a new entity here: It's initialization must resist on the
151 rem = current_ir_graph;
152 current_ir_graph = get_const_code_irg();
153 set_atomic_ent_value(res, new_Const_type(tv, tp));
154 current_ir_graph = rem;
156 pmap_insert(isa->tv_ent, key, res);
164 ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
166 ir_graph *irg = current_ir_graph;
167 ir_node *start_block = get_irg_start_block(irg);
168 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
169 symconst_sign, no_pic_adjust, val);
170 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
175 const arch_register_t *ia32_get_clobber_register(const char *clobber)
177 const arch_register_t *reg = NULL;
180 const arch_register_class_t *cls;
182 /* TODO: construct a hashmap instead of doing linear search for clobber
184 for(c = 0; c < N_CLASSES; ++c) {
185 cls = & ia32_reg_classes[c];
186 for(r = 0; r < cls->n_regs; ++r) {
187 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
188 if (strcmp(temp_reg->name, clobber) == 0
189 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
201 int ia32_mode_needs_gp_reg(ir_mode *mode) {
202 if (mode == mode_fpcw)
204 if (get_mode_size_bits(mode) > 32)
206 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
209 static void parse_asm_constraints(constraint_t *constraint, const char *c,
212 char immediate_type = '\0';
213 unsigned limited = 0;
214 const arch_register_class_t *cls = NULL;
215 int memory_possible = 0;
216 int all_registers_allowed = 0;
220 memset(constraint, 0, sizeof(constraint[0]));
221 constraint->same_as = -1;
224 /* a memory constraint: no need to do anything in backend about it
225 * (the dependencies are already respected by the memory edge of
230 /* TODO: improve error messages with node and source info. (As users can
231 * easily hit these) */
239 /* Skip out/in-out marker */
249 while(*c != 0 && *c != ',')
254 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
255 cls = &ia32_reg_classes[CLASS_ia32_gp];
256 limited |= 1 << REG_EAX;
259 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
260 cls = &ia32_reg_classes[CLASS_ia32_gp];
261 limited |= 1 << REG_EBX;
264 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
265 cls = &ia32_reg_classes[CLASS_ia32_gp];
266 limited |= 1 << REG_ECX;
269 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
270 cls = &ia32_reg_classes[CLASS_ia32_gp];
271 limited |= 1 << REG_EDX;
274 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
275 cls = &ia32_reg_classes[CLASS_ia32_gp];
276 limited |= 1 << REG_EDI;
279 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
280 cls = &ia32_reg_classes[CLASS_ia32_gp];
281 limited |= 1 << REG_ESI;
285 /* q means lower part of the regs only, this makes no
286 * difference to Q for us (we only assign whole registers) */
287 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
288 cls = &ia32_reg_classes[CLASS_ia32_gp];
289 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
293 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
294 cls = &ia32_reg_classes[CLASS_ia32_gp];
295 limited |= 1 << REG_EAX | 1 << REG_EDX;
298 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
299 cls = &ia32_reg_classes[CLASS_ia32_gp];
300 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
301 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
308 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
309 panic("multiple register classes not supported");
310 cls = &ia32_reg_classes[CLASS_ia32_gp];
311 all_registers_allowed = 1;
317 /* TODO: mark values so the x87 simulator knows about t and u */
318 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
319 panic("multiple register classes not supported");
320 cls = &ia32_reg_classes[CLASS_ia32_vfp];
321 all_registers_allowed = 1;
326 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
327 panic("multiple register classes not supproted");
328 cls = &ia32_reg_classes[CLASS_ia32_xmm];
329 all_registers_allowed = 1;
339 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
340 panic("multiple register classes not supported");
341 if (immediate_type != '\0')
342 panic("multiple immediate types not supported");
343 cls = &ia32_reg_classes[CLASS_ia32_gp];
348 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
349 panic("multiple register classes not supported");
350 if (immediate_type != '\0')
351 panic("multiple immediate types not supported");
352 cls = &ia32_reg_classes[CLASS_ia32_gp];
353 immediate_type = 'i';
358 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
359 panic("multiple register classes not supported");
360 if (immediate_type != '\0')
361 panic("multiple immediate types not supported");
362 immediate_type = 'i';
363 cls = &ia32_reg_classes[CLASS_ia32_gp];
364 all_registers_allowed = 1;
379 panic("can only specify same constraint on input");
381 sscanf(c, "%d%n", &same_as, &p);
391 /* memory constraint no need to do anything in backend about it
392 * (the dependencies are already respected by the memory edge of
397 case 'E': /* no float consts yet */
398 case 'F': /* no float consts yet */
399 case 's': /* makes no sense on x86 */
400 case '<': /* no autodecrement on x86 */
401 case '>': /* no autoincrement on x86 */
402 case 'C': /* sse constant not supported yet */
403 case 'G': /* 80387 constant not supported yet */
404 case 'y': /* we don't support mmx registers yet */
405 case 'Z': /* not available in 32 bit mode */
406 case 'e': /* not available in 32 bit mode */
407 panic("unsupported asm constraint '%c' found in (%+F)",
408 *c, current_ir_graph);
411 panic("unknown asm constraint '%c' found in (%+F)", *c,
420 panic("same as and register constraint not supported");
421 if (immediate_type != '\0')
422 panic("same as and immediate constraint not supported");
425 if (cls == NULL && same_as < 0) {
426 if (!memory_possible)
427 panic("no constraint specified for assembler input");
430 constraint->same_as = same_as;
431 constraint->cls = cls;
432 constraint->allowed_registers = limited;
433 constraint->all_registers_allowed = all_registers_allowed;
434 constraint->memory_possible = memory_possible;
435 constraint->immediate_type = immediate_type;
438 static bool can_match(const arch_register_req_t *in,
439 const arch_register_req_t *out)
441 if (in->cls != out->cls)
443 if ( (in->type & arch_register_req_type_limited) == 0
444 || (out->type & arch_register_req_type_limited) == 0 )
447 return (*in->limited & *out->limited) != 0;
450 ir_node *gen_ASM(ir_node *node)
452 ir_node *block = NULL;
453 ir_node *new_block = NULL;
454 dbg_info *dbgi = get_irn_dbg_info(node);
460 int n_out_constraints;
462 const arch_register_req_t **out_reg_reqs;
463 const arch_register_req_t **in_reg_reqs;
464 ia32_asm_reg_t *register_map;
465 unsigned reg_map_size = 0;
466 struct obstack *obst;
467 const ir_asm_constraint *in_constraints;
468 const ir_asm_constraint *out_constraints;
470 int clobbers_flags = 0;
471 unsigned clobber_bits[N_CLASSES];
473 backend_info_t *info;
475 memset(&clobber_bits, 0, sizeof(clobber_bits));
477 switch (be_transformer) {
478 case TRANSFORMER_DEFAULT:
479 block = get_nodes_block(node);
480 new_block = be_transform_node(block);
484 case TRANSFORMER_PBQP:
485 case TRANSFORMER_RAND:
486 new_block = get_nodes_block(node);
491 panic("invalid transformer");
494 /* workaround for lots of buggy code out there as most people think volatile
495 * asm is enough for everything and forget the flags (linux kernel, etc.)
497 if (get_irn_pinned(node) == op_pin_state_pinned) {
501 arity = get_irn_arity(node);
502 in = ALLOCANZ(ir_node*, arity);
504 clobbers = get_ASM_clobbers(node);
506 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
507 const arch_register_req_t *req;
508 const char *c = get_id_str(clobbers[i]);
510 if (strcmp(c, "memory") == 0)
512 if (strcmp(c, "cc") == 0) {
517 req = parse_clobber(c);
518 clobber_bits[req->cls->index] |= *req->limited;
522 n_out_constraints = get_ASM_n_output_constraints(node);
523 out_arity = n_out_constraints + n_clobbers;
525 in_constraints = get_ASM_input_constraints(node);
526 out_constraints = get_ASM_output_constraints(node);
528 /* determine size of register_map */
529 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
530 const ir_asm_constraint *constraint = &out_constraints[out_idx];
531 if (constraint->pos > reg_map_size)
532 reg_map_size = constraint->pos;
534 for (i = 0; i < arity; ++i) {
535 const ir_asm_constraint *constraint = &in_constraints[i];
536 if (constraint->pos > reg_map_size)
537 reg_map_size = constraint->pos;
541 obst = get_irg_obstack(current_ir_graph);
542 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
543 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
545 /* construct output constraints */
546 out_size = out_arity + 1;
547 out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
549 for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
550 const ir_asm_constraint *constraint = &out_constraints[out_idx];
551 const char *c = get_id_str(constraint->constraint);
552 unsigned pos = constraint->pos;
553 constraint_t parsed_constraint;
554 const arch_register_req_t *req;
556 parse_asm_constraints(&parsed_constraint, c, 1);
557 req = make_register_req(&parsed_constraint, n_out_constraints,
558 out_reg_reqs, out_idx);
559 out_reg_reqs[out_idx] = req;
561 register_map[pos].use_input = 0;
562 register_map[pos].valid = 1;
563 register_map[pos].memory = 0;
564 register_map[pos].inout_pos = out_idx;
565 register_map[pos].mode = constraint->mode;
568 /* inputs + input constraints */
569 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
570 for (i = 0; i < arity; ++i) {
571 ir_node *pred = get_irn_n(node, i);
572 const ir_asm_constraint *constraint = &in_constraints[i];
573 ident *constr_id = constraint->constraint;
574 const char *c = get_id_str(constr_id);
575 unsigned pos = constraint->pos;
576 int is_memory_op = 0;
577 ir_node *input = NULL;
578 unsigned r_clobber_bits;
579 constraint_t parsed_constraint;
580 const arch_register_req_t *req;
582 parse_asm_constraints(&parsed_constraint, c, 0);
583 if (parsed_constraint.cls != NULL) {
584 r_clobber_bits = clobber_bits[parsed_constraint.cls->index];
585 if (r_clobber_bits != 0) {
586 if (parsed_constraint.all_registers_allowed) {
587 parsed_constraint.all_registers_allowed = 0;
588 be_abi_set_non_ignore_regs(env_cg->birg->abi,
589 parsed_constraint.cls,
590 &parsed_constraint.allowed_registers);
592 parsed_constraint.allowed_registers &= ~r_clobber_bits;
596 req = make_register_req(&parsed_constraint, n_out_constraints,
598 in_reg_reqs[i] = req;
600 if (parsed_constraint.immediate_type != '\0') {
601 char imm_type = parsed_constraint.immediate_type;
602 input = try_create_Immediate(pred, imm_type);
606 ir_node *pred = NULL;
607 switch (be_transformer) {
608 case TRANSFORMER_DEFAULT:
609 pred = get_irn_n(node, i);
610 input = be_transform_node(pred);
614 case TRANSFORMER_PBQP:
615 case TRANSFORMER_RAND:
616 input = get_irn_n(node, i);
620 default: panic("invalid transformer");
623 if (parsed_constraint.cls == NULL
624 && parsed_constraint.same_as < 0) {
626 } else if (parsed_constraint.memory_possible) {
627 /* TODO: match Load or Load/Store if memory possible is set */
632 register_map[pos].use_input = 1;
633 register_map[pos].valid = 1;
634 register_map[pos].memory = is_memory_op;
635 register_map[pos].inout_pos = i;
636 register_map[pos].mode = constraint->mode;
640 for (i = 0; i < get_ASM_n_clobbers(node); ++i) {
641 const char *c = get_id_str(clobbers[i]);
642 const arch_register_req_t *req;
644 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
647 req = parse_clobber(c);
648 out_reg_reqs[out_idx] = req;
652 /* Attempt to make ASM node register pressure faithful.
653 * (This does not work for complicated cases yet!)
655 * Algorithm: Check if there are fewer inputs or outputs (I will call this
656 * the smaller list). Then try to match each constraint of the smaller list
657 * to 1 of the other list. If we can't match it, then we have to add a dummy
658 * input/output to the other list
660 * FIXME: This is still broken in lots of cases. But at least better than
662 * FIXME: need to do this per register class...
664 if (out_arity <= arity) {
665 int orig_arity = arity;
668 bitset_t *used_ins = bitset_alloca(arity);
669 for (o = 0; o < out_arity; ++o) {
671 const arch_register_req_t *outreq = out_reg_reqs[o];
673 if (outreq->cls == NULL) {
677 for (i = 0; i < orig_arity; ++i) {
678 const arch_register_req_t *inreq;
679 if (bitset_is_set(used_ins, i))
681 inreq = in_reg_reqs[i];
682 if (!can_match(outreq, inreq))
684 bitset_set(used_ins, i);
687 /* did we find any match? */
691 /* we might need more space in the input arrays */
692 if (arity >= in_size) {
693 const arch_register_req_t **new_in_reg_reqs;
698 = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
699 memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
700 new_in = ALLOCANZ(ir_node*, in_size);
701 memcpy(new_in, in, arity*sizeof(new_in[0]));
703 in_reg_reqs = new_in_reg_reqs;
707 /* add a new (dummy) input which occupies the register */
708 assert(outreq->type & arch_register_req_type_limited);
709 in_reg_reqs[arity] = outreq;
710 in[arity] = new_bd_ia32_ProduceVal(NULL, block);
711 be_dep_on_frame(in[arity]);
716 bitset_t *used_outs = bitset_alloca(out_arity);
717 int orig_out_arity = out_arity;
718 for (i = 0; i < arity; ++i) {
720 const arch_register_req_t *inreq = in_reg_reqs[i];
722 if (inreq->cls == NULL) {
726 for (o = 0; o < orig_out_arity; ++o) {
727 const arch_register_req_t *outreq;
728 if (bitset_is_set(used_outs, o))
730 outreq = out_reg_reqs[o];
731 if (!can_match(outreq, inreq))
733 bitset_set(used_outs, i);
736 /* did we find any match? */
737 if (o < orig_out_arity)
740 /* we might need more space in the output arrays */
741 if (out_arity >= out_size) {
742 const arch_register_req_t **new_out_reg_reqs;
746 = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
747 memcpy(new_out_reg_reqs, out_reg_reqs,
748 out_arity * sizeof(new_out_reg_reqs[0]));
749 out_reg_reqs = new_out_reg_reqs;
752 /* add a new (dummy) output which occupies the register */
753 assert(inreq->type & arch_register_req_type_limited);
754 out_reg_reqs[out_arity] = inreq;
759 /* append none register requirement for the memory output */
760 if (out_arity + 1 >= out_size) {
761 const arch_register_req_t **new_out_reg_reqs;
763 out_size = out_arity + 1;
765 = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
766 memcpy(new_out_reg_reqs, out_reg_reqs,
767 out_arity * sizeof(new_out_reg_reqs[0]));
768 out_reg_reqs = new_out_reg_reqs;
771 /* add a new (dummy) output which occupies the register */
772 out_reg_reqs[out_arity] = arch_no_register_req;
775 new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
776 get_ASM_text(node), register_map);
779 be_dep_on_frame(new_node);
781 info = be_get_info(new_node);
782 for (i = 0; i < out_arity; ++i) {
783 info->out_infos[i].req = out_reg_reqs[i];
785 set_ia32_in_req_all(new_node, in_reg_reqs);
787 SET_IA32_ORIG_NODE(new_node, node);
792 ir_node *gen_CopyB(ir_node *node) {
793 ir_node *block = NULL;
795 ir_node *new_src = NULL;
797 ir_node *new_dst = NULL;
799 ir_node *new_mem = NULL;
801 dbg_info *dbgi = get_irn_dbg_info(node);
802 int size = get_type_size_bytes(get_CopyB_type(node));
805 switch (be_transformer) {
806 case TRANSFORMER_DEFAULT:
807 block = be_transform_node(get_nodes_block(node));
808 src = get_CopyB_src(node);
809 new_src = be_transform_node(src);
810 dst = get_CopyB_dst(node);
811 new_dst = be_transform_node(dst);
812 mem = get_CopyB_mem(node);
813 new_mem = be_transform_node(mem);
817 case TRANSFORMER_PBQP:
818 case TRANSFORMER_RAND:
819 block = get_nodes_block(node);
820 new_src = get_CopyB_src(node);
821 new_dst = get_CopyB_dst(node);
822 new_mem = get_CopyB_mem(node);
826 default: panic("invalid transformer");
829 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
830 /* then we need the size explicitly in ECX. */
831 if (size >= 32 * 4) {
832 rem = size & 0x3; /* size % 4 */
835 res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
836 be_dep_on_frame(res);
838 res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
841 ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n",
844 res = new_bd_ia32_CopyB_i(dbgi, block, new_dst, new_src, new_mem, size);
847 SET_IA32_ORIG_NODE(res, node);
852 ir_node *gen_Proj_tls(ir_node *node) {
853 ir_node *block = NULL;
854 dbg_info *dbgi = NULL;
857 switch (be_transformer) {
858 case TRANSFORMER_DEFAULT:
859 block = be_transform_node(get_nodes_block(node));
863 case TRANSFORMER_PBQP:
864 case TRANSFORMER_RAND:
865 block = get_nodes_block(node);
869 default: panic("invalid transformer");
872 res = new_bd_ia32_LdTls(dbgi, block, mode_Iu);
877 ir_node *gen_Unknown(ir_node *node)
879 ir_mode *mode = get_irn_mode(node);
881 if (mode_is_float(mode)) {
882 if (ia32_cg_config.use_sse2) {
883 return ia32_new_Unknown_xmm(env_cg);
885 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
886 ir_graph *irg = current_ir_graph;
887 dbg_info *dbgi = get_irn_dbg_info(node);
888 ir_node *block = get_irg_start_block(irg);
889 ir_node *ret = new_bd_ia32_vfldz(dbgi, block);
891 be_dep_on_frame(ret);
894 } else if (ia32_mode_needs_gp_reg(mode)) {
895 return ia32_new_Unknown_gp(env_cg);
897 panic("unsupported Unknown-Mode");
902 const arch_register_req_t *make_register_req(const constraint_t *constraint,
903 int n_outs, const arch_register_req_t **out_reqs, int pos)
905 struct obstack *obst = get_irg_obstack(current_ir_graph);
906 int same_as = constraint->same_as;
907 arch_register_req_t *req;
910 const arch_register_req_t *other_constr;
912 if (same_as >= n_outs)
913 panic("invalid output number in same_as constraint");
915 other_constr = out_reqs[same_as];
917 req = obstack_alloc(obst, sizeof(req[0]));
918 *req = *other_constr;
919 req->type |= arch_register_req_type_should_be_same;
920 req->other_same = 1U << pos;
922 /* switch constraints. This is because in firm we have same_as
923 * constraints on the output constraints while in the gcc asm syntax
924 * they are specified on the input constraints */
925 out_reqs[same_as] = req;
929 /* pure memory ops */
930 if (constraint->cls == NULL) {
931 return &no_register_req;
934 if (constraint->allowed_registers != 0
935 && !constraint->all_registers_allowed) {
936 unsigned *limited_ptr;
938 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
939 memset(req, 0, sizeof(req[0]));
940 limited_ptr = (unsigned*) (req+1);
942 req->type = arch_register_req_type_limited;
943 *limited_ptr = constraint->allowed_registers;
944 req->limited = limited_ptr;
946 req = obstack_alloc(obst, sizeof(req[0]));
947 memset(req, 0, sizeof(req[0]));
948 req->type = arch_register_req_type_normal;
950 req->cls = constraint->cls;
955 const arch_register_req_t *parse_clobber(const char *clobber)
957 struct obstack *obst = get_irg_obstack(current_ir_graph);
958 const arch_register_t *reg = ia32_get_clobber_register(clobber);
959 arch_register_req_t *req;
963 panic("Register '%s' mentioned in asm clobber is unknown", clobber);
966 assert(reg->index < 32);
968 limited = obstack_alloc(obst, sizeof(limited[0]));
969 *limited = 1 << reg->index;
971 req = obstack_alloc(obst, sizeof(req[0]));
972 memset(req, 0, sizeof(req[0]));
973 req->type = arch_register_req_type_limited;
974 req->cls = arch_register_get_class(reg);
975 req->limited = limited;
981 int prevents_AM(ir_node *const block, ir_node *const am_candidate,
982 ir_node *const other)
984 if (get_nodes_block(other) != block)
987 if (is_Sync(other)) {
990 for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) {
991 ir_node *const pred = get_Sync_pred(other, i);
993 if (get_nodes_block(pred) != block)
996 /* Do not block ourselves from getting eaten */
997 if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
1000 if (!heights_reachable_in_block(heights, pred, am_candidate))
1008 /* Do not block ourselves from getting eaten */
1009 if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
1012 if (!heights_reachable_in_block(heights, other, am_candidate))
1019 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
1022 tarval *offset = NULL;
1023 int offset_sign = 0;
1025 ir_entity *symconst_ent = NULL;
1026 int symconst_sign = 0;
1028 ir_node *cnst = NULL;
1029 ir_node *symconst = NULL;
1032 mode = get_irn_mode(node);
1033 if (!mode_is_int(mode) && !mode_is_reference(mode)) {
1037 if (is_Minus(node)) {
1039 node = get_Minus_op(node);
1042 if (is_Const(node)) {
1045 offset_sign = minus;
1046 } else if (is_SymConst(node)) {
1049 symconst_sign = minus;
1050 } else if (is_Add(node)) {
1051 ir_node *left = get_Add_left(node);
1052 ir_node *right = get_Add_right(node);
1053 if (is_Const(left) && is_SymConst(right)) {
1056 symconst_sign = minus;
1057 offset_sign = minus;
1058 } else if (is_SymConst(left) && is_Const(right)) {
1061 symconst_sign = minus;
1062 offset_sign = minus;
1064 } else if (is_Sub(node)) {
1065 ir_node *left = get_Sub_left(node);
1066 ir_node *right = get_Sub_right(node);
1067 if (is_Const(left) && is_SymConst(right)) {
1070 symconst_sign = !minus;
1071 offset_sign = minus;
1072 } else if (is_SymConst(left) && is_Const(right)) {
1075 symconst_sign = minus;
1076 offset_sign = !minus;
1083 offset = get_Const_tarval(cnst);
1084 if (tarval_is_long(offset)) {
1085 val = get_tarval_long(offset);
1087 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
1092 if (!check_immediate_constraint(val, immediate_constraint_type))
1095 if (symconst != NULL) {
1096 if (immediate_constraint_type != 0) {
1097 /* we need full 32bits for symconsts */
1101 /* unfortunately the assembler/linker doesn't support -symconst */
1105 if (get_SymConst_kind(symconst) != symconst_addr_ent)
1107 symconst_ent = get_SymConst_entity(symconst);
1109 if (cnst == NULL && symconst == NULL)
1112 if (offset_sign && offset != NULL) {
1113 offset = tarval_neg(offset);
1116 new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val);