2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the common parts of IR transformation from
23 * firm into ia32-Firm.
24 * @author Sebastian Buchwald
25 * @version $Id: ia32_common_transform.c 21012 2008-08-06 13:35:17Z beck $
34 #include "../betranshlp.h"
36 #include "ia32_architecture.h"
37 #include "ia32_common_transform.h"
38 #include "ia32_new_nodes.h"
40 #include "gen_ia32_new_nodes.h"
41 #include "gen_ia32_regalloc_if.h"
43 /** hold the current code generator during transformation */
44 ia32_code_gen_t *env_cg = NULL;
46 static const arch_register_req_t no_register_req = {
47 arch_register_req_type_none,
49 NULL, /* limit bitset */
54 static int check_immediate_constraint(long val, char immediate_constraint_type)
56 switch (immediate_constraint_type) {
60 case 'I': return 0 <= val && val <= 31;
61 case 'J': return 0 <= val && val <= 63;
62 case 'K': return -128 <= val && val <= 127;
63 case 'L': return val == 0xff || val == 0xffff;
64 case 'M': return 0 <= val && val <= 3;
65 case 'N': return 0 <= val && val <= 255;
66 case 'O': return 0 <= val && val <= 127;
68 default: panic("Invalid immediate constraint found");
73 * creates a unique ident by adding a number to a tag
75 * @param tag the tag string, must contain a %d if a number
78 static ident *unique_id(const char *tag)
80 static unsigned id = 0;
83 snprintf(str, sizeof(str), tag, ++id);
84 return new_id_from_str(str);
88 * Get a primitive type for a mode.
90 static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
92 pmap_entry *e = pmap_find(types, mode);
97 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
98 res = new_type_primitive(new_id_from_str(buf), mode);
99 set_type_alignment_bytes(res, 16);
100 pmap_insert(types, mode, res);
107 ir_entity *create_float_const_entity(ir_node *cnst)
109 ia32_isa_t *isa = env_cg->isa;
110 tarval *key = get_Const_tarval(cnst);
111 pmap_entry *e = pmap_find(isa->tv_ent, key);
117 ir_mode *mode = get_tarval_mode(tv);
120 if (! ia32_cg_config.use_sse2) {
121 /* try to reduce the mode to produce smaller sized entities */
122 if (mode != mode_F) {
123 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
125 tv = tarval_convert_to(tv, mode);
126 } else if (mode != mode_D) {
127 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
129 tv = tarval_convert_to(tv, mode);
135 if (mode == get_irn_mode(cnst)) {
136 /* mode was not changed */
137 tp = get_Const_type(cnst);
138 if (tp == firm_unknown_type)
139 tp = ia32_get_prim_type(isa->types, mode);
141 tp = ia32_get_prim_type(isa->types, mode);
143 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
145 set_entity_ld_ident(res, get_entity_ident(res));
146 set_entity_visibility(res, visibility_local);
147 set_entity_variability(res, variability_constant);
148 set_entity_allocation(res, allocation_static);
150 /* we create a new entity here: It's initialization must resist on the
152 rem = current_ir_graph;
153 current_ir_graph = get_const_code_irg();
154 set_atomic_ent_value(res, new_Const_type(tv, tp));
155 current_ir_graph = rem;
157 pmap_insert(isa->tv_ent, key, res);
165 ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
167 ir_graph *irg = current_ir_graph;
168 ir_node *start_block = get_irg_start_block(irg);
169 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
170 symconst, symconst_sign, val);
171 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
176 const arch_register_t *ia32_get_clobber_register(const char *clobber)
178 const arch_register_t *reg = NULL;
181 const arch_register_class_t *cls;
183 /* TODO: construct a hashmap instead of doing linear search for clobber
185 for(c = 0; c < N_CLASSES; ++c) {
186 cls = & ia32_reg_classes[c];
187 for(r = 0; r < cls->n_regs; ++r) {
188 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
189 if(strcmp(temp_reg->name, clobber) == 0
190 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
203 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
204 ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
206 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
207 obstack_1grow(isa->name_obst, 0);
208 return obstack_finish(isa->name_obst);
212 int ia32_mode_needs_gp_reg(ir_mode *mode) {
213 if(mode == mode_fpcw)
215 if(get_mode_size_bits(mode) > 32)
217 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
220 static void parse_asm_constraints(constraint_t *constraint, const char *c,
223 asm_constraint_flags_t flags = 0;
224 char immediate_type = '\0';
225 unsigned limited = 0;
226 const arch_register_class_t *cls = NULL;
227 int memory_possible = 0;
228 int all_registers_allowed = 0;
232 memset(constraint, 0, sizeof(constraint[0]));
233 constraint->same_as = -1;
236 /* a memory constraint: no need to do anything in backend about it
237 * (the dependencies are already respected by the memory edge of
242 /* TODO: improve error messages with node and source info. (As users can
243 * easily hit these) */
252 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
253 | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
257 flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
258 | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
265 while(*c != 0 && *c != ',')
270 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
271 cls = &ia32_reg_classes[CLASS_ia32_gp];
272 limited |= 1 << REG_EAX;
275 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
276 cls = &ia32_reg_classes[CLASS_ia32_gp];
277 limited |= 1 << REG_EBX;
280 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
281 cls = &ia32_reg_classes[CLASS_ia32_gp];
282 limited |= 1 << REG_ECX;
285 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
286 cls = &ia32_reg_classes[CLASS_ia32_gp];
287 limited |= 1 << REG_EDX;
290 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
291 cls = &ia32_reg_classes[CLASS_ia32_gp];
292 limited |= 1 << REG_EDI;
295 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
296 cls = &ia32_reg_classes[CLASS_ia32_gp];
297 limited |= 1 << REG_ESI;
301 /* q means lower part of the regs only, this makes no
302 * difference to Q for us (we only assign whole registers) */
303 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
304 cls = &ia32_reg_classes[CLASS_ia32_gp];
305 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
309 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
310 cls = &ia32_reg_classes[CLASS_ia32_gp];
311 limited |= 1 << REG_EAX | 1 << REG_EDX;
314 assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
315 cls = &ia32_reg_classes[CLASS_ia32_gp];
316 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
317 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
324 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
325 panic("multiple register classes not supported");
326 cls = &ia32_reg_classes[CLASS_ia32_gp];
327 all_registers_allowed = 1;
333 /* TODO: mark values so the x87 simulator knows about t and u */
334 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
335 panic("multiple register classes not supported");
336 cls = &ia32_reg_classes[CLASS_ia32_vfp];
337 all_registers_allowed = 1;
342 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
343 panic("multiple register classes not supproted");
344 cls = &ia32_reg_classes[CLASS_ia32_xmm];
345 all_registers_allowed = 1;
355 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
356 panic("multiple register classes not supported");
357 if (immediate_type != '\0')
358 panic("multiple immediate types not supported");
359 cls = &ia32_reg_classes[CLASS_ia32_gp];
364 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
365 panic("multiple register classes not supported");
366 if (immediate_type != '\0')
367 panic("multiple immediate types not supported");
368 cls = &ia32_reg_classes[CLASS_ia32_gp];
369 immediate_type = 'i';
374 if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
375 panic("multiple register classes not supported");
376 if (immediate_type != '\0')
377 panic("multiple immediate types not supported");
378 immediate_type = 'i';
379 cls = &ia32_reg_classes[CLASS_ia32_gp];
380 all_registers_allowed = 1;
395 panic("can only specify same constraint on input");
397 sscanf(c, "%d%n", &same_as, &p);
407 /* memory constraint no need to do anything in backend about it
408 * (the dependencies are already respected by the memory edge of
413 case 'E': /* no float consts yet */
414 case 'F': /* no float consts yet */
415 case 's': /* makes no sense on x86 */
416 case '<': /* no autodecrement on x86 */
417 case '>': /* no autoincrement on x86 */
418 case 'C': /* sse constant not supported yet */
419 case 'G': /* 80387 constant not supported yet */
420 case 'y': /* we don't support mmx registers yet */
421 case 'Z': /* not available in 32 bit mode */
422 case 'e': /* not available in 32 bit mode */
423 panic("unsupported asm constraint '%c' found in (%+F)",
424 *c, current_ir_graph);
427 panic("unknown asm constraint '%c' found in (%+F)", *c,
436 panic("same as and register constraint not supported");
437 if (immediate_type != '\0')
438 panic("same as and immediate constraint not supported");
441 if (cls == NULL && same_as < 0) {
442 if (!memory_possible)
443 panic("no constraint specified for assembler input");
446 constraint->same_as = same_as;
447 constraint->cls = cls;
448 constraint->allowed_registers = limited;
449 constraint->all_registers_allowed = all_registers_allowed;
450 constraint->memory_possible = memory_possible;
451 constraint->immediate_type = immediate_type;
454 ir_node *gen_ASM(ir_node *node)
456 ir_graph *irg = current_ir_graph;
457 ir_node *block = get_nodes_block(node);
458 ir_node *new_block = be_transform_node(block);
459 dbg_info *dbgi = get_irn_dbg_info(node);
465 int n_out_constraints;
467 const arch_register_req_t **out_reg_reqs;
468 const arch_register_req_t **in_reg_reqs;
469 ia32_asm_reg_t *register_map;
470 unsigned reg_map_size = 0;
471 struct obstack *obst;
472 const ir_asm_constraint *in_constraints;
473 const ir_asm_constraint *out_constraints;
475 int clobbers_flags = 0;
477 /* workaround for lots of buggy code out there as most people think volatile
478 * asm is enough for everything and forget the flags (linux kernel, etc.)
480 if (get_irn_pinned(node) == op_pin_state_pinned) {
484 arity = get_irn_arity(node);
485 in = alloca(arity * sizeof(in[0]));
486 memset(in, 0, arity * sizeof(in[0]));
488 clobbers = get_ASM_clobbers(node);
490 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
491 const char *c = get_id_str(clobbers[i]);
492 if (strcmp(c, "memory") == 0)
494 if (strcmp(c, "cc") == 0) {
500 n_out_constraints = get_ASM_n_output_constraints(node);
501 out_arity = n_out_constraints + n_clobbers;
503 in_constraints = get_ASM_input_constraints(node);
504 out_constraints = get_ASM_output_constraints(node);
506 /* determine size of register_map */
507 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
508 const ir_asm_constraint *constraint = &out_constraints[out_idx];
509 if (constraint->pos > reg_map_size)
510 reg_map_size = constraint->pos;
512 for(i = 0; i < arity; ++i) {
513 const ir_asm_constraint *constraint = &in_constraints[i];
514 if(constraint->pos > reg_map_size)
515 reg_map_size = constraint->pos;
519 obst = get_irg_obstack(irg);
520 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
521 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
523 /* construct output constraints */
524 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
526 for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
527 const ir_asm_constraint *constraint = &out_constraints[out_idx];
528 const char *c = get_id_str(constraint->constraint);
529 unsigned pos = constraint->pos;
530 constraint_t parsed_constraint;
531 const arch_register_req_t *req;
533 parse_asm_constraints(&parsed_constraint, c, 1);
534 req = make_register_req(&parsed_constraint, n_out_constraints,
535 out_reg_reqs, out_idx);
536 out_reg_reqs[out_idx] = req;
538 register_map[pos].use_input = 0;
539 register_map[pos].valid = 1;
540 register_map[pos].memory = 0;
541 register_map[pos].inout_pos = out_idx;
542 register_map[pos].mode = constraint->mode;
545 /* inputs + input constraints */
546 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
547 for(i = 0; i < arity; ++i) {
548 ir_node *pred = get_irn_n(node, i);
549 const ir_asm_constraint *constraint = &in_constraints[i];
550 ident *constr_id = constraint->constraint;
551 const char *c = get_id_str(constr_id);
552 unsigned pos = constraint->pos;
553 int is_memory_op = 0;
554 ir_node *input = NULL;
555 constraint_t parsed_constraint;
556 const arch_register_req_t *req;
558 parse_asm_constraints(&parsed_constraint, c, 0);
559 req = make_register_req(&parsed_constraint, n_out_constraints,
561 in_reg_reqs[i] = req;
563 if (parsed_constraint.immediate_type != '\0') {
564 char imm_type = parsed_constraint.immediate_type;
565 input = try_create_Immediate(pred, imm_type);
569 ir_node *pred = get_irn_n(node, i);
570 input = be_transform_node(pred);
572 if (parsed_constraint.cls == NULL
573 && parsed_constraint.same_as < 0) {
575 } else if(parsed_constraint.memory_possible) {
576 /* TODO: match Load or Load/Store if memory possible is set */
581 register_map[pos].use_input = 1;
582 register_map[pos].valid = 1;
583 register_map[pos].memory = is_memory_op;
584 register_map[pos].inout_pos = i;
585 register_map[pos].mode = constraint->mode;
589 for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
590 const char *c = get_id_str(clobbers[i]);
591 const arch_register_req_t *req;
593 if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
596 req = parse_clobber(c);
597 out_reg_reqs[out_idx] = req;
601 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
602 get_ASM_text(node), register_map);
604 set_ia32_out_req_all(new_node, out_reg_reqs);
605 set_ia32_in_req_all(new_node, in_reg_reqs);
607 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
612 ir_node *gen_Unknown(ir_node *node)
614 ir_mode *mode = get_irn_mode(node);
616 if (mode_is_float(mode)) {
617 if (ia32_cg_config.use_sse2) {
618 return ia32_new_Unknown_xmm(env_cg);
620 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
621 ir_graph *irg = current_ir_graph;
622 dbg_info *dbgi = get_irn_dbg_info(node);
623 ir_node *block = get_irg_start_block(irg);
624 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
626 /* Const Nodes before the initial IncSP are a bad idea, because
627 * they could be spilled and we have no SP ready at that point yet.
628 * So add a dependency to the initial frame pointer calculation to
629 * avoid that situation.
631 add_irn_dep(ret, get_irg_frame(irg));
634 } else if (ia32_mode_needs_gp_reg(mode)) {
635 return ia32_new_Unknown_gp(env_cg);
637 panic("unsupported Unknown-Mode");
642 const arch_register_req_t *make_register_req(const constraint_t *constraint,
643 int n_outs, const arch_register_req_t **out_reqs, int pos)
645 struct obstack *obst = get_irg_obstack(current_ir_graph);
646 int same_as = constraint->same_as;
647 arch_register_req_t *req;
650 const arch_register_req_t *other_constr;
652 if (same_as >= n_outs)
653 panic("invalid output number in same_as constraint");
655 other_constr = out_reqs[same_as];
657 req = obstack_alloc(obst, sizeof(req[0]));
658 req->cls = other_constr->cls;
659 req->type = arch_register_req_type_should_be_same;
661 req->other_same = 1U << pos;
662 req->other_different = 0;
664 /* switch constraints. This is because in firm we have same_as
665 * constraints on the output constraints while in the gcc asm syntax
666 * they are specified on the input constraints */
667 out_reqs[same_as] = req;
671 /* pure memory ops */
672 if (constraint->cls == NULL) {
673 return &no_register_req;
676 if (constraint->allowed_registers != 0
677 && !constraint->all_registers_allowed) {
678 unsigned *limited_ptr;
680 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
681 memset(req, 0, sizeof(req[0]));
682 limited_ptr = (unsigned*) (req+1);
684 req->type = arch_register_req_type_limited;
685 *limited_ptr = constraint->allowed_registers;
686 req->limited = limited_ptr;
688 req = obstack_alloc(obst, sizeof(req[0]));
689 memset(req, 0, sizeof(req[0]));
690 req->type = arch_register_req_type_normal;
692 req->cls = constraint->cls;
697 const arch_register_req_t *parse_clobber(const char *clobber)
699 struct obstack *obst = get_irg_obstack(current_ir_graph);
700 const arch_register_t *reg = ia32_get_clobber_register(clobber);
701 arch_register_req_t *req;
705 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
708 assert(reg->index < 32);
710 limited = obstack_alloc(obst, sizeof(limited[0]));
711 *limited = 1 << reg->index;
713 req = obstack_alloc(obst, sizeof(req[0]));
714 memset(req, 0, sizeof(req[0]));
715 req->type = arch_register_req_type_limited;
716 req->cls = arch_register_get_class(reg);
717 req->limited = limited;
722 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
725 tarval *offset = NULL;
728 ir_entity *symconst_ent = NULL;
729 int symconst_sign = 0;
731 ir_node *cnst = NULL;
732 ir_node *symconst = NULL;
735 mode = get_irn_mode(node);
736 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
742 node = get_Minus_op(node);
749 } else if(is_SymConst(node)) {
752 symconst_sign = minus;
753 } else if(is_Add(node)) {
754 ir_node *left = get_Add_left(node);
755 ir_node *right = get_Add_right(node);
756 if(is_Const(left) && is_SymConst(right)) {
759 symconst_sign = minus;
761 } else if(is_SymConst(left) && is_Const(right)) {
764 symconst_sign = minus;
767 } else if(is_Sub(node)) {
768 ir_node *left = get_Sub_left(node);
769 ir_node *right = get_Sub_right(node);
770 if(is_Const(left) && is_SymConst(right)) {
773 symconst_sign = !minus;
775 } else if(is_SymConst(left) && is_Const(right)) {
778 symconst_sign = minus;
779 offset_sign = !minus;
786 offset = get_Const_tarval(cnst);
787 if(tarval_is_long(offset)) {
788 val = get_tarval_long(offset);
790 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
795 if(!check_immediate_constraint(val, immediate_constraint_type))
798 if(symconst != NULL) {
799 if(immediate_constraint_type != 0) {
800 /* we need full 32bits for symconsts */
804 /* unfortunately the assembler/linker doesn't support -symconst */
808 if(get_SymConst_kind(symconst) != symconst_addr_ent)
810 symconst_ent = get_SymConst_entity(symconst);
812 if(cnst == NULL && symconst == NULL)
815 if(offset_sign && offset != NULL) {
816 offset = tarval_neg(offset);
819 new_node = create_Immediate(symconst_ent, symconst_sign, val);