2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
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9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
26 #ifndef FIRM_BE_IA32_ARCHITECTURE_H
27 #define FIRM_BE_IA32_ARCHITECTURE_H
30 /** optimize for size */
31 unsigned optimize_size:1;
32 /** use leave in function epilogue */
34 /** use inc, dec instead of add $1, reg and add $-1, reg */
35 unsigned use_incdec:1;
36 /** use sse2 instructions (instead of x87) */
38 /** use ffreep instead of fpop */
39 unsigned use_ffreep:1;
40 /** use ftst where possible */
42 /** use femms to pop all float registers */
44 /** use emms to pop all float registers */
46 /** use the fucomi instruction */
47 unsigned use_fucomi:1;
48 /** use cmovXX instructions */
50 /** mode_D moves instead of 2 integer moves */
51 unsigned use_modeD_moves:1;
52 /** use add esp, 4 instead of pop */
53 unsigned use_add_esp_4:1;
54 /** use add esp, 8 instead of 2 pops */
55 unsigned use_add_esp_8:1;
56 /** use sub esp, 4 instead of push */
57 unsigned use_sub_esp_4:1;
58 /** use sub esp, 8 instead of 2 pushs */
59 unsigned use_sub_esp_8:1;
60 /** use imul mem, imm32 instruction (slow on some CPUs) */
61 unsigned use_imul_mem_imm32:1;
62 /** use pxor instead xorps/xorpd */
64 /** use mov reg, 0 instruction */
66 /** use cwtl/cltd, which are shorter, to sign extend ax/eax */
67 unsigned use_short_sex_eax:1;
68 /** pad Ret instructions that are destination of conditional jump or directly preceded
69 by other jump instruction. */
70 unsigned use_pad_return:1;
71 /** use the bt instruction */
73 /** use fisttp instruction (requires SSE3) */
74 unsigned use_fisttp:1;
75 /** use SSE prefetch instructions */
76 unsigned use_sse_prefetch:1;
77 /** use 3DNow! prefetch instructions */
78 unsigned use_3dnow_prefetch:1;
79 /** use SSE4.2 or SSE4a popcnt instruction */
80 unsigned use_popcnt:1;
81 /** use i486 instructions */
83 /** optimize calling convention where possible */
84 unsigned optimize_cc:1;
86 * disrespect current floating point rounding mode at entry and exit of
87 * functions (this is ok for programs that don't explicitly change the
90 unsigned use_unsafe_floatconv:1;
91 /** emit machine code instead of assembler */
92 unsigned emit_machcode:1;
94 /** function alignment (a power of two in bytes) */
95 unsigned function_alignment;
96 /** alignment for labels (which are expected to be frequent jump targets) */
97 unsigned label_alignment;
98 /** maximum skip alignment for labels (which are expected to be frequent jump targets) */
99 unsigned label_alignment_max_skip;
100 /** if a blocks execfreq is factor higher than its predecessor then align
101 * the blocks label (0 switches off label alignment) */
102 double label_alignment_factor;
103 } ia32_code_gen_config_t;
105 extern ia32_code_gen_config_t ia32_cg_config;
107 /** Initialize the ia32 architecture module. */
108 void ia32_init_architecture(void);
110 /** Setup the ia32_cg_config structure by inspecting current user settings. */
111 void ia32_setup_cg_config(void);
114 * Evaluate the costs of an instruction. Used by the irach multiplication
117 * @param kind the instruction
118 * @param tv for MUL instruction, the multiplication constant
122 int ia32_evaluate_insn(insn_kind kind, tarval *tv);