2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
26 #ifndef FIRM_BE_IA32_ARCHITECTURE_H
27 #define FIRM_BE_IA32_ARCHITECTURE_H
30 /** optimize for size */
31 unsigned optimize_size:1;
32 /** use leave in function epilogue */
34 /** use inc, dec instead of add $1, reg and add $-1, reg */
35 unsigned use_incdec:1;
36 /** use soft float library */
37 unsigned use_softfloat:1;
38 /** use sse2 instructions (instead of x87) */
40 /** use ffreep instead of fpop */
41 unsigned use_ffreep:1;
42 /** use ftst where possible */
44 /** use femms to pop all float registers */
46 /** use emms to pop all float registers */
48 /** use the fucomi instruction */
49 unsigned use_fucomi:1;
50 /** use cmovXX instructions */
52 /** mode_D moves instead of 2 integer moves */
53 unsigned use_modeD_moves:1;
54 /** use add esp, 4 instead of pop */
55 unsigned use_add_esp_4:1;
56 /** use add esp, 8 instead of 2 pops */
57 unsigned use_add_esp_8:1;
58 /** use sub esp, 4 instead of push */
59 unsigned use_sub_esp_4:1;
60 /** use sub esp, 8 instead of 2 pushs */
61 unsigned use_sub_esp_8:1;
62 /** use imul mem, imm32 instruction (slow on some CPUs) */
63 unsigned use_imul_mem_imm32:1;
64 /** use pxor instead xorps/xorpd */
66 /** use mov reg, 0 instruction */
68 /** use cwtl/cltd, which are shorter, to sign extend ax/eax */
69 unsigned use_short_sex_eax:1;
70 /** pad Ret instructions that are destination of conditional jump or directly preceded
71 by other jump instruction. */
72 unsigned use_pad_return:1;
73 /** use the bt instruction */
75 /** use fisttp instruction (requires SSE3) */
76 unsigned use_fisttp:1;
77 /** use SSE prefetch instructions */
78 unsigned use_sse_prefetch:1;
79 /** use 3DNow! prefetch instructions */
80 unsigned use_3dnow_prefetch:1;
81 /** use SSE4.2 or SSE4a popcnt instruction */
82 unsigned use_popcnt:1;
83 /** use i486 instructions */
85 /** optimize calling convention where possible */
86 unsigned optimize_cc:1;
88 * disrespect current floating point rounding mode at entry and exit of
89 * functions (this is ok for programs that don't explicitly change the
92 unsigned use_unsafe_floatconv:1;
93 /** emit machine code instead of assembler */
94 unsigned emit_machcode:1;
96 /** function alignment (a power of two in bytes) */
97 unsigned function_alignment;
98 /** alignment for labels (which are expected to be frequent jump targets) */
99 unsigned label_alignment;
100 /** maximum skip alignment for labels (which are expected to be frequent jump targets) */
101 unsigned label_alignment_max_skip;
102 /** if a blocks execfreq is factor higher than its predecessor then align
103 * the blocks label (0 switches off label alignment) */
104 double label_alignment_factor;
105 } ia32_code_gen_config_t;
107 extern ia32_code_gen_config_t ia32_cg_config;
109 typedef enum ia32_fp_architectures {
110 IA32_FPU_ARCH_NONE = 0,
111 IA32_FPU_ARCH_X87 = 0x00000001,
112 IA32_FPU_ARCH_SSE2 = 0x00000002,
113 IA32_FPU_ARCH_SOFTFLOAT = 0x00000004,
115 ia32_fp_architectures;
117 /** Initialize the ia32 architecture module. */
118 void ia32_init_architecture(void);
120 /** Setup the ia32_cg_config structure by inspecting current user settings. */
121 void ia32_setup_cg_config(void);
124 * Evaluate the costs of an instruction. Used by the irach multiplication
127 * @param kind the instruction
128 * @param mode the mode of the instruction
129 * @param tv for MUL instruction, the multiplication constant
133 int ia32_evaluate_insn(insn_kind kind, const ir_mode *mode, ir_tarval *tv);