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15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
31 #include "lc_opts_enum.h"
35 #include "bearch_ia32_t.h"
36 #include "ia32_architecture.h"
38 ia32_code_gen_config_t ia32_cg_config;
41 * CPU architectures and features.
43 enum cpu_arch_features {
44 arch_generic32 = 0x00000001, /**< no specific architecture */
46 arch_i386 = 0x00000002, /**< i386 architecture */
47 arch_i486 = 0x00000004, /**< i486 architecture */
48 arch_pentium = 0x00000008, /**< Pentium architecture */
49 arch_ppro = 0x00000010, /**< PentiumPro architecture */
50 arch_netburst = 0x00000020, /**< Netburst architecture */
51 arch_nocona = 0x00000040, /**< Nocona architecture */
52 arch_core2 = 0x00000080, /**< Core2 architecture */
53 arch_atom = 0x00000100, /**< Atom architecture */
55 arch_k6 = 0x00000200, /**< k6 architecture */
56 arch_geode = 0x00000400, /**< Geode architecture */
57 arch_athlon = 0x00000800, /**< Athlon architecture */
58 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
59 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
61 arch_mask = 0x00003FFF,
63 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
64 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
66 arch_feature_mmx = 0x00004000, /**< MMX instructions */
67 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
68 arch_feature_sse1 = 0x00010000 | arch_feature_mmx, /**< SSE1 instructions, include MMX */
69 arch_feature_sse2 = 0x00020000 | arch_feature_sse1, /**< SSE2 instructions, include SSE1 */
70 arch_feature_sse3 = 0x00040000 | arch_feature_sse2, /**< SSE3 instructions, include SSE2 */
71 arch_feature_ssse3 = 0x00080000 | arch_feature_sse3, /**< SSSE3 instructions, include SSE3 */
72 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
73 arch_feature_3DNowE = 0x00200000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
74 arch_feature_64bit = 0x00400000 | arch_feature_sse2, /**< x86_64 support, includes SSE2 */
77 #define FLAGS(x, f) (((x) & (f)) != 0)
83 cpu_generic = arch_generic32,
88 cpu_pentium = arch_pentium,
89 cpu_pentium_mmx = arch_pentium | arch_feature_mmx,
90 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
91 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_feature_mmx,
92 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_feature_sse1,
93 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_feature_sse2,
94 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_feature_sse2,
95 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_feature_sse3,
96 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_feature_64bit | arch_feature_sse3,
97 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_feature_64bit | arch_feature_ssse3,
100 cpu_k6 = arch_k6 | arch_feature_mmx,
101 cpu_k6_PLUS = arch_k6 | arch_feature_mmx | arch_feature_3DNow,
102 cpu_geode = arch_geode | arch_feature_sse1 | arch_feature_3DNowE,
103 cpu_athlon = arch_athlon | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6_insn,
104 cpu_athlon64 = arch_athlon | arch_feature_sse2 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
105 cpu_k8 = arch_k8 | arch_feature_sse2 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
106 cpu_k8_sse3 = arch_k8 | arch_feature_sse3 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
107 cpu_k10 = arch_k10 | arch_feature_sse3 | arch_feature_3DNowE | arch_feature_p6_insn | arch_feature_64bit,
110 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
111 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
112 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
113 cpu_c3_2 = arch_ppro | arch_feature_sse1, /* really no 3DNow! */
116 static int opt_size = 0;
117 static cpu_support arch = cpu_generic;
118 static cpu_support opt_arch = cpu_core2;
119 static int use_sse2 = 0;
120 static int opt_cc = 1;
121 static int opt_unsafe_floatconv = 0;
123 /* instruction set architectures. */
124 static const lc_opt_enum_int_items_t arch_items[] = {
125 { "i386", cpu_i386 },
126 { "i486", cpu_i486 },
127 { "i586", cpu_pentium },
128 { "pentium", cpu_pentium },
129 { "pentium-mmx", cpu_pentium_mmx },
130 { "i686", cpu_pentium_pro },
131 { "pentiumpro", cpu_pentium_pro },
132 { "pentium2", cpu_pentium_2 },
133 { "p2", cpu_pentium_2 },
134 { "pentium3", cpu_pentium_3 },
135 { "pentium3m", cpu_pentium_3 },
136 { "p3", cpu_pentium_3 },
137 { "pentium-m", cpu_pentium_m },
138 { "pm", cpu_pentium_m },
139 { "pentium4", cpu_pentium_4 },
140 { "pentium4m", cpu_pentium_4 },
141 { "p4", cpu_pentium_4 },
142 { "prescott", cpu_prescott },
143 { "nocona", cpu_nocona },
144 { "merom", cpu_core2 },
145 { "core2", cpu_core2 },
148 { "k6-2", cpu_k6_PLUS },
149 { "k6-3", cpu_k6_PLUS },
150 { "geode", cpu_geode },
151 { "athlon", cpu_athlon },
152 { "athlon-tbird", cpu_athlon },
153 { "athlon-4", cpu_athlon },
154 { "athlon-xp", cpu_athlon },
155 { "athlon-mp", cpu_athlon },
156 { "athlon64", cpu_athlon64 },
158 { "opteron", cpu_k8 },
159 { "athlon-fx", cpu_k8 },
160 { "k8-sse3", cpu_k8_sse3 },
161 { "opteron-sse3", cpu_k8_sse3 },
163 { "barcelona", cpu_k10 },
164 { "amdfam10", cpu_k10 },
166 { "winchip-c6", cpu_winchip_c6, },
167 { "winchip2", cpu_winchip2 },
169 { "c3-2", cpu_c3_2 },
171 { "generic", cpu_generic },
172 { "generic32", cpu_generic },
176 static lc_opt_enum_int_var_t arch_var = {
177 (int*) &arch, arch_items
180 static lc_opt_enum_int_var_t opt_arch_var = {
181 (int*) &opt_arch, arch_items
184 static const lc_opt_enum_int_items_t fp_unit_items[] = {
190 static lc_opt_enum_int_var_t fp_unit_var = {
191 &use_sse2, fp_unit_items
194 static const lc_opt_table_entry_t ia32_architecture_options[] = {
195 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
196 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
198 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
200 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
202 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
204 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
205 "optimisations", &opt_unsafe_floatconv, 1),
209 typedef struct insn_const {
210 int add_cost; /**< cost of an add instruction */
211 int lea_cost; /**< cost of a lea instruction */
212 int const_shf_cost; /**< cost of a constant shift instruction */
213 int cost_mul_start; /**< starting cost of a multiply instruction */
214 int cost_mul_bit; /**< cost of multiply for every set bit */
215 unsigned function_alignment; /**< logarithm for alignment of function labels */
216 unsigned label_alignment; /**< logarithm for alignment of loops labels */
217 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
220 /* costs for optimizing for size */
221 static const insn_const size_cost = {
222 2, /* cost of an add instruction */
223 3, /* cost of a lea instruction */
224 3, /* cost of a constant shift instruction */
225 3, /* starting cost of a multiply instruction */
226 0, /* cost of multiply for every set bit */
227 0, /* logarithm for alignment of function labels */
228 0, /* logarithm for alignment of loops labels */
229 0, /* maximum skip for alignment of loops labels */
232 /* costs for the i386 */
233 static const insn_const i386_cost = {
234 1, /* cost of an add instruction */
235 1, /* cost of a lea instruction */
236 3, /* cost of a constant shift instruction */
237 9, /* starting cost of a multiply instruction */
238 1, /* cost of multiply for every set bit */
239 2, /* logarithm for alignment of function labels */
240 2, /* logarithm for alignment of loops labels */
241 3, /* maximum skip for alignment of loops labels */
244 /* costs for the i486 */
245 static const insn_const i486_cost = {
246 1, /* cost of an add instruction */
247 1, /* cost of a lea instruction */
248 2, /* cost of a constant shift instruction */
249 12, /* starting cost of a multiply instruction */
250 1, /* cost of multiply for every set bit */
251 4, /* logarithm for alignment of function labels */
252 4, /* logarithm for alignment of loops labels */
253 15, /* maximum skip for alignment of loops labels */
256 /* costs for the Pentium */
257 static const insn_const pentium_cost = {
258 1, /* cost of an add instruction */
259 1, /* cost of a lea instruction */
260 1, /* cost of a constant shift instruction */
261 11, /* starting cost of a multiply instruction */
262 0, /* cost of multiply for every set bit */
263 4, /* logarithm for alignment of function labels */
264 4, /* logarithm for alignment of loops labels */
265 7, /* maximum skip for alignment of loops labels */
268 /* costs for the Pentium Pro */
269 static const insn_const pentiumpro_cost = {
270 1, /* cost of an add instruction */
271 1, /* cost of a lea instruction */
272 1, /* cost of a constant shift instruction */
273 4, /* starting cost of a multiply instruction */
274 0, /* cost of multiply for every set bit */
275 4, /* logarithm for alignment of function labels */
276 4, /* logarithm for alignment of loops labels */
277 10, /* maximum skip for alignment of loops labels */
280 /* costs for the K6 */
281 static const insn_const k6_cost = {
282 1, /* cost of an add instruction */
283 2, /* cost of a lea instruction */
284 1, /* cost of a constant shift instruction */
285 3, /* starting cost of a multiply instruction */
286 0, /* cost of multiply for every set bit */
287 5, /* logarithm for alignment of function labels */
288 5, /* logarithm for alignment of loops labels */
289 7, /* maximum skip for alignment of loops labels */
292 /* costs for the Geode */
293 static const insn_const geode_cost = {
294 1, /* cost of an add instruction */
295 1, /* cost of a lea instruction */
296 1, /* cost of a constant shift instruction */
297 7, /* starting cost of a multiply instruction */
298 0, /* cost of multiply for every set bit */
299 0, /* logarithm for alignment of function labels */
300 0, /* logarithm for alignment of loops labels */
301 0, /* maximum skip for alignment of loops labels */
304 /* costs for the Athlon */
305 static const insn_const athlon_cost = {
306 1, /* cost of an add instruction */
307 2, /* cost of a lea instruction */
308 1, /* cost of a constant shift instruction */
309 5, /* starting cost of a multiply instruction */
310 0, /* cost of multiply for every set bit */
311 4, /* logarithm for alignment of function labels */
312 4, /* logarithm for alignment of loops labels */
313 7, /* maximum skip for alignment of loops labels */
316 /* costs for the Opteron/K8/K10 */
317 static const insn_const k8_cost = {
318 1, /* cost of an add instruction */
319 2, /* cost of a lea instruction */
320 1, /* cost of a constant shift instruction */
321 3, /* starting cost of a multiply instruction */
322 0, /* cost of multiply for every set bit */
323 4, /* logarithm for alignment of function labels */
324 4, /* logarithm for alignment of loops labels */
325 7, /* maximum skip for alignment of loops labels */
328 /* costs for the K10 */
329 static const insn_const k10_cost = {
330 1, /* cost of an add instruction */
331 2, /* cost of a lea instruction */
332 1, /* cost of a constant shift instruction */
333 3, /* starting cost of a multiply instruction */
334 0, /* cost of multiply for every set bit */
335 5, /* logarithm for alignment of function labels */
336 5, /* logarithm for alignment of loops labels */
337 7, /* maximum skip for alignment of loops labels */
340 /* costs for the Pentium 4 */
341 static const insn_const netburst_cost = {
342 1, /* cost of an add instruction */
343 3, /* cost of a lea instruction */
344 4, /* cost of a constant shift instruction */
345 15, /* starting cost of a multiply instruction */
346 0, /* cost of multiply for every set bit */
347 4, /* logarithm for alignment of function labels */
348 4, /* logarithm for alignment of loops labels */
349 7, /* maximum skip for alignment of loops labels */
352 /* costs for the Nocona and Core */
353 static const insn_const nocona_cost = {
354 1, /* cost of an add instruction */
355 1, /* cost of a lea instruction */
356 1, /* cost of a constant shift instruction */
357 10, /* starting cost of a multiply instruction */
358 0, /* cost of multiply for every set bit */
359 4, /* logarithm for alignment of function labels */
360 4, /* logarithm for alignment of loops labels */
361 7, /* maximum skip for alignment of loops labels */
364 /* costs for the Core2 */
365 static const insn_const core2_cost = {
366 1, /* cost of an add instruction */
367 1, /* cost of a lea instruction */
368 1, /* cost of a constant shift instruction */
369 3, /* starting cost of a multiply instruction */
370 0, /* cost of multiply for every set bit */
371 4, /* logarithm for alignment of function labels */
372 4, /* logarithm for alignment of loops labels */
373 10, /* maximum skip for alignment of loops labels */
376 /* costs for the generic32 */
377 static const insn_const generic32_cost = {
378 1, /* cost of an add instruction */
379 2, /* cost of a lea instruction */
380 1, /* cost of a constant shift instruction */
381 4, /* starting cost of a multiply instruction */
382 0, /* cost of multiply for every set bit */
383 4, /* logarithm for alignment of function labels */
384 4, /* logarithm for alignment of loops labels */
385 7, /* maximum skip for alignment of loops labels */
388 static const insn_const *arch_costs = &generic32_cost;
390 static void set_arch_costs(void)
393 arch_costs = &size_cost;
396 switch (opt_arch & arch_mask) {
398 arch_costs = &i386_cost;
401 arch_costs = &i486_cost;
404 arch_costs = &pentium_cost;
407 arch_costs = &pentiumpro_cost;
410 arch_costs = &netburst_cost;
413 arch_costs = &nocona_cost;
416 arch_costs = &core2_cost;
419 arch_costs = &k6_cost;
422 arch_costs = &geode_cost;
425 arch_costs = &athlon_cost;
428 arch_costs = &k8_cost;
431 arch_costs = &k10_cost;
435 arch_costs = &generic32_cost;
440 * Evaluate a given simple instruction.
442 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
447 cost = arch_costs->cost_mul_start;
448 if (arch_costs->cost_mul_bit > 0) {
449 char *bitstr = get_tarval_bitpattern(tv);
452 for (i = 0; bitstr[i] != '\0'; ++i) {
453 if (bitstr[i] == '1') {
454 cost += arch_costs->cost_mul_bit;
461 return arch_costs->lea_cost;
464 return arch_costs->add_cost;
466 return arch_costs->const_shf_cost;
468 return arch_costs->add_cost;
474 void ia32_setup_cg_config(void)
476 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
480 ia32_cg_config.optimize_size = opt_size != 0;
481 /* on newer intel cpus mov, pop is often faster then leave although it has a
483 ia32_cg_config.use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2);
484 /* P4s don't like inc/decs because they only partially write the flags
485 register which produces false dependencies */
486 ia32_cg_config.use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_geode) || opt_size;
487 ia32_cg_config.use_sse2 = use_sse2;
488 ia32_cg_config.use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
489 ia32_cg_config.use_ftst = !FLAGS(arch, arch_feature_p6_insn);
490 ia32_cg_config.use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
491 FLAGS(arch, arch_feature_mmx | arch_all_amd);
492 ia32_cg_config.use_fucomi = FLAGS(arch, arch_feature_p6_insn);
493 ia32_cg_config.use_cmov = FLAGS(arch, arch_feature_p6_insn);
494 ia32_cg_config.use_modeD_moves = FLAGS(opt_arch, arch_athlon_plus | arch_geode | arch_ppro |
495 arch_netburst | arch_nocona | arch_core2 | arch_generic32);
496 ia32_cg_config.use_add_esp_4 = FLAGS(opt_arch, arch_geode | arch_athlon_plus |
497 arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
499 ia32_cg_config.use_add_esp_8 = FLAGS(opt_arch, arch_geode | arch_athlon_plus |
500 arch_i386 | arch_i486 | arch_ppro | arch_netburst |
501 arch_nocona | arch_core2 | arch_generic32) &&
503 ia32_cg_config.use_sub_esp_4 = FLAGS(opt_arch, arch_athlon_plus | arch_ppro |
504 arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
506 ia32_cg_config.use_sub_esp_8 = FLAGS(opt_arch, arch_athlon_plus | arch_i386 | arch_i486 |
507 arch_ppro | arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
509 ia32_cg_config.use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
510 ia32_cg_config.use_pxor = FLAGS(opt_arch, arch_netburst);
511 ia32_cg_config.use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
512 ia32_cg_config.use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
513 ia32_cg_config.use_bt = FLAGS(opt_arch, arch_core2) || opt_size;
514 ia32_cg_config.optimize_cc = opt_cc;
515 ia32_cg_config.use_unsafe_floatconv = opt_unsafe_floatconv;
517 ia32_cg_config.function_alignment = arch_costs->function_alignment;
518 ia32_cg_config.label_alignment = arch_costs->label_alignment;
519 ia32_cg_config.label_alignment_max_skip = arch_costs->label_alignment_max_skip;
521 if (opt_arch & (arch_i386 | arch_i486)) {
522 ia32_cg_config.label_alignment_factor = 0;
523 } else if (opt_arch & arch_all_amd) {
524 ia32_cg_config.label_alignment_factor = 3;
526 ia32_cg_config.label_alignment_factor = 2;
530 void ia32_init_architecture(void)
532 lc_opt_entry_t *be_grp, *ia32_grp;
534 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
536 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
537 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
539 lc_opt_add_table(ia32_grp, ia32_architecture_options);