2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
29 #include "lc_opts_enum.h"
33 #include "bearch_ia32_t.h"
34 #include "ia32_architecture.h"
36 ia32_code_gen_config_t ia32_cg_config;
39 * CPU architectures and features.
41 enum cpu_arch_features {
42 arch_generic32 = 0x00000001, /**< no specific architecture */
44 arch_i386 = 0x00000002, /**< i386 architecture */
45 arch_i486 = 0x00000004, /**< i486 architecture */
46 arch_pentium = 0x00000008, /**< Pentium architecture */
47 arch_ppro = 0x00000010, /**< PentiumPro architecture */
48 arch_netburst = 0x00000020, /**< Netburst architecture */
49 arch_nocona = 0x00000040, /**< Nocona architecture */
50 arch_core2 = 0x00000080, /**< Core2 architecture */
51 arch_atom = 0x00000100, /**< Atom architecture */
53 arch_k6 = 0x00000200, /**< k6 architecture */
54 arch_geode = 0x00000400, /**< Geode architecture */
55 arch_athlon = 0x00000800, /**< Athlon architecture */
56 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
57 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
59 arch_mask = 0x00003FFF,
61 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
62 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
64 arch_feature_mmx = 0x00004000, /**< MMX instructions */
65 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
66 arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
67 arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
68 arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
69 arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
70 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
71 arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
72 arch_feature_64bit = 0x00400000, /**< x86_64 support */
73 arch_feature_sse4_1 = 0x00800000, /**< SSE4.1 instructions */
74 arch_feature_sse4_2 = 0x01000000, /**< SSE4.2 instructions */
75 arch_feature_sse4a = 0x02000000, /**< SSE4a instructions */
77 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
78 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
79 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
80 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
81 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
82 arch_sse4_1_insn = arch_feature_sse4_1 | arch_ssse3_insn, /**< SSE4.1 instructions, include SSSE3 */
83 arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */
84 arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */
86 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
87 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
88 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
91 #define FLAGS(x, f) (((x) & (f)) != 0)
96 typedef enum cpu_support {
97 cpu_generic = arch_generic32,
100 cpu_i386 = arch_i386,
101 cpu_i486 = arch_i486,
102 cpu_pentium = arch_pentium,
103 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
104 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
105 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
106 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
107 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
108 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
109 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
110 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
111 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
112 cpu_penryn = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
115 cpu_k6 = arch_k6 | arch_mmx_insn,
116 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
117 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
118 cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_p6_insn,
119 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
120 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
121 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
122 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
123 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse4a_insn,
126 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
127 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
128 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
129 cpu_c3_2 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */
134 static int opt_size = 0;
135 static int emit_machcode = 0;
136 static cpu_support arch = cpu_generic;
137 static cpu_support opt_arch = cpu_generic;
138 static int use_sse2 = 0;
139 static int opt_cc = 1;
140 static int opt_unsafe_floatconv = 0;
142 /* instruction set architectures. */
143 static const lc_opt_enum_int_items_t arch_items[] = {
144 { "i386", cpu_i386 },
145 { "i486", cpu_i486 },
146 { "i586", cpu_pentium },
147 { "pentium", cpu_pentium },
148 { "pentium-mmx", cpu_pentium_mmx },
149 { "i686", cpu_pentium_pro },
150 { "pentiumpro", cpu_pentium_pro },
151 { "pentium2", cpu_pentium_2 },
152 { "p2", cpu_pentium_2 },
153 { "pentium3", cpu_pentium_3 },
154 { "pentium3m", cpu_pentium_3 },
155 { "p3", cpu_pentium_3 },
156 { "pentium-m", cpu_pentium_m },
157 { "pm", cpu_pentium_m },
158 { "pentium4", cpu_pentium_4 },
159 { "pentium4m", cpu_pentium_4 },
160 { "p4", cpu_pentium_4 },
161 { "prescott", cpu_prescott },
162 { "nocona", cpu_nocona },
163 { "merom", cpu_core2 },
164 { "core2", cpu_core2 },
165 { "penryn", cpu_penryn },
168 { "k6-2", cpu_k6_PLUS },
169 { "k6-3", cpu_k6_PLUS },
170 { "geode", cpu_geode },
171 { "athlon", cpu_athlon_old },
172 { "athlon-tbird", cpu_athlon },
173 { "athlon-4", cpu_athlon },
174 { "athlon-xp", cpu_athlon },
175 { "athlon-mp", cpu_athlon },
176 { "athlon64", cpu_athlon64 },
178 { "opteron", cpu_k8 },
179 { "athlon-fx", cpu_k8 },
180 { "k8-sse3", cpu_k8_sse3 },
181 { "opteron-sse3", cpu_k8_sse3 },
183 { "barcelona", cpu_k10 },
184 { "amdfam10", cpu_k10 },
186 { "winchip-c6", cpu_winchip_c6, },
187 { "winchip2", cpu_winchip2 },
189 { "c3-2", cpu_c3_2 },
191 { "generic", cpu_generic },
192 { "generic32", cpu_generic },
194 { "native", cpu_autodetect },
198 static lc_opt_enum_int_var_t arch_var = {
199 (int*) &arch, arch_items
202 static lc_opt_enum_int_var_t opt_arch_var = {
203 (int*) &opt_arch, arch_items
206 static const lc_opt_enum_int_items_t fp_unit_items[] = {
212 static lc_opt_enum_int_var_t fp_unit_var = {
213 &use_sse2, fp_unit_items
216 static const lc_opt_table_entry_t ia32_architecture_options[] = {
217 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
218 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
220 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
222 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
224 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
226 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
227 "optimisations", &opt_unsafe_floatconv, 1),
228 LC_OPT_ENT_BOOL("machcode", "output machine code instead of assembler",
233 typedef struct insn_const {
234 int add_cost; /**< cost of an add instruction */
235 int lea_cost; /**< cost of a lea instruction */
236 int const_shf_cost; /**< cost of a constant shift instruction */
237 int cost_mul_start; /**< starting cost of a multiply instruction */
238 int cost_mul_bit; /**< cost of multiply for every set bit */
239 unsigned function_alignment; /**< logarithm for alignment of function labels */
240 unsigned label_alignment; /**< logarithm for alignment of loops labels */
241 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
244 /* costs for optimizing for size */
245 static const insn_const size_cost = {
246 2, /* cost of an add instruction */
247 3, /* cost of a lea instruction */
248 3, /* cost of a constant shift instruction */
249 4, /* starting cost of a multiply instruction */
250 0, /* cost of multiply for every set bit */
251 0, /* logarithm for alignment of function labels */
252 0, /* logarithm for alignment of loops labels */
253 0, /* maximum skip for alignment of loops labels */
256 /* costs for the i386 */
257 static const insn_const i386_cost = {
258 1, /* cost of an add instruction */
259 1, /* cost of a lea instruction */
260 3, /* cost of a constant shift instruction */
261 9, /* starting cost of a multiply instruction */
262 1, /* cost of multiply for every set bit */
263 2, /* logarithm for alignment of function labels */
264 2, /* logarithm for alignment of loops labels */
265 3, /* maximum skip for alignment of loops labels */
268 /* costs for the i486 */
269 static const insn_const i486_cost = {
270 1, /* cost of an add instruction */
271 1, /* cost of a lea instruction */
272 2, /* cost of a constant shift instruction */
273 12, /* starting cost of a multiply instruction */
274 1, /* cost of multiply for every set bit */
275 4, /* logarithm for alignment of function labels */
276 4, /* logarithm for alignment of loops labels */
277 15, /* maximum skip for alignment of loops labels */
280 /* costs for the Pentium */
281 static const insn_const pentium_cost = {
282 1, /* cost of an add instruction */
283 1, /* cost of a lea instruction */
284 1, /* cost of a constant shift instruction */
285 11, /* starting cost of a multiply instruction */
286 0, /* cost of multiply for every set bit */
287 4, /* logarithm for alignment of function labels */
288 4, /* logarithm for alignment of loops labels */
289 7, /* maximum skip for alignment of loops labels */
292 /* costs for the Pentium Pro */
293 static const insn_const pentiumpro_cost = {
294 1, /* cost of an add instruction */
295 1, /* cost of a lea instruction */
296 1, /* cost of a constant shift instruction */
297 4, /* starting cost of a multiply instruction */
298 0, /* cost of multiply for every set bit */
299 4, /* logarithm for alignment of function labels */
300 4, /* logarithm for alignment of loops labels */
301 10, /* maximum skip for alignment of loops labels */
304 /* costs for the K6 */
305 static const insn_const k6_cost = {
306 1, /* cost of an add instruction */
307 2, /* cost of a lea instruction */
308 1, /* cost of a constant shift instruction */
309 3, /* starting cost of a multiply instruction */
310 0, /* cost of multiply for every set bit */
311 5, /* logarithm for alignment of function labels */
312 5, /* logarithm for alignment of loops labels */
313 7, /* maximum skip for alignment of loops labels */
316 /* costs for the Geode */
317 static const insn_const geode_cost = {
318 1, /* cost of an add instruction */
319 1, /* cost of a lea instruction */
320 1, /* cost of a constant shift instruction */
321 7, /* starting cost of a multiply instruction */
322 0, /* cost of multiply for every set bit */
323 0, /* logarithm for alignment of function labels */
324 0, /* logarithm for alignment of loops labels */
325 0, /* maximum skip for alignment of loops labels */
328 /* costs for the Athlon */
329 static const insn_const athlon_cost = {
330 1, /* cost of an add instruction */
331 2, /* cost of a lea instruction */
332 1, /* cost of a constant shift instruction */
333 5, /* starting cost of a multiply instruction */
334 0, /* cost of multiply for every set bit */
335 4, /* logarithm for alignment of function labels */
336 4, /* logarithm for alignment of loops labels */
337 7, /* maximum skip for alignment of loops labels */
340 /* costs for the Opteron/K8 */
341 static const insn_const k8_cost = {
342 1, /* cost of an add instruction */
343 2, /* cost of a lea instruction */
344 1, /* cost of a constant shift instruction */
345 3, /* starting cost of a multiply instruction */
346 0, /* cost of multiply for every set bit */
348 4, /* logarithm for alignment of function labels */
349 4, /* logarithm for alignment of loops labels */
350 7, /* maximum skip for alignment of loops labels */
358 /* costs for the K10 */
359 static const insn_const k10_cost = {
360 1, /* cost of an add instruction */
361 2, /* cost of a lea instruction */
362 1, /* cost of a constant shift instruction */
363 3, /* starting cost of a multiply instruction */
364 0, /* cost of multiply for every set bit */
365 5, /* logarithm for alignment of function labels */
366 5, /* logarithm for alignment of loops labels */
367 7, /* maximum skip for alignment of loops labels */
370 /* costs for the Pentium 4 */
371 static const insn_const netburst_cost = {
372 1, /* cost of an add instruction */
373 3, /* cost of a lea instruction */
374 4, /* cost of a constant shift instruction */
375 15, /* starting cost of a multiply instruction */
376 0, /* cost of multiply for every set bit */
377 4, /* logarithm for alignment of function labels */
378 4, /* logarithm for alignment of loops labels */
379 7, /* maximum skip for alignment of loops labels */
382 /* costs for the Nocona and Core */
383 static const insn_const nocona_cost = {
384 1, /* cost of an add instruction */
385 1, /* cost of a lea instruction */
386 1, /* cost of a constant shift instruction */
387 10, /* starting cost of a multiply instruction */
388 0, /* cost of multiply for every set bit */
389 4, /* logarithm for alignment of function labels */
390 4, /* logarithm for alignment of loops labels */
391 7, /* maximum skip for alignment of loops labels */
394 /* costs for the Core2 */
395 static const insn_const core2_cost = {
396 1, /* cost of an add instruction */
397 1, /* cost of a lea instruction */
398 1, /* cost of a constant shift instruction */
399 3, /* starting cost of a multiply instruction */
400 0, /* cost of multiply for every set bit */
401 4, /* logarithm for alignment of function labels */
402 4, /* logarithm for alignment of loops labels */
403 10, /* maximum skip for alignment of loops labels */
406 /* costs for the generic32 */
407 static const insn_const generic32_cost = {
408 1, /* cost of an add instruction */
409 2, /* cost of a lea instruction */
410 1, /* cost of a constant shift instruction */
411 4, /* starting cost of a multiply instruction */
412 0, /* cost of multiply for every set bit */
413 4, /* logarithm for alignment of function labels */
414 4, /* logarithm for alignment of loops labels */
415 7, /* maximum skip for alignment of loops labels */
418 static const insn_const *arch_costs = &generic32_cost;
420 static void set_arch_costs(void)
423 arch_costs = &size_cost;
426 switch (opt_arch & arch_mask) {
427 case arch_i386: arch_costs = &i386_cost; break;
428 case arch_i486: arch_costs = &i486_cost; break;
429 case arch_pentium: arch_costs = &pentium_cost; break;
430 case arch_ppro: arch_costs = &pentiumpro_cost; break;
431 case arch_netburst: arch_costs = &netburst_cost; break;
432 case arch_nocona: arch_costs = &nocona_cost; break;
433 case arch_core2: arch_costs = &core2_cost; break;
434 case arch_k6: arch_costs = &k6_cost; break;
435 case arch_geode: arch_costs = &geode_cost; break;
436 case arch_athlon: arch_costs = &athlon_cost; break;
437 case arch_k8: arch_costs = &k8_cost; break;
438 case arch_k10: arch_costs = &k10_cost; break;
440 case arch_generic32: arch_costs = &generic32_cost; break;
444 /* Evaluate the costs of an instruction. */
445 int ia32_evaluate_insn(insn_kind kind, const ir_mode *mode, ir_tarval *tv)
451 cost = arch_costs->cost_mul_start;
452 if (arch_costs->cost_mul_bit > 0) {
453 char *bitstr = get_tarval_bitpattern(tv);
456 for (i = 0; bitstr[i] != '\0'; ++i) {
457 if (bitstr[i] == '1') {
458 cost += arch_costs->cost_mul_bit;
463 if (get_mode_size_bits(mode) <= 32)
465 /* 64bit mul supported, approx 4times of a 32bit mul*/
468 /* lea is only supported for 32 bit */
469 if (get_mode_size_bits(mode) <= 32)
470 return arch_costs->lea_cost;
471 /* in 64bit mode, the Lea cost are at wort 2 shifts and one add */
472 return 2 * arch_costs->add_cost + 2 * (2 * arch_costs->const_shf_cost);
475 if (get_mode_size_bits(mode) <= 32)
476 return arch_costs->add_cost;
477 /* 64bit add/sub supported, double the cost */
478 return 2 * arch_costs->add_cost;
480 if (get_mode_size_bits(mode) <= 32)
481 return arch_costs->const_shf_cost;
482 /* 64bit shift supported, double the cost */
483 return 2 * arch_costs->const_shf_cost;
485 return arch_costs->add_cost;
491 static struct cpu_info_t {
497 unsigned edx_features;
498 unsigned ecx_features;
500 static void auto_detect_Intel(struct cpu_info_t info);
501 static void auto_detect_AMD(struct cpu_info_t info);
503 static void autodetect_arch() {
504 /* We use the cpuid instruction to detect the CPU features */
506 /* If bit 21 of the EFLAGS register can be changed, the cpuid instruction is available */
507 unsigned eflags_before;
508 unsigned eflags_after;
513 "xorl $0x00200000, %1\n\t"
518 : "=r" (eflags_before), "=r" (eflags_after) :: "cc"
520 if (eflags_before == eflags_after) {
521 panic("arch autodetection impossible: no cpuid instruction available");
524 unsigned highest_calling_parameter, vid0, vid1, vid2;
527 "xorl %%eax, %%eax\n\t" // 0 in eax for vendor ID
529 : "=a" (highest_calling_parameter), "=b" (vid0), "=d" (vid1), "=c" (vid2)
532 int vendorid[4] = {vid0, vid1, vid2, 0};
534 unsigned cpu_signature, edx_features, ecx_features, add_feature_flags;
536 "movl $1, %%eax\n\t" // 1 in eax for processor info and feature bits
538 : "=a" (cpu_signature), "=b" (add_feature_flags), "=d" (ecx_features), "=c" (edx_features)
541 struct cpu_info_t cpu_info = {
542 (cpu_signature >> 4) & ((1<<4)-1),
543 (cpu_signature >> 8) & ((1<<4)-1),
544 (cpu_signature >> 12) & ((1<<2)-1),
545 (cpu_signature >> 16) & ((1<<4)-1),
546 (cpu_signature >> 20) & ((1<<8)-1),
551 if (0 == strcmp((char*) vendorid, "GenuineIntel")) {
552 auto_detect_Intel(cpu_info);
553 } else if (0 == strcmp((char*) vendorid, "AuthenticAMD")) {
554 auto_detect_AMD(cpu_info);
556 panic("Unknown Vendor ID for arch autodetection: %s\n", vendorid);
560 static void auto_detect_Intel(const struct cpu_info_t info) {
561 cpu_support auto_arch = cpu_generic;
563 switch (info.cpu_family) {
565 auto_arch = arch_i486; break;
567 auto_arch = arch_pentium; break;
569 auto_arch = arch_ppro; break;
571 auto_arch = arch_netburst; break;
573 panic("Unknown cpu family for arch autodetection: %X\n", info.cpu_family);
576 if (info.edx_features & (1<<23)) auto_arch |= arch_feature_mmx;
577 if (info.edx_features & (1<<25)) auto_arch |= arch_feature_sse1;
578 if (info.edx_features & (1<<26)) auto_arch |= arch_feature_sse2;
580 if (info.ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3;
581 if (info.ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3;
582 if (info.ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1;
583 if (info.ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2;
586 opt_arch = auto_arch;
589 static void auto_detect_AMD(const struct cpu_info_t info) {
590 cpu_support auto_arch = cpu_generic;
592 /* TODO find documentation on the cpu_family bits
593 for now we fall back to arch_k6. */
596 if (info.edx_features & (1<<23)) auto_arch |= arch_feature_mmx;
597 if (info.edx_features & (1<<25)) auto_arch |= arch_feature_sse1;
598 if (info.edx_features & (1<<26)) auto_arch |= arch_feature_sse2;
600 if (info.ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3;
601 if (info.ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3;
602 if (info.ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1;
603 if (info.ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2;
606 opt_arch = auto_arch;
609 void ia32_setup_cg_config(void)
611 ia32_code_gen_config_t *const c = &ia32_cg_config;
612 memset(c, 0, sizeof(*c));
616 if (arch == 0) autodetect_arch();
618 c->optimize_size = opt_size != 0;
619 /* on newer intel cpus mov, pop is often faster than leave although it has a
621 c->use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
622 /* P4s don't like inc/decs because they only partially write the flags
623 * register which produces false dependencies */
624 c->use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
625 c->use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
626 c->use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
627 c->use_ftst = !FLAGS(arch, arch_feature_p6_insn);
628 /* valgrind can't cope with femms yet and the usefulness of the optimization
629 * is questionable anyway */
631 c->use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
632 FLAGS(arch, arch_feature_mmx | arch_all_amd);
636 c->use_fucomi = FLAGS(arch, arch_feature_p6_insn);
637 c->use_cmov = FLAGS(arch, arch_feature_p6_insn);
638 c->use_modeD_moves = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode);
639 c->use_add_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size;
640 c->use_add_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size;
641 c->use_sub_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size;
642 c->use_sub_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size;
643 c->use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
644 c->use_pxor = FLAGS(opt_arch, arch_netburst);
645 c->use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
646 c->use_short_sex_eax = !FLAGS(opt_arch, arch_k6) && !opt_size;
647 c->use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
648 c->use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
649 c->use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3);
650 c->use_sse_prefetch = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1));
651 c->use_3dnow_prefetch = FLAGS(arch, arch_feature_3DNow);
652 c->use_popcnt = FLAGS(arch, (arch_feature_sse4_2 | arch_feature_sse4a));
653 c->use_i486 = (arch & arch_mask) >= arch_i486;
654 c->optimize_cc = opt_cc;
655 c->use_unsafe_floatconv = opt_unsafe_floatconv;
656 c->emit_machcode = emit_machcode;
658 c->function_alignment = arch_costs->function_alignment;
659 c->label_alignment = arch_costs->label_alignment;
660 c->label_alignment_max_skip = arch_costs->label_alignment_max_skip;
662 c->label_alignment_factor =
663 FLAGS(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 :
664 opt_arch & arch_all_amd ? 3 :
668 void ia32_init_architecture(void)
670 lc_opt_entry_t *be_grp, *ia32_grp;
672 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
674 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
675 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
677 lc_opt_add_table(ia32_grp, ia32_architecture_options);