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4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
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9 * packaging of this file.
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12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
29 #include "lc_opts_enum.h"
33 #include "bearch_ia32_t.h"
34 #include "ia32_architecture.h"
39 #if defined(_M_IX86) || defined(_M_X64)
44 #if defined(__i386__) || defined(__x86_64__)
49 ia32_code_gen_config_t ia32_cg_config;
52 * CPU architectures and features.
54 enum cpu_arch_features {
55 arch_generic32 = 0x00000001, /**< no specific architecture */
57 arch_i386 = 0x00000002, /**< i386 architecture */
58 arch_i486 = 0x00000004, /**< i486 architecture */
59 arch_pentium = 0x00000008, /**< Pentium architecture */
60 arch_ppro = 0x00000010, /**< PentiumPro architecture */
61 arch_netburst = 0x00000020, /**< Netburst architecture */
62 arch_nocona = 0x00000040, /**< Nocona architecture */
63 arch_core2 = 0x00000080, /**< Core2 architecture */
64 arch_atom = 0x00000100, /**< Atom architecture */
66 arch_k6 = 0x00000200, /**< k6 architecture */
67 arch_geode = 0x00000400, /**< Geode architecture */
68 arch_athlon = 0x00000800, /**< Athlon architecture */
69 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
70 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
72 arch_mask = 0x00003FFF,
74 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
75 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
77 arch_feature_mmx = 0x00004000, /**< MMX instructions */
78 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
79 arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
80 arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
81 arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
82 arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
83 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
84 arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
85 arch_feature_64bit = 0x00400000, /**< x86_64 support */
86 arch_feature_sse4_1 = 0x00800000, /**< SSE4.1 instructions */
87 arch_feature_sse4_2 = 0x01000000, /**< SSE4.2 instructions */
88 arch_feature_sse4a = 0x02000000, /**< SSE4a instructions */
90 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
91 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
92 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
93 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
94 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
95 arch_sse4_1_insn = arch_feature_sse4_1 | arch_ssse3_insn, /**< SSE4.1 instructions, include SSSE3 */
96 arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */
97 arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */
99 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
100 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
101 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
104 #define FLAGS(x, f) (((x) & (f)) != 0)
109 typedef enum cpu_support {
110 cpu_generic = arch_generic32,
113 cpu_i386 = arch_i386,
114 cpu_i486 = arch_i486,
115 cpu_pentium = arch_pentium,
116 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
117 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
118 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
119 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
120 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
121 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
122 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
123 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
124 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
125 cpu_penryn = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
128 cpu_k6 = arch_k6 | arch_mmx_insn,
129 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
130 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
131 cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_p6_insn,
132 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
133 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
134 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
135 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
136 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse4a_insn,
139 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
140 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
141 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
142 cpu_c3_2 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */
147 static int opt_size = 0;
148 static int emit_machcode = 0;
149 static cpu_support arch = cpu_generic;
150 static cpu_support opt_arch = cpu_generic;
151 static int use_sse2 = 0;
152 static int opt_cc = 1;
153 static int opt_unsafe_floatconv = 0;
155 /* instruction set architectures. */
156 static const lc_opt_enum_int_items_t arch_items[] = {
157 { "i386", cpu_i386 },
158 { "i486", cpu_i486 },
159 { "i586", cpu_pentium },
160 { "pentium", cpu_pentium },
161 { "pentium-mmx", cpu_pentium_mmx },
162 { "i686", cpu_pentium_pro },
163 { "pentiumpro", cpu_pentium_pro },
164 { "pentium2", cpu_pentium_2 },
165 { "p2", cpu_pentium_2 },
166 { "pentium3", cpu_pentium_3 },
167 { "pentium3m", cpu_pentium_3 },
168 { "p3", cpu_pentium_3 },
169 { "pentium-m", cpu_pentium_m },
170 { "pm", cpu_pentium_m },
171 { "pentium4", cpu_pentium_4 },
172 { "pentium4m", cpu_pentium_4 },
173 { "p4", cpu_pentium_4 },
174 { "prescott", cpu_prescott },
175 { "nocona", cpu_nocona },
176 { "merom", cpu_core2 },
177 { "core2", cpu_core2 },
178 { "penryn", cpu_penryn },
181 { "k6-2", cpu_k6_PLUS },
182 { "k6-3", cpu_k6_PLUS },
183 { "geode", cpu_geode },
184 { "athlon", cpu_athlon_old },
185 { "athlon-tbird", cpu_athlon },
186 { "athlon-4", cpu_athlon },
187 { "athlon-xp", cpu_athlon },
188 { "athlon-mp", cpu_athlon },
189 { "athlon64", cpu_athlon64 },
191 { "opteron", cpu_k8 },
192 { "athlon-fx", cpu_k8 },
193 { "k8-sse3", cpu_k8_sse3 },
194 { "opteron-sse3", cpu_k8_sse3 },
196 { "barcelona", cpu_k10 },
197 { "amdfam10", cpu_k10 },
199 { "winchip-c6", cpu_winchip_c6, },
200 { "winchip2", cpu_winchip2 },
202 { "c3-2", cpu_c3_2 },
204 { "generic", cpu_generic },
205 { "generic32", cpu_generic },
207 { "native", cpu_autodetect },
211 static lc_opt_enum_int_var_t arch_var = {
212 (int*) &arch, arch_items
215 static lc_opt_enum_int_var_t opt_arch_var = {
216 (int*) &opt_arch, arch_items
219 static const lc_opt_enum_int_items_t fp_unit_items[] = {
225 static lc_opt_enum_int_var_t fp_unit_var = {
226 &use_sse2, fp_unit_items
229 static const lc_opt_table_entry_t ia32_architecture_options[] = {
230 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
231 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
233 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
235 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
237 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
239 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
240 "optimisations", &opt_unsafe_floatconv, 1),
241 LC_OPT_ENT_BOOL("machcode", "output machine code instead of assembler",
246 typedef struct insn_const {
247 int add_cost; /**< cost of an add instruction */
248 int lea_cost; /**< cost of a lea instruction */
249 int const_shf_cost; /**< cost of a constant shift instruction */
250 int cost_mul_start; /**< starting cost of a multiply instruction */
251 int cost_mul_bit; /**< cost of multiply for every set bit */
252 unsigned function_alignment; /**< logarithm for alignment of function labels */
253 unsigned label_alignment; /**< logarithm for alignment of loops labels */
254 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
257 /* costs for optimizing for size */
258 static const insn_const size_cost = {
259 2, /* cost of an add instruction */
260 3, /* cost of a lea instruction */
261 3, /* cost of a constant shift instruction */
262 4, /* starting cost of a multiply instruction */
263 0, /* cost of multiply for every set bit */
264 0, /* logarithm for alignment of function labels */
265 0, /* logarithm for alignment of loops labels */
266 0, /* maximum skip for alignment of loops labels */
269 /* costs for the i386 */
270 static const insn_const i386_cost = {
271 1, /* cost of an add instruction */
272 1, /* cost of a lea instruction */
273 3, /* cost of a constant shift instruction */
274 9, /* starting cost of a multiply instruction */
275 1, /* cost of multiply for every set bit */
276 2, /* logarithm for alignment of function labels */
277 2, /* logarithm for alignment of loops labels */
278 3, /* maximum skip for alignment of loops labels */
281 /* costs for the i486 */
282 static const insn_const i486_cost = {
283 1, /* cost of an add instruction */
284 1, /* cost of a lea instruction */
285 2, /* cost of a constant shift instruction */
286 12, /* starting cost of a multiply instruction */
287 1, /* cost of multiply for every set bit */
288 4, /* logarithm for alignment of function labels */
289 4, /* logarithm for alignment of loops labels */
290 15, /* maximum skip for alignment of loops labels */
293 /* costs for the Pentium */
294 static const insn_const pentium_cost = {
295 1, /* cost of an add instruction */
296 1, /* cost of a lea instruction */
297 1, /* cost of a constant shift instruction */
298 11, /* starting cost of a multiply instruction */
299 0, /* cost of multiply for every set bit */
300 4, /* logarithm for alignment of function labels */
301 4, /* logarithm for alignment of loops labels */
302 7, /* maximum skip for alignment of loops labels */
305 /* costs for the Pentium Pro */
306 static const insn_const pentiumpro_cost = {
307 1, /* cost of an add instruction */
308 1, /* cost of a lea instruction */
309 1, /* cost of a constant shift instruction */
310 4, /* starting cost of a multiply instruction */
311 0, /* cost of multiply for every set bit */
312 4, /* logarithm for alignment of function labels */
313 4, /* logarithm for alignment of loops labels */
314 10, /* maximum skip for alignment of loops labels */
317 /* costs for the K6 */
318 static const insn_const k6_cost = {
319 1, /* cost of an add instruction */
320 2, /* cost of a lea instruction */
321 1, /* cost of a constant shift instruction */
322 3, /* starting cost of a multiply instruction */
323 0, /* cost of multiply for every set bit */
324 5, /* logarithm for alignment of function labels */
325 5, /* logarithm for alignment of loops labels */
326 7, /* maximum skip for alignment of loops labels */
329 /* costs for the Geode */
330 static const insn_const geode_cost = {
331 1, /* cost of an add instruction */
332 1, /* cost of a lea instruction */
333 1, /* cost of a constant shift instruction */
334 7, /* starting cost of a multiply instruction */
335 0, /* cost of multiply for every set bit */
336 0, /* logarithm for alignment of function labels */
337 0, /* logarithm for alignment of loops labels */
338 0, /* maximum skip for alignment of loops labels */
341 /* costs for the Athlon */
342 static const insn_const athlon_cost = {
343 1, /* cost of an add instruction */
344 2, /* cost of a lea instruction */
345 1, /* cost of a constant shift instruction */
346 5, /* starting cost of a multiply instruction */
347 0, /* cost of multiply for every set bit */
348 4, /* logarithm for alignment of function labels */
349 4, /* logarithm for alignment of loops labels */
350 7, /* maximum skip for alignment of loops labels */
353 /* costs for the Opteron/K8 */
354 static const insn_const k8_cost = {
355 1, /* cost of an add instruction */
356 2, /* cost of a lea instruction */
357 1, /* cost of a constant shift instruction */
358 3, /* starting cost of a multiply instruction */
359 0, /* cost of multiply for every set bit */
361 4, /* logarithm for alignment of function labels */
362 4, /* logarithm for alignment of loops labels */
363 7, /* maximum skip for alignment of loops labels */
371 /* costs for the K10 */
372 static const insn_const k10_cost = {
373 1, /* cost of an add instruction */
374 2, /* cost of a lea instruction */
375 1, /* cost of a constant shift instruction */
376 3, /* starting cost of a multiply instruction */
377 0, /* cost of multiply for every set bit */
378 5, /* logarithm for alignment of function labels */
379 5, /* logarithm for alignment of loops labels */
380 7, /* maximum skip for alignment of loops labels */
383 /* costs for the Pentium 4 */
384 static const insn_const netburst_cost = {
385 1, /* cost of an add instruction */
386 3, /* cost of a lea instruction */
387 4, /* cost of a constant shift instruction */
388 15, /* starting cost of a multiply instruction */
389 0, /* cost of multiply for every set bit */
390 4, /* logarithm for alignment of function labels */
391 4, /* logarithm for alignment of loops labels */
392 7, /* maximum skip for alignment of loops labels */
395 /* costs for the Nocona and Core */
396 static const insn_const nocona_cost = {
397 1, /* cost of an add instruction */
398 1, /* cost of a lea instruction */
399 1, /* cost of a constant shift instruction */
400 10, /* starting cost of a multiply instruction */
401 0, /* cost of multiply for every set bit */
402 4, /* logarithm for alignment of function labels */
403 4, /* logarithm for alignment of loops labels */
404 7, /* maximum skip for alignment of loops labels */
407 /* costs for the Core2 */
408 static const insn_const core2_cost = {
409 1, /* cost of an add instruction */
410 1, /* cost of a lea instruction */
411 1, /* cost of a constant shift instruction */
412 3, /* starting cost of a multiply instruction */
413 0, /* cost of multiply for every set bit */
414 4, /* logarithm for alignment of function labels */
415 4, /* logarithm for alignment of loops labels */
416 10, /* maximum skip for alignment of loops labels */
419 /* costs for the generic32 */
420 static const insn_const generic32_cost = {
421 1, /* cost of an add instruction */
422 2, /* cost of a lea instruction */
423 1, /* cost of a constant shift instruction */
424 4, /* starting cost of a multiply instruction */
425 0, /* cost of multiply for every set bit */
426 4, /* logarithm for alignment of function labels */
427 4, /* logarithm for alignment of loops labels */
428 7, /* maximum skip for alignment of loops labels */
431 static const insn_const *arch_costs = &generic32_cost;
433 static void set_arch_costs(void)
436 arch_costs = &size_cost;
439 switch (opt_arch & arch_mask) {
440 case arch_i386: arch_costs = &i386_cost; break;
441 case arch_i486: arch_costs = &i486_cost; break;
442 case arch_pentium: arch_costs = &pentium_cost; break;
443 case arch_ppro: arch_costs = &pentiumpro_cost; break;
444 case arch_netburst: arch_costs = &netburst_cost; break;
445 case arch_nocona: arch_costs = &nocona_cost; break;
446 case arch_core2: arch_costs = &core2_cost; break;
447 case arch_k6: arch_costs = &k6_cost; break;
448 case arch_geode: arch_costs = &geode_cost; break;
449 case arch_athlon: arch_costs = &athlon_cost; break;
450 case arch_k8: arch_costs = &k8_cost; break;
451 case arch_k10: arch_costs = &k10_cost; break;
453 case arch_generic32: arch_costs = &generic32_cost; break;
457 /* Evaluate the costs of an instruction. */
458 int ia32_evaluate_insn(insn_kind kind, const ir_mode *mode, ir_tarval *tv)
464 cost = arch_costs->cost_mul_start;
465 if (arch_costs->cost_mul_bit > 0) {
466 char *bitstr = get_tarval_bitpattern(tv);
469 for (i = 0; bitstr[i] != '\0'; ++i) {
470 if (bitstr[i] == '1') {
471 cost += arch_costs->cost_mul_bit;
476 if (get_mode_size_bits(mode) <= 32)
478 /* 64bit mul supported, approx 4times of a 32bit mul*/
481 /* lea is only supported for 32 bit */
482 if (get_mode_size_bits(mode) <= 32)
483 return arch_costs->lea_cost;
484 /* in 64bit mode, the Lea cost are at wort 2 shifts and one add */
485 return 2 * arch_costs->add_cost + 2 * (2 * arch_costs->const_shf_cost);
488 if (get_mode_size_bits(mode) <= 32)
489 return arch_costs->add_cost;
490 /* 64bit add/sub supported, double the cost */
491 return 2 * arch_costs->add_cost;
493 if (get_mode_size_bits(mode) <= 32)
494 return arch_costs->const_shf_cost;
495 /* 64bit shift supported, double the cost */
496 return 2 * arch_costs->const_shf_cost;
498 return arch_costs->add_cost;
504 /* auto detection code only works if we're on an x86 cpu obviously */
506 typedef struct x86_cpu_info_t {
507 unsigned char cpu_stepping;
508 unsigned char cpu_model;
509 unsigned char cpu_family;
510 unsigned char cpu_type;
511 unsigned char cpu_ext_model;
512 unsigned char cpu_ext_family;
513 unsigned edx_features;
514 unsigned ecx_features;
515 unsigned add_features;
518 static cpu_support auto_detect_Intel(x86_cpu_info_t const *info)
520 cpu_support auto_arch = cpu_generic;
522 unsigned family = (info->cpu_ext_family << 4) | info->cpu_family;
523 unsigned model = (info->cpu_ext_model << 4) | info->cpu_model;
527 auto_arch = arch_i486;
530 auto_arch = arch_pentium;
534 case 0x01: /* PentiumPro */
535 case 0x03: /* Pentium II Model 3 */
536 case 0x05: /* Pentium II Model 5 */
537 case 0x06: /* Celeron Model 6 */
538 case 0x07: /* Pentium III Model 7 */
539 case 0x08: /* Pentium III Model 8 */
540 case 0x09: /* Pentium M Model 9 */
541 case 0x0A: /* Pentium III Model 0A */
542 case 0x0B: /* Pentium III Model 0B */
543 case 0x0D: /* Pentium M Model 0D */
544 auto_arch = arch_ppro;
546 case 0x0E: /* Core Model 0E */
547 auto_arch = arch_ppro;
549 case 0x0F: /* Core2 Model 0F */
550 case 0x15: /* Intel EP80579 */
551 case 0x16: /* Celeron Model 16 */
552 case 0x17: /* Core2 Model 17 */
553 auto_arch = arch_core2;
562 case 0x00: /* Pentium 4 Model 00 */
563 case 0x01: /* Pentium 4 Model 01 */
564 case 0x02: /* Pentium 4 Model 02 */
565 case 0x03: /* Pentium 4 Model 03 */
566 case 0x04: /* Pentium 4 Model 04 */
567 case 0x06: /* Pentium 4 Model 06 */
568 auto_arch = arch_netburst;
570 case 0x1A: /* Core i7 */
571 auto_arch = arch_core2;
573 case 0x1C: /* Atom */
574 auto_arch = arch_atom;
576 case 0x1D: /* Xeon MP */
577 auto_arch = arch_core2;
589 if (info->edx_features & (1<<23)) auto_arch |= arch_feature_mmx;
590 if (info->edx_features & (1<<25)) auto_arch |= arch_feature_sse1;
591 if (info->edx_features & (1<<26)) auto_arch |= arch_feature_sse2;
593 if (info->ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3;
594 if (info->ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3;
595 if (info->ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1;
596 if (info->ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2;
601 static cpu_support auto_detect_AMD(x86_cpu_info_t const *info) {
602 cpu_support auto_arch = cpu_generic;
604 unsigned family, model;
606 if (info->cpu_family == 0x0F) {
607 family = (info->cpu_ext_family << 4) | info->cpu_family;
608 model = (info->cpu_ext_model << 4) | info->cpu_model;
610 family = info->cpu_family;
611 model = info->cpu_model;
616 auto_arch = arch_i486;
619 case 0x06: // actually, 6 means K7 family
627 auto_arch = arch_k10;
634 if (info->edx_features & (1<<23)) auto_arch |= arch_feature_mmx;
635 if (info->edx_features & (1<<25)) auto_arch |= arch_feature_sse1;
636 if (info->edx_features & (1<<26)) auto_arch |= arch_feature_sse2;
638 if (info->ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3;
639 if (info->ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3;
640 if (info->ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1;
641 if (info->ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2;
656 static void x86_cpuid(cpuid_registers *regs, unsigned level)
658 #if defined(__GNUC__)
660 : "=a" (regs->r.eax), "=b" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
663 #elif defined(_MSC_VER)
664 __cpuid(regs->bulk, level);
668 static int x86_toogle_cpuid(void)
670 unsigned eflags_before = 0, eflags_after = 0;
672 #if defined(__GNUC__)
674 /* If bit 21 of the EFLAGS register can be changed, the cpuid instruction is available */
679 "xorl $0x00200000, %1\n\t"
684 : "=r" (eflags_before), "=r" (eflags_after) :: "cc"
687 /* cpuid always available on 64bit */
690 #elif defined(_MSC_VER)
695 mov eflags_before, eax
701 mov eflags_after, eax
707 return (eflags_before ^ eflags_after) & 0x00200000;
710 static void autodetect_arch(void)
712 cpu_support auto_arch = cpu_generic;
714 /* We use the cpuid instruction to detect the CPU features */
715 if (x86_toogle_cpuid()) {
716 cpuid_registers regs;
717 unsigned highest_level;
719 x86_cpu_info_t cpu_info;
723 highest_level = regs.r.eax;
724 memcpy(&vendorid[0], ®s.r.ebx, 4);
725 memcpy(&vendorid[4], ®s.r.edx, 4);
726 memcpy(&vendorid[8], ®s.r.ecx, 4);
729 /* get processor info and feature bits */
732 cpu_info.cpu_stepping = (regs.r.eax >> 0) & 0x0F;
733 cpu_info.cpu_model = (regs.r.eax >> 4) & 0x0F;
734 cpu_info.cpu_family = (regs.r.eax >> 8) & 0x0F;
735 cpu_info.cpu_type = (regs.r.eax >> 12) & 0x03;
736 cpu_info.cpu_ext_model = (regs.r.eax >> 16) & 0x0F;
737 cpu_info.cpu_ext_family = (regs.r.eax >> 20) & 0xFF;
738 cpu_info.edx_features = regs.r.edx;
739 cpu_info.ecx_features = regs.r.ecx;
740 cpu_info.add_features = regs.r.ebx;
742 if (0 == strcmp(vendorid, "GenuineIntel")) {
743 auto_arch = auto_detect_Intel(&cpu_info);
744 } else if (0 == strcmp(vendorid, "AuthenticAMD")) {
745 auto_arch = auto_detect_AMD(&cpu_info);
750 opt_arch = auto_arch;
753 static void autodetect_arch(void)
755 panic("architecture autodetection only possible when compiling on target architecture");
759 void ia32_setup_cg_config(void)
761 ia32_code_gen_config_t *const c = &ia32_cg_config;
762 memset(c, 0, sizeof(*c));
769 c->optimize_size = opt_size != 0;
770 /* on newer intel cpus mov, pop is often faster than leave although it has a
772 c->use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
773 /* P4s don't like inc/decs because they only partially write the flags
774 * register which produces false dependencies */
775 c->use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
776 c->use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
777 c->use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
778 c->use_ftst = !FLAGS(arch, arch_feature_p6_insn);
779 /* valgrind can't cope with femms yet and the usefulness of the optimization
780 * is questionable anyway */
782 c->use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
783 FLAGS(arch, arch_feature_mmx | arch_all_amd);
787 c->use_fucomi = FLAGS(arch, arch_feature_p6_insn);
788 c->use_cmov = FLAGS(arch, arch_feature_p6_insn);
789 c->use_modeD_moves = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode);
790 c->use_add_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size;
791 c->use_add_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size;
792 c->use_sub_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size;
793 c->use_sub_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size;
794 c->use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
795 c->use_pxor = FLAGS(opt_arch, arch_netburst);
796 c->use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
797 c->use_short_sex_eax = !FLAGS(opt_arch, arch_k6) && !opt_size;
798 c->use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
799 c->use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
800 c->use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3);
801 c->use_sse_prefetch = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1));
802 c->use_3dnow_prefetch = FLAGS(arch, arch_feature_3DNow);
803 c->use_popcnt = FLAGS(arch, (arch_feature_sse4_2 | arch_feature_sse4a));
804 c->use_i486 = (arch & arch_mask) >= arch_i486;
805 c->optimize_cc = opt_cc;
806 c->use_unsafe_floatconv = opt_unsafe_floatconv;
807 c->emit_machcode = emit_machcode;
809 c->function_alignment = arch_costs->function_alignment;
810 c->label_alignment = arch_costs->label_alignment;
811 c->label_alignment_max_skip = arch_costs->label_alignment_max_skip;
813 c->label_alignment_factor =
814 FLAGS(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 :
815 opt_arch & arch_all_amd ? 3 :
819 void ia32_init_architecture(void)
821 lc_opt_entry_t *be_grp, *ia32_grp;
823 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
825 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
826 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
828 lc_opt_add_table(ia32_grp, ia32_architecture_options);