2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief ia32 architecture variants
9 * @author Michael Beck, Matthias Braun
15 #include "lc_opts_enum.h"
19 #include "bearch_ia32_t.h"
20 #include "ia32_architecture.h"
25 #if defined(_M_IX86) || defined(_M_X64)
30 #if defined(__i386__) || defined(__x86_64__)
35 ia32_code_gen_config_t ia32_cg_config;
38 * CPU architectures and features.
40 typedef enum cpu_arch_features {
41 arch_generic32 = 0x00000001, /**< no specific architecture */
43 arch_i386 = 0x00000002, /**< i386 architecture */
44 arch_i486 = 0x00000004, /**< i486 architecture */
45 arch_pentium = 0x00000008, /**< Pentium architecture */
46 arch_ppro = 0x00000010, /**< PentiumPro architecture */
47 arch_netburst = 0x00000020, /**< Netburst architecture */
48 arch_nocona = 0x00000040, /**< Nocona architecture */
49 arch_core2 = 0x00000080, /**< Core2 architecture */
50 arch_atom = 0x00000100, /**< Atom architecture */
52 arch_k6 = 0x00000200, /**< k6 architecture */
53 arch_geode = 0x00000400, /**< Geode architecture */
54 arch_athlon = 0x00000800, /**< Athlon architecture */
55 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
56 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
58 arch_mask = 0x00003FFF,
60 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
61 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
63 arch_feature_mmx = 0x00004000, /**< MMX instructions */
64 arch_feature_cmov = 0x00008000, /**< cmov instructions */
65 arch_feature_p6_insn = 0x00010000, /**< PentiumPro instructions */
66 arch_feature_sse1 = 0x00020000, /**< SSE1 instructions */
67 arch_feature_sse2 = 0x00040000, /**< SSE2 instructions */
68 arch_feature_sse3 = 0x00080000, /**< SSE3 instructions */
69 arch_feature_ssse3 = 0x00100000, /**< SSSE3 instructions */
70 arch_feature_3DNow = 0x00200000, /**< 3DNow! instructions */
71 arch_feature_3DNowE = 0x00400000, /**< Enhanced 3DNow! instructions */
72 arch_feature_64bit = 0x00800000, /**< x86_64 support */
73 arch_feature_sse4_1 = 0x01000000, /**< SSE4.1 instructions */
74 arch_feature_sse4_2 = 0x02000000, /**< SSE4.2 instructions */
75 arch_feature_sse4a = 0x04000000, /**< SSE4a instructions */
76 arch_feature_popcnt = 0x08000000, /**< popcnt instruction */
78 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
79 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
80 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
81 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
82 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
83 arch_sse4_1_insn = arch_feature_sse4_1 | arch_ssse3_insn, /**< SSE4.1 instructions, include SSSE3 */
84 arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */
85 arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */
87 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
88 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
89 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
91 cpu_generic = arch_generic32,
96 cpu_pentium = arch_pentium,
97 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
98 cpu_pentium_pro_generic = arch_ppro | arch_feature_p6_insn,
99 cpu_pentium_pro = arch_ppro | arch_feature_cmov | arch_feature_p6_insn,
100 cpu_pentium_2 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_mmx_insn,
101 cpu_pentium_3 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse1_insn,
102 cpu_pentium_m = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn,
103 cpu_netburst_generic = arch_netburst | arch_feature_p6_insn,
104 cpu_pentium_4 = arch_netburst | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn,
105 cpu_prescott = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_sse3_insn,
106 cpu_nocona = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
107 cpu_core2_generic = arch_core2 | arch_feature_p6_insn,
108 cpu_core2 = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
109 cpu_penryn = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
110 cpu_atom_generic = arch_atom | arch_feature_p6_insn,
111 cpu_atom = arch_atom | arch_feature_cmov | arch_feature_p6_insn | arch_ssse3_insn,
114 cpu_k6_generic = arch_k6,
115 cpu_k6 = arch_k6 | arch_mmx_insn,
116 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
117 cpu_geode_generic = arch_geode,
118 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
119 cpu_athlon_generic = arch_athlon | arch_feature_p6_insn,
120 cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn,
121 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn,
122 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn,
123 cpu_k8_generic = arch_k8 | arch_feature_p6_insn,
124 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn,
125 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
126 cpu_k10_generic = arch_k10 | arch_feature_p6_insn,
127 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_feature_popcnt | arch_64bit_insn | arch_sse4a_insn,
130 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
131 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
132 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
133 cpu_c3_2 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */
137 ENUM_BITSET(cpu_arch_features)
139 static int opt_size = 0;
140 static int emit_machcode = 0;
141 static cpu_arch_features arch = cpu_generic;
142 static cpu_arch_features opt_arch = cpu_generic;
143 static int fpu_arch = 0;
144 static int opt_cc = 1;
145 static int opt_unsafe_floatconv = 0;
147 /* instruction set architectures. */
148 static const lc_opt_enum_int_items_t arch_items[] = {
149 { "i386", cpu_i386 },
150 { "i486", cpu_i486 },
151 { "i586", cpu_pentium },
152 { "pentium", cpu_pentium },
153 { "pentium-mmx", cpu_pentium_mmx },
154 { "i686", cpu_pentium_pro },
155 { "pentiumpro", cpu_pentium_pro },
156 { "pentium2", cpu_pentium_2 },
157 { "p2", cpu_pentium_2 },
158 { "pentium3", cpu_pentium_3 },
159 { "pentium3m", cpu_pentium_3 },
160 { "p3", cpu_pentium_3 },
161 { "pentium-m", cpu_pentium_m },
162 { "pm", cpu_pentium_m },
163 { "pentium4", cpu_pentium_4 },
164 { "pentium4m", cpu_pentium_4 },
165 { "p4", cpu_pentium_4 },
166 { "prescott", cpu_prescott },
167 { "nocona", cpu_nocona },
168 { "merom", cpu_core2 },
169 { "core2", cpu_core2 },
170 { "penryn", cpu_penryn },
171 { "atom", cpu_atom },
174 { "k6-2", cpu_k6_PLUS },
175 { "k6-3", cpu_k6_PLUS },
176 { "geode", cpu_geode },
177 { "athlon", cpu_athlon_old },
178 { "athlon-tbird", cpu_athlon },
179 { "athlon-4", cpu_athlon },
180 { "athlon-xp", cpu_athlon },
181 { "athlon-mp", cpu_athlon },
182 { "athlon64", cpu_athlon64 },
184 { "opteron", cpu_k8 },
185 { "athlon-fx", cpu_k8 },
186 { "k8-sse3", cpu_k8_sse3 },
187 { "opteron-sse3", cpu_k8_sse3 },
189 { "barcelona", cpu_k10 },
190 { "amdfam10", cpu_k10 },
192 { "winchip-c6", cpu_winchip_c6, },
193 { "winchip2", cpu_winchip2 },
195 { "c3-2", cpu_c3_2 },
197 { "generic", cpu_generic },
198 { "generic32", cpu_generic },
201 { "native", cpu_autodetect },
207 static lc_opt_enum_int_var_t arch_var = {
208 (int*) &arch, arch_items
211 static lc_opt_enum_int_var_t opt_arch_var = {
212 (int*) &opt_arch, arch_items
215 static const lc_opt_enum_int_items_t fp_unit_items[] = {
216 { "x87" , IA32_FPU_ARCH_X87 },
217 { "sse2", IA32_FPU_ARCH_SSE2 },
218 { "softfloat", IA32_FPU_ARCH_SOFTFLOAT },
219 { NULL, IA32_FPU_ARCH_NONE }
222 static lc_opt_enum_int_var_t fp_unit_var = {
223 &fpu_arch, fp_unit_items
226 static const lc_opt_table_entry_t ia32_architecture_options[] = {
227 LC_OPT_ENT_BOOL ("size", "optimize for size", &opt_size),
228 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
229 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
230 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
231 LC_OPT_ENT_BOOL ("optcc", "optimize calling convention", &opt_cc),
232 LC_OPT_ENT_BOOL ("unsafe_floatconv", "do unsafe floating point controlword optimisations", &opt_unsafe_floatconv),
233 LC_OPT_ENT_BOOL ("machcode", "output machine code instead of assembler", &emit_machcode),
237 typedef struct insn_const {
238 int add_cost; /**< cost of an add instruction */
239 int lea_cost; /**< cost of a lea instruction */
240 int const_shf_cost; /**< cost of a constant shift instruction */
241 int cost_mul_start; /**< starting cost of a multiply instruction */
242 int cost_mul_bit; /**< cost of multiply for every set bit */
243 unsigned function_alignment; /**< logarithm for alignment of function labels */
244 unsigned label_alignment; /**< logarithm for alignment of loops labels */
245 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
248 /* costs for optimizing for size */
249 static const insn_const size_cost = {
250 2, /* cost of an add instruction */
251 3, /* cost of a lea instruction */
252 3, /* cost of a constant shift instruction */
253 4, /* starting cost of a multiply instruction */
254 0, /* cost of multiply for every set bit */
255 0, /* logarithm for alignment of function labels */
256 0, /* logarithm for alignment of loops labels */
257 0, /* maximum skip for alignment of loops labels */
260 /* costs for the i386 */
261 static const insn_const i386_cost = {
262 1, /* cost of an add instruction */
263 1, /* cost of a lea instruction */
264 3, /* cost of a constant shift instruction */
265 9, /* starting cost of a multiply instruction */
266 1, /* cost of multiply for every set bit */
267 2, /* logarithm for alignment of function labels */
268 2, /* logarithm for alignment of loops labels */
269 3, /* maximum skip for alignment of loops labels */
272 /* costs for the i486 */
273 static const insn_const i486_cost = {
274 1, /* cost of an add instruction */
275 1, /* cost of a lea instruction */
276 2, /* cost of a constant shift instruction */
277 12, /* starting cost of a multiply instruction */
278 1, /* cost of multiply for every set bit */
279 4, /* logarithm for alignment of function labels */
280 4, /* logarithm for alignment of loops labels */
281 15, /* maximum skip for alignment of loops labels */
284 /* costs for the Pentium */
285 static const insn_const pentium_cost = {
286 1, /* cost of an add instruction */
287 1, /* cost of a lea instruction */
288 1, /* cost of a constant shift instruction */
289 11, /* starting cost of a multiply instruction */
290 0, /* cost of multiply for every set bit */
291 4, /* logarithm for alignment of function labels */
292 4, /* logarithm for alignment of loops labels */
293 7, /* maximum skip for alignment of loops labels */
296 /* costs for the Pentium Pro */
297 static const insn_const pentiumpro_cost = {
298 1, /* cost of an add instruction */
299 1, /* cost of a lea instruction */
300 1, /* cost of a constant shift instruction */
301 4, /* starting cost of a multiply instruction */
302 0, /* cost of multiply for every set bit */
303 4, /* logarithm for alignment of function labels */
304 4, /* logarithm for alignment of loops labels */
305 10, /* maximum skip for alignment of loops labels */
308 /* costs for the K6 */
309 static const insn_const k6_cost = {
310 1, /* cost of an add instruction */
311 2, /* cost of a lea instruction */
312 1, /* cost of a constant shift instruction */
313 3, /* starting cost of a multiply instruction */
314 0, /* cost of multiply for every set bit */
315 5, /* logarithm for alignment of function labels */
316 5, /* logarithm for alignment of loops labels */
317 7, /* maximum skip for alignment of loops labels */
320 /* costs for the Geode */
321 static const insn_const geode_cost = {
322 1, /* cost of an add instruction */
323 1, /* cost of a lea instruction */
324 1, /* cost of a constant shift instruction */
325 7, /* starting cost of a multiply instruction */
326 0, /* cost of multiply for every set bit */
327 0, /* logarithm for alignment of function labels */
328 0, /* logarithm for alignment of loops labels */
329 0, /* maximum skip for alignment of loops labels */
332 /* costs for the Athlon */
333 static const insn_const athlon_cost = {
334 1, /* cost of an add instruction */
335 2, /* cost of a lea instruction */
336 1, /* cost of a constant shift instruction */
337 5, /* starting cost of a multiply instruction */
338 0, /* cost of multiply for every set bit */
339 4, /* logarithm for alignment of function labels */
340 4, /* logarithm for alignment of loops labels */
341 7, /* maximum skip for alignment of loops labels */
344 /* costs for the Opteron/K8 */
345 static const insn_const k8_cost = {
346 1, /* cost of an add instruction */
347 2, /* cost of a lea instruction */
348 1, /* cost of a constant shift instruction */
349 3, /* starting cost of a multiply instruction */
350 0, /* cost of multiply for every set bit */
351 4, /* logarithm for alignment of function labels */
352 4, /* logarithm for alignment of loops labels */
353 7, /* maximum skip for alignment of loops labels */
356 /* costs for the K10 */
357 static const insn_const k10_cost = {
358 1, /* cost of an add instruction */
359 2, /* cost of a lea instruction */
360 1, /* cost of a constant shift instruction */
361 3, /* starting cost of a multiply instruction */
362 0, /* cost of multiply for every set bit */
363 5, /* logarithm for alignment of function labels */
364 5, /* logarithm for alignment of loops labels */
365 7, /* maximum skip for alignment of loops labels */
368 /* costs for the Pentium 4 */
369 static const insn_const netburst_cost = {
370 1, /* cost of an add instruction */
371 3, /* cost of a lea instruction */
372 4, /* cost of a constant shift instruction */
373 15, /* starting cost of a multiply instruction */
374 0, /* cost of multiply for every set bit */
375 4, /* logarithm for alignment of function labels */
376 4, /* logarithm for alignment of loops labels */
377 7, /* maximum skip for alignment of loops labels */
380 /* costs for the Nocona and Core */
381 static const insn_const nocona_cost = {
382 1, /* cost of an add instruction */
383 1, /* cost of a lea instruction */
384 1, /* cost of a constant shift instruction */
385 10, /* starting cost of a multiply instruction */
386 0, /* cost of multiply for every set bit */
387 4, /* logarithm for alignment of function labels */
388 4, /* logarithm for alignment of loops labels */
389 7, /* maximum skip for alignment of loops labels */
392 /* costs for the Core2 */
393 static const insn_const core2_cost = {
394 1, /* cost of an add instruction */
395 1, /* cost of a lea instruction */
396 1, /* cost of a constant shift instruction */
397 3, /* starting cost of a multiply instruction */
398 0, /* cost of multiply for every set bit */
399 4, /* logarithm for alignment of function labels */
400 4, /* logarithm for alignment of loops labels */
401 10, /* maximum skip for alignment of loops labels */
404 /* costs for the generic32 */
405 static const insn_const generic32_cost = {
406 1, /* cost of an add instruction */
407 2, /* cost of a lea instruction */
408 1, /* cost of a constant shift instruction */
409 4, /* starting cost of a multiply instruction */
410 0, /* cost of multiply for every set bit */
411 4, /* logarithm for alignment of function labels */
412 4, /* logarithm for alignment of loops labels */
413 7, /* maximum skip for alignment of loops labels */
416 static const insn_const *arch_costs = &generic32_cost;
418 static void set_arch_costs(void)
421 arch_costs = &size_cost;
424 switch (opt_arch & arch_mask) {
425 case arch_i386: arch_costs = &i386_cost; break;
426 case arch_i486: arch_costs = &i486_cost; break;
427 case arch_pentium: arch_costs = &pentium_cost; break;
428 case arch_ppro: arch_costs = &pentiumpro_cost; break;
429 case arch_netburst: arch_costs = &netburst_cost; break;
430 case arch_nocona: arch_costs = &nocona_cost; break;
431 case arch_core2: arch_costs = &core2_cost; break;
432 case arch_k6: arch_costs = &k6_cost; break;
433 case arch_geode: arch_costs = &geode_cost; break;
434 case arch_athlon: arch_costs = &athlon_cost; break;
435 case arch_k8: arch_costs = &k8_cost; break;
436 case arch_k10: arch_costs = &k10_cost; break;
438 case arch_generic32: arch_costs = &generic32_cost; break;
442 /* Evaluate the costs of an instruction. */
443 int ia32_evaluate_insn(insn_kind kind, const ir_mode *mode, ir_tarval *tv)
449 cost = arch_costs->cost_mul_start;
450 if (arch_costs->cost_mul_bit > 0) {
451 char *bitstr = get_tarval_bitpattern(tv);
454 for (i = 0; bitstr[i] != '\0'; ++i) {
455 if (bitstr[i] == '1') {
456 cost += arch_costs->cost_mul_bit;
461 if (get_mode_size_bits(mode) <= 32)
463 /* 64bit mul supported, approx 4times of a 32bit mul*/
466 /* lea is only supported for 32 bit */
467 if (get_mode_size_bits(mode) <= 32)
468 return arch_costs->lea_cost;
469 /* in 64bit mode, the Lea cost are at wort 2 shifts and one add */
470 return 2 * arch_costs->add_cost + 2 * (2 * arch_costs->const_shf_cost);
473 if (get_mode_size_bits(mode) <= 32)
474 return arch_costs->add_cost;
475 /* 64bit add/sub supported, double the cost */
476 return 2 * arch_costs->add_cost;
478 if (get_mode_size_bits(mode) <= 32)
479 return arch_costs->const_shf_cost;
480 /* 64bit shift supported, double the cost */
481 return 2 * arch_costs->const_shf_cost;
483 return arch_costs->add_cost;
489 /* auto detection code only works if we're on an x86 cpu obviously */
491 typedef struct x86_cpu_info_t {
492 unsigned char cpu_stepping;
493 unsigned char cpu_model;
494 unsigned char cpu_family;
495 unsigned char cpu_type;
496 unsigned char cpu_ext_model;
497 unsigned char cpu_ext_family;
498 unsigned edx_features;
499 unsigned ecx_features;
500 unsigned add_features;
504 CPUID_FEAT_ECX_SSE3 = 1 << 0,
505 CPUID_FEAT_ECX_PCLMUL = 1 << 1,
506 CPUID_FEAT_ECX_DTES64 = 1 << 2,
507 CPUID_FEAT_ECX_MONITOR = 1 << 3,
508 CPUID_FEAT_ECX_DS_CPL = 1 << 4,
509 CPUID_FEAT_ECX_VMX = 1 << 5,
510 CPUID_FEAT_ECX_SMX = 1 << 6,
511 CPUID_FEAT_ECX_EST = 1 << 7,
512 CPUID_FEAT_ECX_TM2 = 1 << 8,
513 CPUID_FEAT_ECX_SSSE3 = 1 << 9,
514 CPUID_FEAT_ECX_CID = 1 << 10,
515 CPUID_FEAT_ECX_FMA = 1 << 12,
516 CPUID_FEAT_ECX_CX16 = 1 << 13,
517 CPUID_FEAT_ECX_ETPRD = 1 << 14,
518 CPUID_FEAT_ECX_PDCM = 1 << 15,
519 CPUID_FEAT_ECX_DCA = 1 << 18,
520 CPUID_FEAT_ECX_SSE4_1 = 1 << 19,
521 CPUID_FEAT_ECX_SSE4_2 = 1 << 20,
522 CPUID_FEAT_ECX_x2APIC = 1 << 21,
523 CPUID_FEAT_ECX_MOVBE = 1 << 22,
524 CPUID_FEAT_ECX_POPCNT = 1 << 23,
525 CPUID_FEAT_ECX_AES = 1 << 25,
526 CPUID_FEAT_ECX_XSAVE = 1 << 26,
527 CPUID_FEAT_ECX_OSXSAVE = 1 << 27,
528 CPUID_FEAT_ECX_AVX = 1 << 28,
530 CPUID_FEAT_EDX_FPU = 1 << 0,
531 CPUID_FEAT_EDX_VME = 1 << 1,
532 CPUID_FEAT_EDX_DE = 1 << 2,
533 CPUID_FEAT_EDX_PSE = 1 << 3,
534 CPUID_FEAT_EDX_TSC = 1 << 4,
535 CPUID_FEAT_EDX_MSR = 1 << 5,
536 CPUID_FEAT_EDX_PAE = 1 << 6,
537 CPUID_FEAT_EDX_MCE = 1 << 7,
538 CPUID_FEAT_EDX_CX8 = 1 << 8,
539 CPUID_FEAT_EDX_APIC = 1 << 9,
540 CPUID_FEAT_EDX_SEP = 1 << 11,
541 CPUID_FEAT_EDX_MTRR = 1 << 12,
542 CPUID_FEAT_EDX_PGE = 1 << 13,
543 CPUID_FEAT_EDX_MCA = 1 << 14,
544 CPUID_FEAT_EDX_CMOV = 1 << 15,
545 CPUID_FEAT_EDX_PAT = 1 << 16,
546 CPUID_FEAT_EDX_PSE36 = 1 << 17,
547 CPUID_FEAT_EDX_PSN = 1 << 18,
548 CPUID_FEAT_EDX_CLF = 1 << 19,
549 CPUID_FEAT_EDX_DTES = 1 << 21,
550 CPUID_FEAT_EDX_ACPI = 1 << 22,
551 CPUID_FEAT_EDX_MMX = 1 << 23,
552 CPUID_FEAT_EDX_FXSR = 1 << 24,
553 CPUID_FEAT_EDX_SSE = 1 << 25,
554 CPUID_FEAT_EDX_SSE2 = 1 << 26,
555 CPUID_FEAT_EDX_SS = 1 << 27,
556 CPUID_FEAT_EDX_HTT = 1 << 28,
557 CPUID_FEAT_EDX_TM1 = 1 << 29,
558 CPUID_FEAT_EDX_IA64 = 1 << 30,
559 CPUID_FEAT_EDX_PBE = 1 << 31
562 static cpu_arch_features auto_detect_Intel(x86_cpu_info_t const *info)
564 cpu_arch_features auto_arch = cpu_generic;
566 unsigned family = info->cpu_ext_family + info->cpu_family;
567 unsigned model = (info->cpu_ext_model << 4) | info->cpu_model;
571 auto_arch = cpu_i486;
574 auto_arch = cpu_pentium;
578 case 0x01: /* PentiumPro */
579 case 0x03: /* Pentium II Model 3 */
580 case 0x05: /* Pentium II Model 5 */
581 case 0x06: /* Celeron Model 6 */
582 case 0x07: /* Pentium III Model 7 */
583 case 0x08: /* Pentium III Model 8 */
584 case 0x09: /* Pentium M Model 9 */
585 case 0x0A: /* Pentium III Model 0A */
586 case 0x0B: /* Pentium III Model 0B */
587 case 0x0D: /* Pentium M Model 0D */
588 case 0x0E: /* Core Model 0E */
589 auto_arch = cpu_pentium_pro_generic;
591 case 0x0F: /* Core2 Model 0F */
592 case 0x15: /* Intel EP80579 */
593 case 0x16: /* Celeron Model 16 */
594 case 0x17: /* Core2 Model 17 */
595 auto_arch = cpu_core2_generic;
604 case 0x00: /* Pentium 4 Model 00 */
605 case 0x01: /* Pentium 4 Model 01 */
606 case 0x02: /* Pentium 4 Model 02 */
607 case 0x03: /* Pentium 4 Model 03 */
608 case 0x04: /* Pentium 4 Model 04 */
609 case 0x06: /* Pentium 4 Model 06 */
610 auto_arch = cpu_netburst_generic;
612 case 0x1A: /* Core i7 */
613 auto_arch = cpu_core2_generic;
615 case 0x1C: /* Atom */
616 auto_arch = cpu_atom_generic;
618 case 0x1D: /* Xeon MP */
619 auto_arch = cpu_core2_generic;
634 static cpu_arch_features auto_detect_AMD(x86_cpu_info_t const *info)
636 cpu_arch_features auto_arch = cpu_generic;
638 unsigned family, model;
640 if (info->cpu_family == 0x0F) {
641 family = info->cpu_ext_family + info->cpu_family;
642 model = (info->cpu_ext_model << 4) | info->cpu_model;
644 family = info->cpu_family;
645 model = info->cpu_model;
650 auto_arch = cpu_i486;
654 case 0x00: /* K5 Model 0 */
655 case 0x01: /* K5 Model 1 */
656 case 0x02: /* K5 Model 2 */
657 case 0x03: /* K5 Model 3 */
658 auto_arch = cpu_pentium;
660 case 0x06: /* K6 Model 6 */
661 case 0x07: /* K6 Model 7 */
662 case 0x08: /* K6-2 Model 8 */
663 case 0x09: /* K6-III Model 9 */
664 case 0x0D: /* K6-2+ or K6-III+ */
665 auto_arch = cpu_k6_generic;
667 case 0x0A: /* Geode LX */
668 auto_arch = cpu_geode_generic;
672 auto_arch = cpu_k6_generic;
678 case 0x01: /* Athlon Model 1 */
679 case 0x02: /* Athlon Model 2 */
680 case 0x03: /* Duron Model 3 */
681 case 0x04: /* Athlon Model 4 */
682 case 0x06: /* Athlon MP/Mobile Athlon Model 6 */
683 case 0x07: /* Mobile Duron Model 7 */
684 case 0x08: /* Athlon (TH/AP core) including Geode NX */
685 case 0x0A: /* Athlon (BT core) */
686 default: /* unknown K7 */
687 auto_arch = cpu_athlon_generic;
692 auto_arch = cpu_k8_generic;
695 case 0x11: /* AMD Family 11h */
696 case 0x12: /* AMD Family 12h */
697 case 0x14: /* AMD Family 14h */
698 case 0x15: /* AMD Family 15h */
699 auto_arch = cpu_k10_generic;
719 static void x86_cpuid(cpuid_registers *regs, unsigned level)
721 #if defined(__GNUC__)
722 # if defined(__PIC__) && !defined(__amd64) // GCC cannot handle EBX in PIC
728 : "=a" (regs->r.eax), "=r" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
733 : "=a" (regs->r.eax), "=b" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
737 #elif defined(_MSC_VER)
738 __cpuid(regs->bulk, level);
740 # error CPUID is missing
744 static bool x86_toogle_cpuid(void)
746 unsigned eflags_before = 0;
747 unsigned eflags_after = 0;
749 #if defined(__GNUC__)
751 /* If bit 21 of the EFLAGS register can be changed, the cpuid instruction is available */
756 "xorl $0x00200000, %1\n\t"
761 : "=r" (eflags_before), "=r" (eflags_after) :: "cc"
764 eflags_after = 0x00200000;
766 #elif defined(_MSC_VER)
771 mov eflags_before, eax
777 mov eflags_after, eax
780 eflags_after = 0x00200000;
783 return (eflags_before ^ eflags_after) & 0x00200000;
786 static void autodetect_arch(void)
788 cpu_arch_features auto_arch = cpu_generic;
790 /* We use the cpuid instruction to detect the CPU features */
791 if (x86_toogle_cpuid()) {
792 cpuid_registers regs;
794 x86_cpu_info_t cpu_info;
798 memcpy(&vendorid[0], ®s.r.ebx, 4);
799 memcpy(&vendorid[4], ®s.r.edx, 4);
800 memcpy(&vendorid[8], ®s.r.ecx, 4);
803 /* get processor info and feature bits */
806 cpu_info.cpu_stepping = (regs.r.eax >> 0) & 0x0F;
807 cpu_info.cpu_model = (regs.r.eax >> 4) & 0x0F;
808 cpu_info.cpu_family = (regs.r.eax >> 8) & 0x0F;
809 cpu_info.cpu_type = (regs.r.eax >> 12) & 0x03;
810 cpu_info.cpu_ext_model = (regs.r.eax >> 16) & 0x0F;
811 cpu_info.cpu_ext_family = (regs.r.eax >> 20) & 0xFF;
812 cpu_info.edx_features = regs.r.edx;
813 cpu_info.ecx_features = regs.r.ecx;
814 cpu_info.add_features = regs.r.ebx;
816 if (0 == strcmp(vendorid, "GenuineIntel")) {
817 auto_arch = auto_detect_Intel(&cpu_info);
818 } else if (0 == strcmp(vendorid, "AuthenticAMD")) {
819 auto_arch = auto_detect_AMD(&cpu_info);
820 } else if (0 == strcmp(vendorid, "Geode by NSC")) {
821 auto_arch = cpu_geode_generic;
824 if (cpu_info.edx_features & CPUID_FEAT_EDX_CMOV)
825 auto_arch |= arch_feature_cmov;
826 if (cpu_info.edx_features & CPUID_FEAT_EDX_MMX)
827 auto_arch |= arch_feature_mmx;
828 if (cpu_info.edx_features & CPUID_FEAT_EDX_SSE)
829 auto_arch |= arch_feature_sse1;
830 if (cpu_info.edx_features & CPUID_FEAT_EDX_SSE2)
831 auto_arch |= arch_feature_sse2;
833 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSE3)
834 auto_arch |= arch_feature_sse3;
835 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSSE3)
836 auto_arch |= arch_feature_ssse3;
837 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSE4_1)
838 auto_arch |= arch_feature_sse4_1;
839 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSE4_2)
840 auto_arch |= arch_feature_sse4_2;
841 if (cpu_info.ecx_features & CPUID_FEAT_ECX_POPCNT)
842 auto_arch |= arch_feature_popcnt;
846 opt_arch = auto_arch;
848 #endif /* NATIVE_X86 */
850 static bool flags(cpu_arch_features features, cpu_arch_features flags)
852 return (features & flags) != 0;
855 void ia32_setup_cg_config(void)
857 ia32_code_gen_config_t *const c = &ia32_cg_config;
858 memset(c, 0, sizeof(*c));
863 if (arch == cpu_autodetect)
867 c->optimize_size = opt_size != 0;
868 /* on newer intel cpus mov, pop is often faster than leave although it has a
870 c->use_leave = flags(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
871 /* P4s don't like inc/decs because they only partially write the flags
872 * register which produces false dependencies */
873 c->use_incdec = !flags(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
874 c->use_softfloat = (fpu_arch & IA32_FPU_ARCH_SOFTFLOAT) != 0;
875 c->use_sse2 = (fpu_arch & IA32_FPU_ARCH_SSE2) != 0 && flags(arch, arch_feature_sse2);
876 c->use_ffreep = flags(opt_arch, arch_athlon_plus);
877 c->use_femms = flags(opt_arch, arch_athlon_plus) &&
878 flags(arch, arch_feature_mmx | arch_all_amd);
879 c->use_fucomi = flags(arch, arch_feature_p6_insn);
880 c->use_cmov = flags(arch, arch_feature_cmov);
881 c->use_modeD_moves = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode);
882 c->use_add_esp_4 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size;
883 c->use_add_esp_8 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size;
884 c->use_sub_esp_4 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size;
885 c->use_sub_esp_8 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size;
886 c->use_imul_mem_imm32 = !flags(opt_arch, arch_k8 | arch_k10) || opt_size;
887 c->use_pxor = flags(opt_arch, arch_netburst);
888 c->use_mov_0 = flags(opt_arch, arch_k6) && !opt_size;
889 c->use_short_sex_eax = !flags(opt_arch, arch_k6) || opt_size;
890 c->use_pad_return = flags(opt_arch, arch_athlon_plus) && !opt_size;
891 c->use_bt = flags(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
892 c->use_fisttp = flags(opt_arch & arch, arch_feature_sse3);
893 c->use_sse_prefetch = flags(arch, (arch_feature_3DNowE | arch_feature_sse1));
894 c->use_3dnow_prefetch = flags(arch, arch_feature_3DNow);
895 c->use_popcnt = flags(arch, arch_feature_popcnt);
896 c->use_bswap = (arch & arch_mask) >= arch_i486;
897 c->optimize_cc = opt_cc;
898 c->use_unsafe_floatconv = opt_unsafe_floatconv;
899 c->emit_machcode = emit_machcode;
901 c->function_alignment = arch_costs->function_alignment;
902 c->label_alignment = arch_costs->label_alignment;
903 c->label_alignment_max_skip = arch_costs->label_alignment_max_skip;
905 c->label_alignment_factor =
906 flags(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 :
907 opt_arch & arch_all_amd ? 3 :
911 void ia32_init_architecture(void)
913 lc_opt_entry_t *be_grp, *ia32_grp;
915 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
917 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
918 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
920 lc_opt_add_table(ia32_grp, ia32_architecture_options);