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4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
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9 * packaging of this file.
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12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
29 #include "lc_opts_enum.h"
33 #include "bearch_ia32_t.h"
34 #include "ia32_architecture.h"
39 #if defined(_M_IX86) || defined(_M_X64)
44 #if defined(__i386__) || defined(__x86_64__)
49 ia32_code_gen_config_t ia32_cg_config;
52 * CPU architectures and features.
54 enum cpu_arch_features {
55 arch_generic32 = 0x00000001, /**< no specific architecture */
57 arch_i386 = 0x00000002, /**< i386 architecture */
58 arch_i486 = 0x00000004, /**< i486 architecture */
59 arch_pentium = 0x00000008, /**< Pentium architecture */
60 arch_ppro = 0x00000010, /**< PentiumPro architecture */
61 arch_netburst = 0x00000020, /**< Netburst architecture */
62 arch_nocona = 0x00000040, /**< Nocona architecture */
63 arch_core2 = 0x00000080, /**< Core2 architecture */
64 arch_atom = 0x00000100, /**< Atom architecture */
66 arch_k6 = 0x00000200, /**< k6 architecture */
67 arch_geode = 0x00000400, /**< Geode architecture */
68 arch_athlon = 0x00000800, /**< Athlon architecture */
69 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
70 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
72 arch_mask = 0x00003FFF,
74 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
75 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
77 arch_feature_mmx = 0x00004000, /**< MMX instructions */
78 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
79 arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
80 arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
81 arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
82 arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
83 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
84 arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
85 arch_feature_64bit = 0x00400000, /**< x86_64 support */
86 arch_feature_sse4_1 = 0x00800000, /**< SSE4.1 instructions */
87 arch_feature_sse4_2 = 0x01000000, /**< SSE4.2 instructions */
88 arch_feature_sse4a = 0x02000000, /**< SSE4a instructions */
90 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
91 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
92 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
93 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
94 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
95 arch_sse4_1_insn = arch_feature_sse4_1 | arch_ssse3_insn, /**< SSE4.1 instructions, include SSSE3 */
96 arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */
97 arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */
99 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
100 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
101 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
104 #define FLAGS(x, f) (((x) & (f)) != 0)
109 typedef enum cpu_support {
110 cpu_generic = arch_generic32,
113 cpu_i386 = arch_i386,
114 cpu_i486 = arch_i486,
115 cpu_pentium = arch_pentium,
116 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
117 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
118 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
119 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
120 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
121 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
122 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
123 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
124 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
125 cpu_penryn = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
128 cpu_k6 = arch_k6 | arch_mmx_insn,
129 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
130 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
131 cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_p6_insn,
132 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
133 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
134 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
135 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
136 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse4a_insn,
139 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
140 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
141 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
142 cpu_c3_2 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */
147 static int opt_size = 0;
148 static int emit_machcode = 0;
149 static cpu_support arch = cpu_generic;
150 static cpu_support opt_arch = cpu_generic;
151 static int use_sse2 = 0;
152 static int opt_cc = 1;
153 static int opt_unsafe_floatconv = 0;
155 /* instruction set architectures. */
156 static const lc_opt_enum_int_items_t arch_items[] = {
157 { "i386", cpu_i386 },
158 { "i486", cpu_i486 },
159 { "i586", cpu_pentium },
160 { "pentium", cpu_pentium },
161 { "pentium-mmx", cpu_pentium_mmx },
162 { "i686", cpu_pentium_pro },
163 { "pentiumpro", cpu_pentium_pro },
164 { "pentium2", cpu_pentium_2 },
165 { "p2", cpu_pentium_2 },
166 { "pentium3", cpu_pentium_3 },
167 { "pentium3m", cpu_pentium_3 },
168 { "p3", cpu_pentium_3 },
169 { "pentium-m", cpu_pentium_m },
170 { "pm", cpu_pentium_m },
171 { "pentium4", cpu_pentium_4 },
172 { "pentium4m", cpu_pentium_4 },
173 { "p4", cpu_pentium_4 },
174 { "prescott", cpu_prescott },
175 { "nocona", cpu_nocona },
176 { "merom", cpu_core2 },
177 { "core2", cpu_core2 },
178 { "penryn", cpu_penryn },
181 { "k6-2", cpu_k6_PLUS },
182 { "k6-3", cpu_k6_PLUS },
183 { "geode", cpu_geode },
184 { "athlon", cpu_athlon_old },
185 { "athlon-tbird", cpu_athlon },
186 { "athlon-4", cpu_athlon },
187 { "athlon-xp", cpu_athlon },
188 { "athlon-mp", cpu_athlon },
189 { "athlon64", cpu_athlon64 },
191 { "opteron", cpu_k8 },
192 { "athlon-fx", cpu_k8 },
193 { "k8-sse3", cpu_k8_sse3 },
194 { "opteron-sse3", cpu_k8_sse3 },
196 { "barcelona", cpu_k10 },
197 { "amdfam10", cpu_k10 },
199 { "winchip-c6", cpu_winchip_c6, },
200 { "winchip2", cpu_winchip2 },
202 { "c3-2", cpu_c3_2 },
204 { "generic", cpu_generic },
205 { "generic32", cpu_generic },
208 { "native", cpu_autodetect },
214 static lc_opt_enum_int_var_t arch_var = {
215 (int*) &arch, arch_items
218 static lc_opt_enum_int_var_t opt_arch_var = {
219 (int*) &opt_arch, arch_items
222 static const lc_opt_enum_int_items_t fp_unit_items[] = {
228 static lc_opt_enum_int_var_t fp_unit_var = {
229 &use_sse2, fp_unit_items
232 static const lc_opt_table_entry_t ia32_architecture_options[] = {
233 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
234 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
236 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
238 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
240 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
242 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
243 "optimisations", &opt_unsafe_floatconv, 1),
244 LC_OPT_ENT_BOOL("machcode", "output machine code instead of assembler",
249 typedef struct insn_const {
250 int add_cost; /**< cost of an add instruction */
251 int lea_cost; /**< cost of a lea instruction */
252 int const_shf_cost; /**< cost of a constant shift instruction */
253 int cost_mul_start; /**< starting cost of a multiply instruction */
254 int cost_mul_bit; /**< cost of multiply for every set bit */
255 unsigned function_alignment; /**< logarithm for alignment of function labels */
256 unsigned label_alignment; /**< logarithm for alignment of loops labels */
257 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
260 /* costs for optimizing for size */
261 static const insn_const size_cost = {
262 2, /* cost of an add instruction */
263 3, /* cost of a lea instruction */
264 3, /* cost of a constant shift instruction */
265 4, /* starting cost of a multiply instruction */
266 0, /* cost of multiply for every set bit */
267 0, /* logarithm for alignment of function labels */
268 0, /* logarithm for alignment of loops labels */
269 0, /* maximum skip for alignment of loops labels */
272 /* costs for the i386 */
273 static const insn_const i386_cost = {
274 1, /* cost of an add instruction */
275 1, /* cost of a lea instruction */
276 3, /* cost of a constant shift instruction */
277 9, /* starting cost of a multiply instruction */
278 1, /* cost of multiply for every set bit */
279 2, /* logarithm for alignment of function labels */
280 2, /* logarithm for alignment of loops labels */
281 3, /* maximum skip for alignment of loops labels */
284 /* costs for the i486 */
285 static const insn_const i486_cost = {
286 1, /* cost of an add instruction */
287 1, /* cost of a lea instruction */
288 2, /* cost of a constant shift instruction */
289 12, /* starting cost of a multiply instruction */
290 1, /* cost of multiply for every set bit */
291 4, /* logarithm for alignment of function labels */
292 4, /* logarithm for alignment of loops labels */
293 15, /* maximum skip for alignment of loops labels */
296 /* costs for the Pentium */
297 static const insn_const pentium_cost = {
298 1, /* cost of an add instruction */
299 1, /* cost of a lea instruction */
300 1, /* cost of a constant shift instruction */
301 11, /* starting cost of a multiply instruction */
302 0, /* cost of multiply for every set bit */
303 4, /* logarithm for alignment of function labels */
304 4, /* logarithm for alignment of loops labels */
305 7, /* maximum skip for alignment of loops labels */
308 /* costs for the Pentium Pro */
309 static const insn_const pentiumpro_cost = {
310 1, /* cost of an add instruction */
311 1, /* cost of a lea instruction */
312 1, /* cost of a constant shift instruction */
313 4, /* starting cost of a multiply instruction */
314 0, /* cost of multiply for every set bit */
315 4, /* logarithm for alignment of function labels */
316 4, /* logarithm for alignment of loops labels */
317 10, /* maximum skip for alignment of loops labels */
320 /* costs for the K6 */
321 static const insn_const k6_cost = {
322 1, /* cost of an add instruction */
323 2, /* cost of a lea instruction */
324 1, /* cost of a constant shift instruction */
325 3, /* starting cost of a multiply instruction */
326 0, /* cost of multiply for every set bit */
327 5, /* logarithm for alignment of function labels */
328 5, /* logarithm for alignment of loops labels */
329 7, /* maximum skip for alignment of loops labels */
332 /* costs for the Geode */
333 static const insn_const geode_cost = {
334 1, /* cost of an add instruction */
335 1, /* cost of a lea instruction */
336 1, /* cost of a constant shift instruction */
337 7, /* starting cost of a multiply instruction */
338 0, /* cost of multiply for every set bit */
339 0, /* logarithm for alignment of function labels */
340 0, /* logarithm for alignment of loops labels */
341 0, /* maximum skip for alignment of loops labels */
344 /* costs for the Athlon */
345 static const insn_const athlon_cost = {
346 1, /* cost of an add instruction */
347 2, /* cost of a lea instruction */
348 1, /* cost of a constant shift instruction */
349 5, /* starting cost of a multiply instruction */
350 0, /* cost of multiply for every set bit */
351 4, /* logarithm for alignment of function labels */
352 4, /* logarithm for alignment of loops labels */
353 7, /* maximum skip for alignment of loops labels */
356 /* costs for the Opteron/K8 */
357 static const insn_const k8_cost = {
358 1, /* cost of an add instruction */
359 2, /* cost of a lea instruction */
360 1, /* cost of a constant shift instruction */
361 3, /* starting cost of a multiply instruction */
362 0, /* cost of multiply for every set bit */
364 4, /* logarithm for alignment of function labels */
365 4, /* logarithm for alignment of loops labels */
366 7, /* maximum skip for alignment of loops labels */
374 /* costs for the K10 */
375 static const insn_const k10_cost = {
376 1, /* cost of an add instruction */
377 2, /* cost of a lea instruction */
378 1, /* cost of a constant shift instruction */
379 3, /* starting cost of a multiply instruction */
380 0, /* cost of multiply for every set bit */
381 5, /* logarithm for alignment of function labels */
382 5, /* logarithm for alignment of loops labels */
383 7, /* maximum skip for alignment of loops labels */
386 /* costs for the Pentium 4 */
387 static const insn_const netburst_cost = {
388 1, /* cost of an add instruction */
389 3, /* cost of a lea instruction */
390 4, /* cost of a constant shift instruction */
391 15, /* starting cost of a multiply instruction */
392 0, /* cost of multiply for every set bit */
393 4, /* logarithm for alignment of function labels */
394 4, /* logarithm for alignment of loops labels */
395 7, /* maximum skip for alignment of loops labels */
398 /* costs for the Nocona and Core */
399 static const insn_const nocona_cost = {
400 1, /* cost of an add instruction */
401 1, /* cost of a lea instruction */
402 1, /* cost of a constant shift instruction */
403 10, /* starting cost of a multiply instruction */
404 0, /* cost of multiply for every set bit */
405 4, /* logarithm for alignment of function labels */
406 4, /* logarithm for alignment of loops labels */
407 7, /* maximum skip for alignment of loops labels */
410 /* costs for the Core2 */
411 static const insn_const core2_cost = {
412 1, /* cost of an add instruction */
413 1, /* cost of a lea instruction */
414 1, /* cost of a constant shift instruction */
415 3, /* starting cost of a multiply instruction */
416 0, /* cost of multiply for every set bit */
417 4, /* logarithm for alignment of function labels */
418 4, /* logarithm for alignment of loops labels */
419 10, /* maximum skip for alignment of loops labels */
422 /* costs for the generic32 */
423 static const insn_const generic32_cost = {
424 1, /* cost of an add instruction */
425 2, /* cost of a lea instruction */
426 1, /* cost of a constant shift instruction */
427 4, /* starting cost of a multiply instruction */
428 0, /* cost of multiply for every set bit */
429 4, /* logarithm for alignment of function labels */
430 4, /* logarithm for alignment of loops labels */
431 7, /* maximum skip for alignment of loops labels */
434 static const insn_const *arch_costs = &generic32_cost;
436 static void set_arch_costs(void)
439 arch_costs = &size_cost;
442 switch (opt_arch & arch_mask) {
443 case arch_i386: arch_costs = &i386_cost; break;
444 case arch_i486: arch_costs = &i486_cost; break;
445 case arch_pentium: arch_costs = &pentium_cost; break;
446 case arch_ppro: arch_costs = &pentiumpro_cost; break;
447 case arch_netburst: arch_costs = &netburst_cost; break;
448 case arch_nocona: arch_costs = &nocona_cost; break;
449 case arch_core2: arch_costs = &core2_cost; break;
450 case arch_k6: arch_costs = &k6_cost; break;
451 case arch_geode: arch_costs = &geode_cost; break;
452 case arch_athlon: arch_costs = &athlon_cost; break;
453 case arch_k8: arch_costs = &k8_cost; break;
454 case arch_k10: arch_costs = &k10_cost; break;
456 case arch_generic32: arch_costs = &generic32_cost; break;
460 /* Evaluate the costs of an instruction. */
461 int ia32_evaluate_insn(insn_kind kind, const ir_mode *mode, ir_tarval *tv)
467 cost = arch_costs->cost_mul_start;
468 if (arch_costs->cost_mul_bit > 0) {
469 char *bitstr = get_tarval_bitpattern(tv);
472 for (i = 0; bitstr[i] != '\0'; ++i) {
473 if (bitstr[i] == '1') {
474 cost += arch_costs->cost_mul_bit;
479 if (get_mode_size_bits(mode) <= 32)
481 /* 64bit mul supported, approx 4times of a 32bit mul*/
484 /* lea is only supported for 32 bit */
485 if (get_mode_size_bits(mode) <= 32)
486 return arch_costs->lea_cost;
487 /* in 64bit mode, the Lea cost are at wort 2 shifts and one add */
488 return 2 * arch_costs->add_cost + 2 * (2 * arch_costs->const_shf_cost);
491 if (get_mode_size_bits(mode) <= 32)
492 return arch_costs->add_cost;
493 /* 64bit add/sub supported, double the cost */
494 return 2 * arch_costs->add_cost;
496 if (get_mode_size_bits(mode) <= 32)
497 return arch_costs->const_shf_cost;
498 /* 64bit shift supported, double the cost */
499 return 2 * arch_costs->const_shf_cost;
501 return arch_costs->add_cost;
507 /* auto detection code only works if we're on an x86 cpu obviously */
509 typedef struct x86_cpu_info_t {
510 unsigned char cpu_stepping;
511 unsigned char cpu_model;
512 unsigned char cpu_family;
513 unsigned char cpu_type;
514 unsigned char cpu_ext_model;
515 unsigned char cpu_ext_family;
516 unsigned edx_features;
517 unsigned ecx_features;
518 unsigned add_features;
521 static cpu_support auto_detect_Intel(x86_cpu_info_t const *info)
523 cpu_support auto_arch = cpu_generic;
525 unsigned family = (info->cpu_ext_family << 4) | info->cpu_family;
526 unsigned model = (info->cpu_ext_model << 4) | info->cpu_model;
530 auto_arch = arch_i486;
533 auto_arch = arch_pentium;
537 case 0x01: /* PentiumPro */
538 case 0x03: /* Pentium II Model 3 */
539 case 0x05: /* Pentium II Model 5 */
540 case 0x06: /* Celeron Model 6 */
541 case 0x07: /* Pentium III Model 7 */
542 case 0x08: /* Pentium III Model 8 */
543 case 0x09: /* Pentium M Model 9 */
544 case 0x0A: /* Pentium III Model 0A */
545 case 0x0B: /* Pentium III Model 0B */
546 case 0x0D: /* Pentium M Model 0D */
547 auto_arch = arch_ppro;
549 case 0x0E: /* Core Model 0E */
550 auto_arch = arch_ppro;
552 case 0x0F: /* Core2 Model 0F */
553 case 0x15: /* Intel EP80579 */
554 case 0x16: /* Celeron Model 16 */
555 case 0x17: /* Core2 Model 17 */
556 auto_arch = arch_core2;
565 case 0x00: /* Pentium 4 Model 00 */
566 case 0x01: /* Pentium 4 Model 01 */
567 case 0x02: /* Pentium 4 Model 02 */
568 case 0x03: /* Pentium 4 Model 03 */
569 case 0x04: /* Pentium 4 Model 04 */
570 case 0x06: /* Pentium 4 Model 06 */
571 auto_arch = arch_netburst;
573 case 0x1A: /* Core i7 */
574 auto_arch = arch_core2;
576 case 0x1C: /* Atom */
577 auto_arch = arch_atom;
579 case 0x1D: /* Xeon MP */
580 auto_arch = arch_core2;
592 if (info->edx_features & (1<<23)) auto_arch |= arch_feature_mmx;
593 if (info->edx_features & (1<<25)) auto_arch |= arch_feature_sse1;
594 if (info->edx_features & (1<<26)) auto_arch |= arch_feature_sse2;
596 if (info->ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3;
597 if (info->ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3;
598 if (info->ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1;
599 if (info->ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2;
604 static cpu_support auto_detect_AMD(x86_cpu_info_t const *info) {
605 cpu_support auto_arch = cpu_generic;
607 unsigned family, model;
609 if (info->cpu_family == 0x0F) {
610 family = (info->cpu_ext_family << 4) | info->cpu_family;
611 model = (info->cpu_ext_model << 4) | info->cpu_model;
613 family = info->cpu_family;
614 model = info->cpu_model;
619 auto_arch = arch_i486;
623 case 0x00: /* K5 Model 0 */
624 case 0x01: /* K5 Model 1 */
625 case 0x02: /* K5 Model 2 */
626 case 0x03: /* K5 Model 3 */
627 auto_arch = arch_pentium;
629 case 0x06: /* K6 Model 6 */
630 case 0x07: /* K6 Model 7 */
631 case 0x08: /* K6-2 Model 8 */
632 case 0x09: /* K6-III Model 9 */
633 case 0x0D: /* K6-2+ or K6-III+ */
637 auto_arch = arch_geode;
646 case 0x01: /* Athlon Model 1 */
647 case 0x02: /* Athlon Model 2 */
648 case 0x03: /* Duron Model 3 */
649 case 0x04: /* Athlon Model 4 */
650 case 0x06: /* Athlon MP/Mobile Athlon Model 6 */
651 case 0x07: /* Mobile Duron Model 7 */
652 case 0x08: /* Athlon (TH/AP core) */
653 case 0x0A: /* Athlon (BT core) */
654 auto_arch = arch_athlon;
658 auto_arch = arch_athlon;
666 auto_arch = arch_k10;
673 if (info->edx_features & (1<<23)) auto_arch |= arch_feature_mmx;
674 if (info->edx_features & (1<<25)) auto_arch |= arch_feature_sse1;
675 if (info->edx_features & (1<<26)) auto_arch |= arch_feature_sse2;
677 if (info->ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3;
678 if (info->ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3;
679 if (info->ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1;
680 if (info->ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2;
695 static void x86_cpuid(cpuid_registers *regs, unsigned level)
697 #if defined(__GNUC__)
699 : "=a" (regs->r.eax), "=b" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
702 #elif defined(_MSC_VER)
703 __cpuid(regs->bulk, level);
707 static int x86_toogle_cpuid(void)
709 unsigned eflags_before = 0, eflags_after = 0;
711 #if defined(__GNUC__)
713 /* If bit 21 of the EFLAGS register can be changed, the cpuid instruction is available */
718 "xorl $0x00200000, %1\n\t"
723 : "=r" (eflags_before), "=r" (eflags_after) :: "cc"
726 /* cpuid always available on 64bit */
729 #elif defined(_MSC_VER)
734 mov eflags_before, eax
740 mov eflags_after, eax
746 return (eflags_before ^ eflags_after) & 0x00200000;
749 static void autodetect_arch(void)
751 cpu_support auto_arch = cpu_generic;
753 /* We use the cpuid instruction to detect the CPU features */
754 if (x86_toogle_cpuid()) {
755 cpuid_registers regs;
756 unsigned highest_level;
758 x86_cpu_info_t cpu_info;
762 highest_level = regs.r.eax;
763 memcpy(&vendorid[0], ®s.r.ebx, 4);
764 memcpy(&vendorid[4], ®s.r.edx, 4);
765 memcpy(&vendorid[8], ®s.r.ecx, 4);
768 /* get processor info and feature bits */
771 cpu_info.cpu_stepping = (regs.r.eax >> 0) & 0x0F;
772 cpu_info.cpu_model = (regs.r.eax >> 4) & 0x0F;
773 cpu_info.cpu_family = (regs.r.eax >> 8) & 0x0F;
774 cpu_info.cpu_type = (regs.r.eax >> 12) & 0x03;
775 cpu_info.cpu_ext_model = (regs.r.eax >> 16) & 0x0F;
776 cpu_info.cpu_ext_family = (regs.r.eax >> 20) & 0xFF;
777 cpu_info.edx_features = regs.r.edx;
778 cpu_info.ecx_features = regs.r.ecx;
779 cpu_info.add_features = regs.r.ebx;
781 if (0 == strcmp(vendorid, "GenuineIntel")) {
782 auto_arch = auto_detect_Intel(&cpu_info);
783 } else if (0 == strcmp(vendorid, "AuthenticAMD")) {
784 auto_arch = auto_detect_AMD(&cpu_info);
789 opt_arch = auto_arch;
791 #endif /* NATIVE_X86 */
793 void ia32_setup_cg_config(void)
795 ia32_code_gen_config_t *const c = &ia32_cg_config;
796 memset(c, 0, sizeof(*c));
801 if (arch == cpu_autodetect)
805 c->optimize_size = opt_size != 0;
806 /* on newer intel cpus mov, pop is often faster than leave although it has a
808 c->use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
809 /* P4s don't like inc/decs because they only partially write the flags
810 * register which produces false dependencies */
811 c->use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
812 c->use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
813 c->use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
814 c->use_ftst = !FLAGS(arch, arch_feature_p6_insn);
815 /* valgrind can't cope with femms yet and the usefulness of the optimization
816 * is questionable anyway */
818 c->use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
819 FLAGS(arch, arch_feature_mmx | arch_all_amd);
823 c->use_fucomi = FLAGS(arch, arch_feature_p6_insn);
824 c->use_cmov = FLAGS(arch, arch_feature_p6_insn);
825 c->use_modeD_moves = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode);
826 c->use_add_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size;
827 c->use_add_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size;
828 c->use_sub_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size;
829 c->use_sub_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size;
830 c->use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
831 c->use_pxor = FLAGS(opt_arch, arch_netburst);
832 c->use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
833 c->use_short_sex_eax = !FLAGS(opt_arch, arch_k6) && !opt_size;
834 c->use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
835 c->use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
836 c->use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3);
837 c->use_sse_prefetch = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1));
838 c->use_3dnow_prefetch = FLAGS(arch, arch_feature_3DNow);
839 c->use_popcnt = FLAGS(arch, (arch_feature_sse4_2 | arch_feature_sse4a));
840 c->use_i486 = (arch & arch_mask) >= arch_i486;
841 c->optimize_cc = opt_cc;
842 c->use_unsafe_floatconv = opt_unsafe_floatconv;
843 c->emit_machcode = emit_machcode;
845 c->function_alignment = arch_costs->function_alignment;
846 c->label_alignment = arch_costs->label_alignment;
847 c->label_alignment_max_skip = arch_costs->label_alignment_max_skip;
849 c->label_alignment_factor =
850 FLAGS(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 :
851 opt_arch & arch_all_amd ? 3 :
855 void ia32_init_architecture(void)
857 lc_opt_entry_t *be_grp, *ia32_grp;
859 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
861 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
862 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
864 lc_opt_add_table(ia32_grp, ia32_architecture_options);