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15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
31 #include "lc_opts_enum.h"
35 #include "bearch_ia32_t.h"
36 #include "ia32_architecture.h"
38 ia32_code_gen_config_t ia32_cg_config;
43 enum cpu_arch_features {
44 arch_feature_intel = 0x80000000, /**< Intel CPU */
45 arch_feature_amd = 0x40000000, /**< AMD CPU */
46 arch_feature_p6 = 0x20000000, /**< P6 instructions */
47 arch_feature_mmx = 0x10000000, /**< MMX instructions */
48 arch_feature_sse1 = 0x08000000 | arch_feature_mmx, /**< SSE1 instructions, include MMX */
49 arch_feature_sse2 = 0x04000000 | arch_feature_sse1, /**< SSE2 instructions, include SSE1 */
50 arch_feature_sse3 = 0x02000000 | arch_feature_sse2, /**< SSE3 instructions, include SSE2 */
51 arch_feature_ssse3 = 0x01000000 | arch_feature_sse3, /**< SSSE3 instructions, include SSE3 */
52 arch_feature_3DNow = 0x00800000, /**< 3DNow! instructions */
53 arch_feature_3DNowE = 0x00400000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
54 arch_feature_netburst = 0x00200000 | arch_feature_intel, /**< Netburst architecture */
55 arch_feature_64bit = 0x00100000 | arch_feature_sse2, /**< x86_64 support, include SSE2 */
67 arch_pentium = 3 | arch_feature_intel,
68 arch_pentium_mmx = 4 | arch_feature_intel | arch_feature_mmx,
69 arch_pentium_pro = 5 | arch_feature_intel | arch_feature_p6,
70 arch_pentium_2 = 6 | arch_feature_intel | arch_feature_p6 | arch_feature_mmx,
71 arch_pentium_3 = 7 | arch_feature_intel | arch_feature_p6 | arch_feature_sse1,
72 arch_pentium_4 = 8 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse2,
73 arch_prescott = 9 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse3,
74 arch_nocona = 10 | arch_feature_netburst | arch_feature_p6 | arch_feature_64bit | arch_feature_sse3,
75 arch_pentium_m = 11 | arch_feature_intel | arch_feature_p6 | arch_feature_sse2,
76 arch_core = 12 | arch_feature_intel | arch_feature_p6 | arch_feature_sse3,
77 arch_core2 = 13 | arch_feature_intel | arch_feature_p6 | arch_feature_64bit | arch_feature_ssse3,
80 arch_k6 = 14 | arch_feature_amd | arch_feature_mmx,
81 arch_geode = 15 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE,
82 arch_k6_2 = 16 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
83 arch_k6_3 = 17 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
84 arch_athlon = 18 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE | arch_feature_p6,
85 arch_athlon_xp = 19 | arch_feature_amd | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6,
86 arch_opteron = 20 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,
87 arch_k10 = 21 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,
90 arch_winchip_c6 = 22 | arch_feature_mmx,
91 arch_winchip2 = 23 | arch_feature_mmx | arch_feature_3DNow,
92 arch_c3 = 24 | arch_feature_mmx | arch_feature_3DNow,
93 arch_c3_2 = 25 | arch_feature_sse1, /* really no 3DNow! */
96 /** checks for l <= x <= h */
97 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
99 /** returns true if it's Intel architecture */
100 #define ARCH_INTEL(x) (((x) & arch_feature_intel) != 0)
102 /** returns true if it's AMD architecture */
103 #define ARCH_AMD(x) (((x) & arch_feature_amd) != 0)
105 /** return true if it's a Athlon/Opteron */
106 #define ARCH_K8(x) _IN_RANGE((x), arch_athlon, arch_opteron)
108 /** return true if it's a Athlon or newer */
109 #define ARCH_ATHLON_PLUS(x) _IN_RANGE((x), arch_athlon, arch_k10)
111 /** return true if the CPU has MMX support */
112 #define ARCH_MMX(x) (((x) & arch_feature_mmx) != 0)
114 /** return true if the CPU has 3DNow! support */
115 #define ARCH_3DNow(x) (((x) & arch_feature_3DNow) != 0)
117 /** return true if the CPU has P6 features (CMOV) */
118 #define IS_P6_ARCH(x) (((x) & arch_feature_p6) != 0)
120 /** return true if the CPU has the NetBurst architecture */
121 #define IS_NETBURST_ARCH(x) (((x) & arch_feature_netburst) != 0)
123 static cpu_support arch = arch_generic;
124 static cpu_support opt_arch = arch_pentium_4;
125 static int use_sse2 = 0;
126 static int opt_cc = 1;
127 static int opt_unsafe_floatconv = 0;
129 /* instruction set architectures. */
130 static const lc_opt_enum_int_items_t arch_items[] = {
131 { "i386", arch_i386, },
132 { "i486", arch_i486, },
133 { "pentium", arch_pentium, },
134 { "i586", arch_pentium, },
135 { "pentiumpro", arch_pentium_pro, },
136 { "i686", arch_pentium_pro, },
137 { "pentiummmx", arch_pentium_mmx, },
138 { "pentium2", arch_pentium_2, },
139 { "p2", arch_pentium_2, },
140 { "pentium3", arch_pentium_3, },
141 { "p3", arch_pentium_3, },
142 { "pentium4", arch_pentium_4, },
143 { "p4", arch_pentium_4, },
144 { "prescott", arch_prescott, },
145 { "nocona", arch_nocona, },
146 { "pentiumm", arch_pentium_m, },
147 { "pm", arch_pentium_m, },
151 { "core", arch_core, },
152 { "yonah", arch_core, },
154 * core2 CPUs: Conroe (XE, L), Allendale, Merom (XE),
155 * Kentsfield (XE), Yorkfield XE, Penryn, Wolfdale, Yorkfield
158 { "merom", arch_core2, },
159 { "core2", arch_core2, },
161 { "k6-2", arch_k6_2, },
162 { "k6-3", arch_k6_2, },
163 { "geode", arch_geode, },
164 { "athlon", arch_athlon, },
165 { "athlon-xp", arch_athlon_xp, },
166 { "athlon-mp", arch_athlon_xp, },
167 { "athlon-4", arch_athlon_xp, },
168 { "athlon64", arch_opteron, },
169 { "k8", arch_opteron, },
170 { "k10", arch_k10, },
171 { "opteron", arch_opteron, },
172 { "generic", arch_generic, },
176 static lc_opt_enum_int_var_t arch_var = {
177 (int*) &arch, arch_items
180 static lc_opt_enum_int_var_t opt_arch_var = {
181 (int*) &opt_arch, arch_items
184 static const lc_opt_enum_int_items_t fp_unit_items[] = {
190 static lc_opt_enum_int_var_t fp_unit_var = {
191 &use_sse2, fp_unit_items
194 static const lc_opt_table_entry_t ia32_architecture_options[] = {
195 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
197 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
199 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
201 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
203 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
204 "optimisations", &opt_unsafe_floatconv, 1),
208 typedef struct insn_const {
209 int add_cost; /**< cost of an add instruction */
210 int lea_cost; /**< cost of a lea instruction */
211 int const_shf_cost; /**< cost of a constant shift instruction */
212 int cost_mul_start; /**< starting cost of a multiply instruction */
213 int cost_mul_bit; /**< cost of multiply for every set bit */
216 /* costs for the i386 */
217 static const insn_const i386_cost = {
218 1, /* cost of an add instruction */
219 1, /* cost of a lea instruction */
220 3, /* cost of a constant shift instruction */
221 9, /* starting cost of a multiply instruction */
222 1 /* cost of multiply for every set bit */
225 /* costs for the i486 */
226 static const insn_const i486_cost = {
227 1, /* cost of an add instruction */
228 1, /* cost of a lea instruction */
229 2, /* cost of a constant shift instruction */
230 12, /* starting cost of a multiply instruction */
231 1 /* cost of multiply for every set bit */
234 /* costs for the Pentium */
235 static const insn_const pentium_cost = {
236 1, /* cost of an add instruction */
237 1, /* cost of a lea instruction */
238 1, /* cost of a constant shift instruction */
239 11, /* starting cost of a multiply instruction */
240 0 /* cost of multiply for every set bit */
243 /* costs for the Pentium Pro */
244 static const insn_const pentiumpro_cost = {
245 1, /* cost of an add instruction */
246 1, /* cost of a lea instruction */
247 1, /* cost of a constant shift instruction */
248 4, /* starting cost of a multiply instruction */
249 0 /* cost of multiply for every set bit */
252 /* costs for the K6 */
253 static const insn_const k6_cost = {
254 1, /* cost of an add instruction */
255 2, /* cost of a lea instruction */
256 1, /* cost of a constant shift instruction */
257 3, /* starting cost of a multiply instruction */
258 0 /* cost of multiply for every set bit */
261 /* costs for the Geode */
262 static const insn_const geode_cost = {
263 1, /* cost of an add instruction */
264 1, /* cost of a lea instruction */
265 1, /* cost of a constant shift instruction */
266 7, /* starting cost of a multiply instruction */
267 0 /* cost of multiply for every set bit */
270 /* costs for the Athlon */
271 static const insn_const athlon_cost = {
272 1, /* cost of an add instruction */
273 2, /* cost of a lea instruction */
274 1, /* cost of a constant shift instruction */
275 5, /* starting cost of a multiply instruction */
276 0 /* cost of multiply for every set bit */
279 /* costs for the Opteron/K8/K10 */
280 static const insn_const opteron_cost = {
281 1, /* cost of an add instruction */
282 2, /* cost of a lea instruction */
283 1, /* cost of a constant shift instruction */
284 3, /* starting cost of a multiply instruction */
285 0 /* cost of multiply for every set bit */
288 /* costs for the Pentium 4 */
289 static const insn_const pentium4_cost = {
290 1, /* cost of an add instruction */
291 3, /* cost of a lea instruction */
292 4, /* cost of a constant shift instruction */
293 15, /* starting cost of a multiply instruction */
294 0 /* cost of multiply for every set bit */
297 /* costs for the Nocona and Core */
298 static const insn_const nocona_cost = {
299 1, /* cost of an add instruction */
300 1, /* cost of a lea instruction */
301 1, /* cost of a constant shift instruction */
302 10, /* starting cost of a multiply instruction */
303 0 /* cost of multiply for every set bit */
306 /* costs for the Core2 */
307 static const insn_const core2_cost = {
308 1, /* cost of an add instruction */
309 1, /* cost of a lea instruction */
310 1, /* cost of a constant shift instruction */
311 3, /* starting cost of a multiply instruction */
312 0 /* cost of multiply for every set bit */
315 /* costs for the generic */
316 static const insn_const generic_cost = {
317 1, /* cost of an add instruction */
318 2, /* cost of a lea instruction */
319 1, /* cost of a constant shift instruction */
320 4, /* starting cost of a multiply instruction */
321 0 /* cost of multiply for every set bit */
324 static const insn_const *arch_costs = &generic_cost;
326 static void set_arch_costs(void)
330 arch_costs = &i386_cost;
333 arch_costs = &i486_cost;
336 case arch_pentium_mmx:
337 arch_costs = &pentium_cost;
339 case arch_pentium_pro:
342 arch_costs = &pentiumpro_cost;
345 arch_costs = &pentium4_cost;
348 arch_costs = &pentiumpro_cost;
353 arch_costs = &nocona_cost;
356 arch_costs = &core2_cost;
360 arch_costs = &k6_cost;
363 arch_costs = &geode_cost;
367 arch_costs = &athlon_cost;
371 arch_costs = &opteron_cost;
375 arch_costs = &generic_cost;
380 * Evaluate a given simple instruction.
382 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
387 cost = arch_costs->cost_mul_start;
388 if (arch_costs->cost_mul_bit > 0) {
389 char *bitstr = get_tarval_bitpattern(tv);
392 for (i = 0; bitstr[i] != '\0'; ++i) {
393 if (bitstr[i] == '1') {
394 cost += arch_costs->cost_mul_bit;
401 return arch_costs->lea_cost;
404 return arch_costs->add_cost;
406 return arch_costs->const_shf_cost;
408 return arch_costs->add_cost;
414 void ia32_setup_cg_config(void)
416 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
418 /* on newer intel cpus mov, pop is often faster then leave although it has a
420 ia32_cg_config.use_leave = !ARCH_INTEL(opt_arch)
421 || !IS_P6_ARCH(opt_arch);
422 /* P4s don't like inc/decs because they only partially write the flags
423 register which produces false dependencies */
424 ia32_cg_config.use_incdec = !IS_NETBURST_ARCH(opt_arch) && (opt_arch != arch_generic);
425 ia32_cg_config.use_sse2 = use_sse2;
426 ia32_cg_config.use_ffreep = ARCH_ATHLON_PLUS(opt_arch);
427 ia32_cg_config.use_ftst = !IS_P6_ARCH(arch);
428 ia32_cg_config.use_femms = ARCH_ATHLON_PLUS(opt_arch)
429 && ARCH_MMX(arch) && ARCH_AMD(arch);
430 ia32_cg_config.use_fucomi = IS_P6_ARCH(arch);
431 ia32_cg_config.use_cmov = IS_P6_ARCH(arch);
432 ia32_cg_config.use_add_esp_4 = ARCH_ATHLON_PLUS(opt_arch) || (opt_arch == arch_geode) ||
433 IS_NETBURST_ARCH(opt_arch) || (opt_arch == arch_core2) ||
434 (opt_arch == arch_generic);
435 ia32_cg_config.use_add_esp_8 = ARCH_ATHLON_PLUS(opt_arch) || (opt_arch == arch_geode) ||
436 IS_P6_ARCH(opt_arch) || IS_NETBURST_ARCH(opt_arch) ||
437 (opt_arch == arch_core2) || (opt_arch == arch_generic) ||
438 (opt_arch == arch_i386) || (opt_arch == arch_i486);
439 ia32_cg_config.use_sub_esp_4 = ARCH_ATHLON_PLUS(opt_arch) || IS_P6_ARCH(opt_arch) ||
440 IS_NETBURST_ARCH(opt_arch) || (opt_arch == arch_core2) ||
441 (opt_arch == arch_generic);
442 ia32_cg_config.use_sub_esp_8 = ARCH_ATHLON_PLUS(opt_arch) ||
443 IS_P6_ARCH(opt_arch) || IS_NETBURST_ARCH(opt_arch) ||
444 (opt_arch == arch_core2) || (opt_arch == arch_generic) ||
445 (opt_arch == arch_i386) || (opt_arch == arch_i486);
446 ia32_cg_config.optimize_cc = opt_cc;
447 ia32_cg_config.use_unsafe_floatconv = opt_unsafe_floatconv;
449 if(opt_arch == arch_i386) {
450 ia32_cg_config.function_alignment = 2;
451 } else if(opt_arch == arch_i486) {
452 ia32_cg_config.function_alignment = 4;
453 } else if(opt_arch == arch_k6) {
454 ia32_cg_config.function_alignment = 5;
455 ia32_cg_config.label_alignment = 5;
457 ia32_cg_config.function_alignment = 4;
458 ia32_cg_config.label_alignment = 4;
461 if(opt_arch == arch_i386 || opt_arch == arch_i486) {
462 ia32_cg_config.label_alignment_factor = -1;
463 } else if(ARCH_AMD(opt_arch)) {
464 ia32_cg_config.label_alignment_factor = 3;
466 ia32_cg_config.label_alignment_factor = 2;
472 void ia32_init_architecture(void)
474 lc_opt_entry_t *be_grp, *ia32_grp;
476 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
478 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
479 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
481 lc_opt_add_table(ia32_grp, ia32_architecture_options);