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15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
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22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
31 #include "lc_opts_enum.h"
35 #include "bearch_ia32_t.h"
36 #include "ia32_architecture.h"
38 ia32_code_gen_config_t ia32_cg_config;
43 enum cpu_arch_features {
44 arch_feature_intel = 0x80000000, /**< Intel CPU */
45 arch_feature_amd = 0x40000000, /**< AMD CPU */
46 arch_feature_p6 = 0x20000000, /**< P6 instructions */
47 arch_feature_mmx = 0x10000000, /**< MMX instructions */
48 arch_feature_sse1 = 0x08000000 | arch_feature_mmx, /**< SSE1 instructions, include MMX */
49 arch_feature_sse2 = 0x04000000 | arch_feature_sse1, /**< SSE2 instructions, include SSE1 */
50 arch_feature_sse3 = 0x02000000 | arch_feature_sse2, /**< SSE3 instructions, include SSE2 */
51 arch_feature_ssse3 = 0x01000000 | arch_feature_sse3, /**< SSSE3 instructions, include SSE3 */
52 arch_feature_3DNow = 0x00800000, /**< 3DNow! instructions */
53 arch_feature_3DNowE = 0x00400000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
54 arch_feature_netburst = 0x00200000 | arch_feature_intel, /**< Netburst architecture */
55 arch_feature_64bit = 0x00100000 | arch_feature_sse2, /**< x86_64 support, include SSE2 */
67 arch_pentium = 3 | arch_feature_intel,
68 arch_pentium_mmx = 4 | arch_feature_intel | arch_feature_mmx,
69 arch_pentium_pro = 5 | arch_feature_intel | arch_feature_p6,
70 arch_pentium_2 = 6 | arch_feature_intel | arch_feature_p6 | arch_feature_mmx,
71 arch_pentium_3 = 7 | arch_feature_intel | arch_feature_p6 | arch_feature_sse1,
72 arch_pentium_4 = 8 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse2,
73 arch_pentium_m = 9 | arch_feature_intel | arch_feature_p6 | arch_feature_sse2,
74 arch_core = 10 | arch_feature_intel | arch_feature_p6 | arch_feature_sse3,
75 arch_prescott = 11 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse3,
76 arch_core2 = 12 | arch_feature_intel | arch_feature_p6 | arch_feature_64bit | arch_feature_ssse3,
79 arch_k6 = 13 | arch_feature_amd | arch_feature_mmx,
80 arch_k6_2 = 14 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
81 arch_k6_3 = 15 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
82 arch_athlon = 16 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE | arch_feature_p6,
83 arch_athlon_xp = 17 | arch_feature_amd | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6,
84 arch_opteron = 18 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,
87 arch_winchip_c6 = 19 | arch_feature_mmx,
88 arch_winchip2 = 20 | arch_feature_mmx | arch_feature_3DNow,
89 arch_c3 = 21 | arch_feature_mmx | arch_feature_3DNow,
90 arch_c3_2 = 22 | arch_feature_sse1, /* really no 3DNow! */
93 /** checks for l <= x <= h */
94 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
96 /** returns true if it's Intel architecture */
97 #define ARCH_INTEL(x) (((x) & arch_feature_intel) != 0)
99 /** returns true if it's AMD architecture */
100 #define ARCH_AMD(x) (((x) & arch_feature_amd) != 0)
102 /** return true if it's a Athlon/Opteron */
103 #define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron)
105 /** return true if the CPU has MMX support */
106 #define ARCH_MMX(x) (((x) & arch_feature_mmx) != 0)
108 /** return true if the CPU has 3DNow! support */
109 #define ARCH_3DNow(x) (((x) & arch_feature_3DNow) != 0)
111 /** return true if the CPU has P6 features (CMOV) */
112 #define IS_P6_ARCH(x) (((x) & arch_feature_p6) != 0)
114 static cpu_support arch = arch_generic;
115 static cpu_support opt_arch = arch_pentium_4;
116 static int use_sse2 = 0;
117 static int opt_cc = 1;
118 static int opt_unsafe_floatconv = 0;
120 /* instruction set architectures. */
121 static const lc_opt_enum_int_items_t arch_items[] = {
122 { "i386", arch_i386, },
123 { "i486", arch_i486, },
124 { "pentium", arch_pentium, },
125 { "i586", arch_pentium, },
126 { "pentiumpro", arch_pentium_pro, },
127 { "i686", arch_pentium_pro, },
128 { "pentiummmx", arch_pentium_mmx, },
129 { "pentium2", arch_pentium_2, },
130 { "p2", arch_pentium_2, },
131 { "pentium3", arch_pentium_3, },
132 { "p3", arch_pentium_3, },
133 { "pentium4", arch_pentium_4, },
134 { "p4", arch_pentium_4, },
135 { "prescott", arch_pentium_4, },
136 { "nocona", arch_pentium_4, },
137 { "pentiumm", arch_pentium_m, },
138 { "pm", arch_pentium_m, },
142 { "core", arch_core, },
143 { "yonah", arch_core, },
145 * core2 CPUs: Conroe (XE, L), Allendale, Merom (XE),
146 * Kentsfield (XE), Yorkfield XE, Penryn, Wolfdale, Yorkfield
148 { "merom", arch_core2, },
149 { "core2", arch_core2, },
151 { "k6-2", arch_k6_2, },
152 { "k6-3", arch_k6_2, },
153 { "athlon", arch_athlon, },
154 { "athlon-xp", arch_athlon_xp, },
155 { "athlon-mp", arch_athlon_xp, },
156 { "athlon-4", arch_athlon_xp, },
157 { "athlon64", arch_opteron, },
158 { "k8", arch_opteron, },
159 { "opteron", arch_opteron, },
160 { "generic", arch_generic, },
164 static lc_opt_enum_int_var_t arch_var = {
165 (int*) &arch, arch_items
168 static lc_opt_enum_int_var_t opt_arch_var = {
169 (int*) &opt_arch, arch_items
172 static const lc_opt_enum_int_items_t fp_unit_items[] = {
178 static lc_opt_enum_int_var_t fp_unit_var = {
179 &use_sse2, fp_unit_items
182 static const lc_opt_table_entry_t ia32_architecture_options[] = {
183 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
185 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
187 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
189 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
191 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
192 "optimisations", &opt_unsafe_floatconv, 1),
196 typedef struct insn_const {
197 int add_cost; /**< cost of an add instruction */
198 int lea_cost; /**< cost of a lea instruction */
199 int const_shf_cost; /**< cost of a constant shift instruction */
200 int cost_mul_start; /**< starting cost of a multiply instruction */
201 int cost_mul_bit; /**< cost of multiply for every set bit */
204 /* costs for the i386 */
205 static const insn_const i386_cost = {
206 1, /* cost of an add instruction */
207 1, /* cost of a lea instruction */
208 2, /* cost of a constant shift instruction */
209 6, /* starting cost of a multiply instruction */
210 1 /* cost of multiply for every set bit */
213 /* costs for the i486 */
214 static const insn_const i486_cost = {
215 1, /* cost of an add instruction */
216 1, /* cost of a lea instruction */
217 2, /* cost of a constant shift instruction */
218 12, /* starting cost of a multiply instruction */
219 1 /* cost of multiply for every set bit */
222 /* costs for the Pentium */
223 static const insn_const pentium_cost = {
224 1, /* cost of an add instruction */
225 1, /* cost of a lea instruction */
226 1, /* cost of a constant shift instruction */
227 11, /* starting cost of a multiply instruction */
228 0 /* cost of multiply for every set bit */
231 /* costs for the Pentium Pro */
232 static const insn_const pentiumpro_cost = {
233 1, /* cost of an add instruction */
234 1, /* cost of a lea instruction */
235 1, /* cost of a constant shift instruction */
236 4, /* starting cost of a multiply instruction */
237 0 /* cost of multiply for every set bit */
240 /* costs for the K6 */
241 static const insn_const k6_cost = {
242 1, /* cost of an add instruction */
243 2, /* cost of a lea instruction */
244 1, /* cost of a constant shift instruction */
245 3, /* starting cost of a multiply instruction */
246 0 /* cost of multiply for every set bit */
249 /* costs for the Athlon */
250 static const insn_const athlon_cost = {
251 1, /* cost of an add instruction */
252 2, /* cost of a lea instruction */
253 1, /* cost of a constant shift instruction */
254 5, /* starting cost of a multiply instruction */
255 0 /* cost of multiply for every set bit */
258 /* costs for the Pentium 4 */
259 static const insn_const pentium4_cost = {
260 1, /* cost of an add instruction */
261 3, /* cost of a lea instruction */
262 4, /* cost of a constant shift instruction */
263 15, /* starting cost of a multiply instruction */
264 0 /* cost of multiply for every set bit */
267 /* costs for the Core */
268 static const insn_const core_cost = {
269 1, /* cost of an add instruction */
270 1, /* cost of a lea instruction */
271 1, /* cost of a constant shift instruction */
272 10, /* starting cost of a multiply instruction */
273 0 /* cost of multiply for every set bit */
276 /* costs for the generic */
277 static const insn_const generic_cost = {
278 1, /* cost of an add instruction */
279 2, /* cost of a lea instruction */
280 1, /* cost of a constant shift instruction */
281 4, /* starting cost of a multiply instruction */
282 0 /* cost of multiply for every set bit */
285 static const insn_const *arch_costs = &generic_cost;
287 static void set_arch_costs(void)
291 arch_costs = &i386_cost;
294 arch_costs = &i486_cost;
297 case arch_pentium_mmx:
298 arch_costs = &pentium_cost;
300 case arch_pentium_pro:
303 arch_costs = &pentiumpro_cost;
306 arch_costs = &pentium4_cost;
309 arch_costs = &pentiumpro_cost;
312 arch_costs = &core_cost;
315 arch_costs = &pentium4_cost;
318 arch_costs = &core_cost;
322 arch_costs = &k6_cost;
327 arch_costs = &athlon_cost;
331 arch_costs = &generic_cost;
336 * Evaluate a given simple instruction.
338 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
343 cost = arch_costs->cost_mul_start;
344 if (arch_costs->cost_mul_bit > 0) {
345 char *bitstr = get_tarval_bitpattern(tv);
348 for (i = 0; bitstr[i] != '\0'; ++i) {
349 if (bitstr[i] == '1') {
350 cost += arch_costs->cost_mul_bit;
357 return arch_costs->lea_cost;
360 return arch_costs->add_cost;
362 return arch_costs->const_shf_cost;
364 return arch_costs->add_cost;
372 void ia32_setup_cg_config(void)
374 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
376 /* on newer intel cpus mov, pop is often faster then leave although it has a
378 ia32_cg_config.use_leave = !ARCH_INTEL(opt_arch)
379 || !IS_P6_ARCH(opt_arch);
380 /* P4s don't like inc/decs because they only partially write the flags
381 register which produces false dependencies */
382 ia32_cg_config.use_incdec = (opt_arch != arch_pentium_4);
383 ia32_cg_config.use_sse2 = use_sse2;
384 ia32_cg_config.use_ffreep = ARCH_ATHLON(opt_arch);
385 ia32_cg_config.use_ftst = !IS_P6_ARCH(arch);
386 ia32_cg_config.use_femms = ARCH_ATHLON(opt_arch)
387 && ARCH_MMX(arch) && ARCH_AMD(arch);
388 ia32_cg_config.use_fucomi = IS_P6_ARCH(arch);
389 ia32_cg_config.use_cmov = IS_P6_ARCH(arch);
390 ia32_cg_config.optimize_cc = opt_cc;
391 ia32_cg_config.use_unsafe_floatconv = opt_unsafe_floatconv;
393 if(opt_arch == arch_i386) {
394 ia32_cg_config.function_alignment = 2;
395 } else if(opt_arch == arch_i486) {
396 ia32_cg_config.function_alignment = 4;
397 } else if(opt_arch == arch_k6) {
398 ia32_cg_config.function_alignment = 5;
399 ia32_cg_config.label_alignment = 5;
401 ia32_cg_config.function_alignment = 4;
402 ia32_cg_config.label_alignment = 4;
405 if(opt_arch == arch_i386 || opt_arch == arch_i486) {
406 ia32_cg_config.label_alignment_factor = -1;
407 } else if(ARCH_AMD(opt_arch)) {
408 ia32_cg_config.label_alignment_factor = 3;
410 ia32_cg_config.label_alignment_factor = 2;
416 void ia32_init_architecture(void)
418 lc_opt_entry_t *be_grp, *ia32_grp;
420 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
422 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
423 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
425 lc_opt_add_table(ia32_grp, ia32_architecture_options);