2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
31 #include "lc_opts_enum.h"
35 #include "bearch_ia32_t.h"
36 #include "ia32_architecture.h"
38 ia32_code_gen_config_t ia32_cg_config;
43 enum cpu_arch_features {
44 arch_feature_intel = 0x80000000, /**< Intel CPU */
45 arch_feature_amd = 0x40000000, /**< AMD CPU */
46 arch_feature_p6 = 0x20000000, /**< P6 instructions */
47 arch_feature_mmx = 0x10000000, /**< MMX instructions */
48 arch_feature_sse1 = 0x08000000 | arch_feature_mmx, /**< SSE1 instructions, include MMX */
49 arch_feature_sse2 = 0x04000000 | arch_feature_sse1, /**< SSE2 instructions, include SSE1 */
50 arch_feature_sse3 = 0x02000000 | arch_feature_sse2, /**< SSE3 instructions, include SSE2 */
51 arch_feature_ssse3 = 0x01000000 | arch_feature_sse3, /**< SSSE3 instructions, include SSE3 */
52 arch_feature_3DNow = 0x00800000, /**< 3DNow! instructions */
53 arch_feature_3DNowE = 0x00400000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
54 arch_feature_netburst = 0x00200000 | arch_feature_intel, /**< Netburst architecture */
55 arch_feature_64bit = 0x00100000 | arch_feature_sse2, /**< x86_64 support, include SSE2 */
67 arch_pentium = 3 | arch_feature_intel,
68 arch_pentium_mmx = 4 | arch_feature_intel | arch_feature_mmx,
69 arch_pentium_pro = 5 | arch_feature_intel | arch_feature_p6,
70 arch_pentium_2 = 6 | arch_feature_intel | arch_feature_p6 | arch_feature_mmx,
71 arch_pentium_3 = 7 | arch_feature_intel | arch_feature_p6 | arch_feature_sse1,
72 arch_pentium_4 = 8 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse2,
73 arch_prescott = 9 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse3,
74 arch_nocona = 10 | arch_feature_netburst | arch_feature_p6 | arch_feature_64bit | arch_feature_sse3,
75 arch_pentium_m = 11 | arch_feature_intel | arch_feature_p6 | arch_feature_sse2,
76 arch_core = 12 | arch_feature_intel | arch_feature_p6 | arch_feature_sse3,
77 arch_core2 = 13 | arch_feature_intel | arch_feature_p6 | arch_feature_64bit | arch_feature_ssse3,
80 arch_k6 = 14 | arch_feature_amd | arch_feature_mmx,
81 arch_geode = 15 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE,
82 arch_k6_2 = 16 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
83 arch_k6_3 = 17 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
84 arch_athlon = 18 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE | arch_feature_p6,
85 arch_athlon_xp = 19 | arch_feature_amd | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6,
86 arch_opteron = 20 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,
89 arch_winchip_c6 = 21 | arch_feature_mmx,
90 arch_winchip2 = 22 | arch_feature_mmx | arch_feature_3DNow,
91 arch_c3 = 23 | arch_feature_mmx | arch_feature_3DNow,
92 arch_c3_2 = 24 | arch_feature_sse1, /* really no 3DNow! */
95 /** checks for l <= x <= h */
96 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
98 /** returns true if it's Intel architecture */
99 #define ARCH_INTEL(x) (((x) & arch_feature_intel) != 0)
101 /** returns true if it's AMD architecture */
102 #define ARCH_AMD(x) (((x) & arch_feature_amd) != 0)
104 /** return true if it's a Athlon/Opteron */
105 #define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron)
107 /** return true if the CPU has MMX support */
108 #define ARCH_MMX(x) (((x) & arch_feature_mmx) != 0)
110 /** return true if the CPU has 3DNow! support */
111 #define ARCH_3DNow(x) (((x) & arch_feature_3DNow) != 0)
113 /** return true if the CPU has P6 features (CMOV) */
114 #define IS_P6_ARCH(x) (((x) & arch_feature_p6) != 0)
116 /** return true if the CPU has the NetBurst architecture */
117 #define IS_NETBURST_ARCH(x) (((x) & arch_feature_netburst) != 0)
119 static cpu_support arch = arch_generic;
120 static cpu_support opt_arch = arch_pentium_4;
121 static int use_sse2 = 0;
122 static int opt_cc = 1;
123 static int opt_unsafe_floatconv = 0;
125 /* instruction set architectures. */
126 static const lc_opt_enum_int_items_t arch_items[] = {
127 { "i386", arch_i386, },
128 { "i486", arch_i486, },
129 { "pentium", arch_pentium, },
130 { "i586", arch_pentium, },
131 { "pentiumpro", arch_pentium_pro, },
132 { "i686", arch_pentium_pro, },
133 { "pentiummmx", arch_pentium_mmx, },
134 { "pentium2", arch_pentium_2, },
135 { "p2", arch_pentium_2, },
136 { "pentium3", arch_pentium_3, },
137 { "p3", arch_pentium_3, },
138 { "pentium4", arch_pentium_4, },
139 { "p4", arch_pentium_4, },
140 { "prescott", arch_prescott, },
141 { "nocona", arch_nocona, },
142 { "pentiumm", arch_pentium_m, },
143 { "pm", arch_pentium_m, },
147 { "core", arch_core, },
148 { "yonah", arch_core, },
150 * core2 CPUs: Conroe (XE, L), Allendale, Merom (XE),
151 * Kentsfield (XE), Yorkfield XE, Penryn, Wolfdale, Yorkfield
154 { "merom", arch_core2, },
155 { "core2", arch_core2, },
157 { "k6-2", arch_k6_2, },
158 { "k6-3", arch_k6_2, },
159 { "geode", arch_geode, },
160 { "athlon", arch_athlon, },
161 { "athlon-xp", arch_athlon_xp, },
162 { "athlon-mp", arch_athlon_xp, },
163 { "athlon-4", arch_athlon_xp, },
164 { "athlon64", arch_opteron, },
165 { "k8", arch_opteron, },
166 { "k10", arch_opteron, },
167 { "opteron", arch_opteron, },
168 { "generic", arch_generic, },
172 static lc_opt_enum_int_var_t arch_var = {
173 (int*) &arch, arch_items
176 static lc_opt_enum_int_var_t opt_arch_var = {
177 (int*) &opt_arch, arch_items
180 static const lc_opt_enum_int_items_t fp_unit_items[] = {
186 static lc_opt_enum_int_var_t fp_unit_var = {
187 &use_sse2, fp_unit_items
190 static const lc_opt_table_entry_t ia32_architecture_options[] = {
191 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
193 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
195 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
197 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
199 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
200 "optimisations", &opt_unsafe_floatconv, 1),
204 typedef struct insn_const {
205 int add_cost; /**< cost of an add instruction */
206 int lea_cost; /**< cost of a lea instruction */
207 int const_shf_cost; /**< cost of a constant shift instruction */
208 int cost_mul_start; /**< starting cost of a multiply instruction */
209 int cost_mul_bit; /**< cost of multiply for every set bit */
212 /* costs for the i386 */
213 static const insn_const i386_cost = {
214 1, /* cost of an add instruction */
215 1, /* cost of a lea instruction */
216 3, /* cost of a constant shift instruction */
217 9, /* starting cost of a multiply instruction */
218 1 /* cost of multiply for every set bit */
221 /* costs for the i486 */
222 static const insn_const i486_cost = {
223 1, /* cost of an add instruction */
224 1, /* cost of a lea instruction */
225 2, /* cost of a constant shift instruction */
226 12, /* starting cost of a multiply instruction */
227 1 /* cost of multiply for every set bit */
230 /* costs for the Pentium */
231 static const insn_const pentium_cost = {
232 1, /* cost of an add instruction */
233 1, /* cost of a lea instruction */
234 1, /* cost of a constant shift instruction */
235 11, /* starting cost of a multiply instruction */
236 0 /* cost of multiply for every set bit */
239 /* costs for the Pentium Pro */
240 static const insn_const pentiumpro_cost = {
241 1, /* cost of an add instruction */
242 1, /* cost of a lea instruction */
243 1, /* cost of a constant shift instruction */
244 4, /* starting cost of a multiply instruction */
245 0 /* cost of multiply for every set bit */
248 /* costs for the K6 */
249 static const insn_const k6_cost = {
250 1, /* cost of an add instruction */
251 2, /* cost of a lea instruction */
252 1, /* cost of a constant shift instruction */
253 3, /* starting cost of a multiply instruction */
254 0 /* cost of multiply for every set bit */
257 /* costs for the Geode */
258 static const insn_const geode_cost = {
259 1, /* cost of an add instruction */
260 1, /* cost of a lea instruction */
261 1, /* cost of a constant shift instruction */
262 7, /* starting cost of a multiply instruction */
263 0 /* cost of multiply for every set bit */
266 /* costs for the Athlon */
267 static const insn_const athlon_cost = {
268 1, /* cost of an add instruction */
269 2, /* cost of a lea instruction */
270 1, /* cost of a constant shift instruction */
271 5, /* starting cost of a multiply instruction */
272 0 /* cost of multiply for every set bit */
275 /* costs for the K8 */
276 static const insn_const k8_cost = {
277 1, /* cost of an add instruction */
278 2, /* cost of a lea instruction */
279 1, /* cost of a constant shift instruction */
280 3, /* starting cost of a multiply instruction */
281 0 /* cost of multiply for every set bit */
284 /* costs for the Pentium 4 */
285 static const insn_const pentium4_cost = {
286 1, /* cost of an add instruction */
287 3, /* cost of a lea instruction */
288 4, /* cost of a constant shift instruction */
289 15, /* starting cost of a multiply instruction */
290 0 /* cost of multiply for every set bit */
293 /* costs for the Nocona and Core */
294 static const insn_const nocona_cost = {
295 1, /* cost of an add instruction */
296 1, /* cost of a lea instruction */
297 1, /* cost of a constant shift instruction */
298 10, /* starting cost of a multiply instruction */
299 0 /* cost of multiply for every set bit */
302 /* costs for the Core2 */
303 static const insn_const core2_cost = {
304 1, /* cost of an add instruction */
305 1, /* cost of a lea instruction */
306 1, /* cost of a constant shift instruction */
307 3, /* starting cost of a multiply instruction */
308 0 /* cost of multiply for every set bit */
311 /* costs for the generic */
312 static const insn_const generic_cost = {
313 1, /* cost of an add instruction */
314 2, /* cost of a lea instruction */
315 1, /* cost of a constant shift instruction */
316 4, /* starting cost of a multiply instruction */
317 0 /* cost of multiply for every set bit */
320 static const insn_const *arch_costs = &generic_cost;
322 static void set_arch_costs(void)
326 arch_costs = &i386_cost;
329 arch_costs = &i486_cost;
332 case arch_pentium_mmx:
333 arch_costs = &pentium_cost;
335 case arch_pentium_pro:
338 arch_costs = &pentiumpro_cost;
341 arch_costs = &pentium4_cost;
344 arch_costs = &pentiumpro_cost;
349 arch_costs = &nocona_cost;
352 arch_costs = &core2_cost;
356 arch_costs = &k6_cost;
359 arch_costs = &geode_cost;
364 arch_costs = &athlon_cost;
368 arch_costs = &generic_cost;
373 * Evaluate a given simple instruction.
375 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
380 cost = arch_costs->cost_mul_start;
381 if (arch_costs->cost_mul_bit > 0) {
382 char *bitstr = get_tarval_bitpattern(tv);
385 for (i = 0; bitstr[i] != '\0'; ++i) {
386 if (bitstr[i] == '1') {
387 cost += arch_costs->cost_mul_bit;
394 return arch_costs->lea_cost;
397 return arch_costs->add_cost;
399 return arch_costs->const_shf_cost;
401 return arch_costs->add_cost;
409 void ia32_setup_cg_config(void)
411 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
413 /* on newer intel cpus mov, pop is often faster then leave although it has a
415 ia32_cg_config.use_leave = !ARCH_INTEL(opt_arch)
416 || !IS_P6_ARCH(opt_arch);
417 /* P4s don't like inc/decs because they only partially write the flags
418 register which produces false dependencies */
419 ia32_cg_config.use_incdec = !IS_NETBURST_ARCH(opt_arch) && (opt_arch != arch_generic);
420 ia32_cg_config.use_sse2 = use_sse2;
421 ia32_cg_config.use_ffreep = ARCH_ATHLON(opt_arch);
422 ia32_cg_config.use_ftst = !IS_P6_ARCH(arch);
423 ia32_cg_config.use_femms = ARCH_ATHLON(opt_arch)
424 && ARCH_MMX(arch) && ARCH_AMD(arch);
425 ia32_cg_config.use_fucomi = IS_P6_ARCH(arch);
426 ia32_cg_config.use_cmov = IS_P6_ARCH(arch);
427 ia32_cg_config.optimize_cc = opt_cc;
428 ia32_cg_config.use_unsafe_floatconv = opt_unsafe_floatconv;
430 if(opt_arch == arch_i386) {
431 ia32_cg_config.function_alignment = 2;
432 } else if(opt_arch == arch_i486) {
433 ia32_cg_config.function_alignment = 4;
434 } else if(opt_arch == arch_k6) {
435 ia32_cg_config.function_alignment = 5;
436 ia32_cg_config.label_alignment = 5;
438 ia32_cg_config.function_alignment = 4;
439 ia32_cg_config.label_alignment = 4;
442 if(opt_arch == arch_i386 || opt_arch == arch_i486) {
443 ia32_cg_config.label_alignment_factor = -1;
444 } else if(ARCH_AMD(opt_arch)) {
445 ia32_cg_config.label_alignment_factor = 3;
447 ia32_cg_config.label_alignment_factor = 2;
453 void ia32_init_architecture(void)
455 lc_opt_entry_t *be_grp, *ia32_grp;
457 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
459 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
460 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
462 lc_opt_add_table(ia32_grp, ia32_architecture_options);