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22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
31 #include "lc_opts_enum.h"
35 #include "bearch_ia32_t.h"
36 #include "ia32_architecture.h"
38 ia32_code_gen_config_t ia32_cg_config;
43 enum cpu_arch_features {
44 arch_feature_intel = 0x80000000, /**< Intel CPU */
45 arch_feature_amd = 0x40000000, /**< AMD CPU */
46 arch_feature_p6 = 0x20000000, /**< P6 instructions */
47 arch_feature_mmx = 0x10000000, /**< MMX instructions */
48 arch_feature_sse1 = 0x08000000 | arch_feature_mmx, /**< SSE1 instructions, include MMX */
49 arch_feature_sse2 = 0x04000000 | arch_feature_sse1, /**< SSE2 instructions, include SSE1 */
50 arch_feature_sse3 = 0x02000000 | arch_feature_sse2, /**< SSE3 instructions, include SSE2 */
51 arch_feature_ssse3 = 0x01000000 | arch_feature_sse3, /**< SSSE3 instructions, include SSE3 */
52 arch_feature_3DNow = 0x00800000, /**< 3DNow! instructions */
53 arch_feature_3DNowE = 0x00400000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
54 arch_feature_netburst = 0x00200000 | arch_feature_intel, /**< Netburst architecture */
55 arch_feature_64bit = 0x00100000 | arch_feature_sse2, /**< x86_64 support, include SSE2 */
67 arch_pentium = 3 | arch_feature_intel,
68 arch_pentium_mmx = 4 | arch_feature_intel | arch_feature_mmx,
69 arch_pentium_pro = 5 | arch_feature_intel | arch_feature_p6,
70 arch_pentium_2 = 6 | arch_feature_intel | arch_feature_p6 | arch_feature_mmx,
71 arch_pentium_3 = 7 | arch_feature_intel | arch_feature_p6 | arch_feature_sse1,
72 arch_pentium_4 = 8 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse2,
73 arch_pentium_m = 9 | arch_feature_intel | arch_feature_p6 | arch_feature_sse2,
74 arch_core = 10 | arch_feature_intel | arch_feature_p6 | arch_feature_sse3,
75 arch_prescott = 11 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse3,
76 arch_core2 = 12 | arch_feature_intel | arch_feature_p6 | arch_feature_64bit | arch_feature_ssse3,
79 arch_k6 = 13 | arch_feature_amd | arch_feature_mmx,
80 arch_k6_2 = 14 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
81 arch_k6_3 = 15 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
82 arch_athlon = 16 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE | arch_feature_p6,
83 arch_athlon_xp = 17 | arch_feature_amd | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6,
84 arch_opteron = 18 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,
87 arch_winchip_c6 = 19 | arch_feature_mmx,
88 arch_winchip2 = 20 | arch_feature_mmx | arch_feature_3DNow,
89 arch_c3 = 21 | arch_feature_mmx | arch_feature_3DNow,
90 arch_c3_2 = 22 | arch_feature_sse1, /* really no 3DNow! */
93 /** checks for l <= x <= h */
94 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
96 /** returns true if it's Intel architecture */
97 #define ARCH_INTEL(x) (((x) & arch_feature_intel) != 0)
99 /** returns true if it's AMD architecture */
100 #define ARCH_AMD(x) (((x) & arch_feature_amd) != 0)
102 /** return true if it's a Athlon/Opteron */
103 #define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron)
105 /** return true if the CPU has MMX support */
106 #define ARCH_MMX(x) (((x) & arch_feature_mmx) != 0)
108 /** return true if the CPU has 3DNow! support */
109 #define ARCH_3DNow(x) (((x) & arch_feature_3DNow) != 0)
111 /** return true if the CPU has P6 features (CMOV) */
112 #define IS_P6_ARCH(x) (((x) & arch_feature_p6) != 0)
114 static cpu_support arch = arch_generic;
115 static cpu_support opt_arch = arch_pentium_4;
116 static int use_sse2 = 0;
117 static int opt_cc = 1;
118 static int opt_unsafe_floatconv = 0;
120 /* instruction set architectures. */
121 static const lc_opt_enum_int_items_t arch_items[] = {
122 { "i386", arch_i386, },
123 { "i486", arch_i486, },
124 { "pentium", arch_pentium, },
125 { "i586", arch_pentium, },
126 { "pentiumpro", arch_pentium_pro, },
127 { "i686", arch_pentium_pro, },
128 { "pentiummmx", arch_pentium_mmx, },
129 { "pentium2", arch_pentium_2, },
130 { "p2", arch_pentium_2, },
131 { "pentium3", arch_pentium_3, },
132 { "p3", arch_pentium_3, },
133 { "pentium4", arch_pentium_4, },
134 { "p4", arch_pentium_4, },
135 { "prescott", arch_pentium_4, },
136 { "pentiumm", arch_pentium_m, },
137 { "pm", arch_pentium_m, },
138 { "core", arch_core, },
139 { "yonah", arch_core, },
140 { "merom", arch_core2, },
141 { "core2", arch_core2, },
143 { "k6-2", arch_k6_2, },
144 { "k6-3", arch_k6_2, },
145 { "athlon", arch_athlon, },
146 { "athlon-xp", arch_athlon_xp, },
147 { "athlon-mp", arch_athlon_xp, },
148 { "athlon-4", arch_athlon_xp, },
149 { "athlon64", arch_opteron, },
150 { "k8", arch_opteron, },
151 { "opteron", arch_opteron, },
152 { "generic", arch_generic, },
156 static lc_opt_enum_int_var_t arch_var = {
157 (int*) &arch, arch_items
160 static lc_opt_enum_int_var_t opt_arch_var = {
161 (int*) &opt_arch, arch_items
164 static const lc_opt_enum_int_items_t fp_unit_items[] = {
170 static lc_opt_enum_int_var_t fp_unit_var = {
171 &use_sse2, fp_unit_items
174 static const lc_opt_table_entry_t ia32_architecture_options[] = {
175 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
177 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
179 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
181 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
183 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
184 "optimisations", &opt_unsafe_floatconv, 1),
188 typedef struct insn_const {
189 int add_cost; /**< cost of an add instruction */
190 int lea_cost; /**< cost of a lea instruction */
191 int const_shf_cost; /**< cost of a constant shift instruction */
192 int cost_mul_start; /**< starting cost of a multiply instruction */
193 int cost_mul_bit; /**< cost of multiply for every set bit */
196 /* costs for the i386 */
197 static const insn_const i386_cost = {
198 1, /* cost of an add instruction */
199 1, /* cost of a lea instruction */
200 2, /* cost of a constant shift instruction */
201 6, /* starting cost of a multiply instruction */
202 1 /* cost of multiply for every set bit */
205 /* costs for the i486 */
206 static const insn_const i486_cost = {
207 1, /* cost of an add instruction */
208 1, /* cost of a lea instruction */
209 2, /* cost of a constant shift instruction */
210 12, /* starting cost of a multiply instruction */
211 1 /* cost of multiply for every set bit */
214 /* costs for the Pentium */
215 static const insn_const pentium_cost = {
216 1, /* cost of an add instruction */
217 1, /* cost of a lea instruction */
218 1, /* cost of a constant shift instruction */
219 11, /* starting cost of a multiply instruction */
220 0 /* cost of multiply for every set bit */
223 /* costs for the Pentium Pro */
224 static const insn_const pentiumpro_cost = {
225 1, /* cost of an add instruction */
226 1, /* cost of a lea instruction */
227 1, /* cost of a constant shift instruction */
228 4, /* starting cost of a multiply instruction */
229 0 /* cost of multiply for every set bit */
232 /* costs for the K6 */
233 static const insn_const k6_cost = {
234 1, /* cost of an add instruction */
235 2, /* cost of a lea instruction */
236 1, /* cost of a constant shift instruction */
237 3, /* starting cost of a multiply instruction */
238 0 /* cost of multiply for every set bit */
241 /* costs for the Athlon */
242 static const insn_const athlon_cost = {
243 1, /* cost of an add instruction */
244 2, /* cost of a lea instruction */
245 1, /* cost of a constant shift instruction */
246 5, /* starting cost of a multiply instruction */
247 0 /* cost of multiply for every set bit */
250 /* costs for the Pentium 4 */
251 static const insn_const pentium4_cost = {
252 1, /* cost of an add instruction */
253 3, /* cost of a lea instruction */
254 4, /* cost of a constant shift instruction */
255 15, /* starting cost of a multiply instruction */
256 0 /* cost of multiply for every set bit */
259 /* costs for the Core */
260 static const insn_const core_cost = {
261 1, /* cost of an add instruction */
262 1, /* cost of a lea instruction */
263 1, /* cost of a constant shift instruction */
264 10, /* starting cost of a multiply instruction */
265 0 /* cost of multiply for every set bit */
268 /* costs for the generic */
269 static const insn_const generic_cost = {
270 1, /* cost of an add instruction */
271 2, /* cost of a lea instruction */
272 1, /* cost of a constant shift instruction */
273 4, /* starting cost of a multiply instruction */
274 0 /* cost of multiply for every set bit */
277 static const insn_const *arch_costs = &generic_cost;
279 static void set_arch_costs(void)
283 arch_costs = &i386_cost;
286 arch_costs = &i486_cost;
289 case arch_pentium_mmx:
290 arch_costs = &pentium_cost;
292 case arch_pentium_pro:
295 arch_costs = &pentiumpro_cost;
298 arch_costs = &pentium4_cost;
301 arch_costs = &pentiumpro_cost;
304 arch_costs = &core_cost;
307 arch_costs = &pentium4_cost;
310 arch_costs = &core_cost;
314 arch_costs = &k6_cost;
319 arch_costs = &athlon_cost;
323 arch_costs = &generic_cost;
328 * Evaluate a given simple instruction.
330 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
335 cost = arch_costs->cost_mul_start;
336 if (arch_costs->cost_mul_bit > 0) {
337 char *bitstr = get_tarval_bitpattern(tv);
340 for (i = 0; bitstr[i] != '\0'; ++i) {
341 if (bitstr[i] == '1') {
342 cost += arch_costs->cost_mul_bit;
349 return arch_costs->lea_cost;
352 return arch_costs->add_cost;
354 return arch_costs->const_shf_cost;
356 return arch_costs->add_cost;
364 void ia32_setup_cg_config(void)
366 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
368 /* on newer intel cpus mov, pop is often faster then leave although it has a
370 ia32_cg_config.use_leave = !ARCH_INTEL(opt_arch)
371 || !IS_P6_ARCH(opt_arch);
372 /* P4s don't like inc/decs because they only partially write the flags
373 register which produces false dependencies */
374 ia32_cg_config.use_incdec = (opt_arch != arch_pentium_4);
375 ia32_cg_config.use_sse2 = use_sse2;
376 ia32_cg_config.use_ffreep = ARCH_ATHLON(opt_arch);
377 ia32_cg_config.use_ftst = !IS_P6_ARCH(arch);
378 ia32_cg_config.use_femms = ARCH_ATHLON(opt_arch)
379 && ARCH_MMX(arch) && ARCH_AMD(arch);
380 ia32_cg_config.use_fucomi = IS_P6_ARCH(arch);
381 ia32_cg_config.use_cmov = IS_P6_ARCH(arch);
382 ia32_cg_config.optimize_cc = opt_cc;
383 ia32_cg_config.use_unsafe_floatconv = opt_unsafe_floatconv;
385 if(opt_arch == arch_i386) {
386 ia32_cg_config.function_alignment = 2;
387 } else if(opt_arch == arch_i486) {
388 ia32_cg_config.function_alignment = 4;
389 } else if(opt_arch == arch_k6) {
390 ia32_cg_config.function_alignment = 5;
391 ia32_cg_config.label_alignment = 5;
393 ia32_cg_config.function_alignment = 4;
394 ia32_cg_config.label_alignment = 4;
397 if(opt_arch == arch_i386 || opt_arch == arch_i486) {
398 ia32_cg_config.label_alignment_factor = -1;
399 } else if(ARCH_AMD(opt_arch)) {
400 ia32_cg_config.label_alignment_factor = 3;
402 ia32_cg_config.label_alignment_factor = 2;
408 void ia32_init_architecture(void)
410 lc_opt_entry_t *be_grp, *ia32_grp;
412 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
414 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
415 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
417 lc_opt_add_table(ia32_grp, ia32_architecture_options);