2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
31 #include "lc_opts_enum.h"
35 #include "bearch_ia32_t.h"
36 #include "ia32_architecture.h"
38 ia32_code_gen_config_t ia32_cg_config;
41 * CPU architectures and features.
43 enum cpu_arch_features {
44 arch_generic32 = 0x00000001, /**< no specific architecture */
46 arch_i386 = 0x00000002, /**< i386 architecture */
47 arch_i486 = 0x00000004, /**< i486 architecture */
48 arch_pentium = 0x00000008, /**< Pentium architecture */
49 arch_ppro = 0x00000010, /**< PentiumPro architecture */
50 arch_netburst = 0x00000020, /**< Netburst architecture */
51 arch_nocona = 0x00000040, /**< Nocona architecture */
52 arch_core2 = 0x00000080, /**< Core2 architecture */
53 arch_atom = 0x00000100, /**< Atom architecture */
55 arch_k6 = 0x00000200, /**< k6 architecture */
56 arch_geode = 0x00000400, /**< Geode architecture */
57 arch_athlon = 0x00000800, /**< Athlon architecture */
58 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
59 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
61 arch_mask = 0x00003FFF,
63 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
64 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
66 arch_feature_mmx = 0x00004000, /**< MMX instructions */
67 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
68 arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
69 arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
70 arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
71 arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
72 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
73 arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
74 arch_feature_64bit = 0x00400000, /**< x86_64 support */
76 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
77 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
78 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
79 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
80 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
82 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
83 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
84 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
87 #define FLAGS(x, f) (((x) & (f)) != 0)
93 cpu_generic = arch_generic32,
98 cpu_pentium = arch_pentium,
99 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
100 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
101 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
102 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
103 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
104 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
105 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
106 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
107 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
110 cpu_k6 = arch_k6 | arch_mmx_insn,
111 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
112 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
113 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
114 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
115 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
116 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
117 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
120 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
121 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
122 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
123 cpu_c3_2 = arch_ppro | arch_sse1_insn, /* really no 3DNow! */
126 static int opt_size = 0;
127 static cpu_support arch = cpu_generic;
128 static cpu_support opt_arch = cpu_generic;
129 static int use_sse2 = 0;
130 static int opt_cc = 1;
131 static int opt_unsafe_floatconv = 0;
133 /* instruction set architectures. */
134 static const lc_opt_enum_int_items_t arch_items[] = {
135 { "i386", cpu_i386 },
136 { "i486", cpu_i486 },
137 { "i586", cpu_pentium },
138 { "pentium", cpu_pentium },
139 { "pentium-mmx", cpu_pentium_mmx },
140 { "i686", cpu_pentium_pro },
141 { "pentiumpro", cpu_pentium_pro },
142 { "pentium2", cpu_pentium_2 },
143 { "p2", cpu_pentium_2 },
144 { "pentium3", cpu_pentium_3 },
145 { "pentium3m", cpu_pentium_3 },
146 { "p3", cpu_pentium_3 },
147 { "pentium-m", cpu_pentium_m },
148 { "pm", cpu_pentium_m },
149 { "pentium4", cpu_pentium_4 },
150 { "pentium4m", cpu_pentium_4 },
151 { "p4", cpu_pentium_4 },
152 { "prescott", cpu_prescott },
153 { "nocona", cpu_nocona },
154 { "merom", cpu_core2 },
155 { "core2", cpu_core2 },
158 { "k6-2", cpu_k6_PLUS },
159 { "k6-3", cpu_k6_PLUS },
160 { "geode", cpu_geode },
161 { "athlon", cpu_athlon },
162 { "athlon-tbird", cpu_athlon },
163 { "athlon-4", cpu_athlon },
164 { "athlon-xp", cpu_athlon },
165 { "athlon-mp", cpu_athlon },
166 { "athlon64", cpu_athlon64 },
168 { "opteron", cpu_k8 },
169 { "athlon-fx", cpu_k8 },
170 { "k8-sse3", cpu_k8_sse3 },
171 { "opteron-sse3", cpu_k8_sse3 },
173 { "barcelona", cpu_k10 },
174 { "amdfam10", cpu_k10 },
176 { "winchip-c6", cpu_winchip_c6, },
177 { "winchip2", cpu_winchip2 },
179 { "c3-2", cpu_c3_2 },
181 { "generic", cpu_generic },
182 { "generic32", cpu_generic },
186 static lc_opt_enum_int_var_t arch_var = {
187 (int*) &arch, arch_items
190 static lc_opt_enum_int_var_t opt_arch_var = {
191 (int*) &opt_arch, arch_items
194 static const lc_opt_enum_int_items_t fp_unit_items[] = {
200 static lc_opt_enum_int_var_t fp_unit_var = {
201 &use_sse2, fp_unit_items
204 static const lc_opt_table_entry_t ia32_architecture_options[] = {
205 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
206 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
208 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
210 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
212 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
214 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
215 "optimisations", &opt_unsafe_floatconv, 1),
219 typedef struct insn_const {
220 int add_cost; /**< cost of an add instruction */
221 int lea_cost; /**< cost of a lea instruction */
222 int const_shf_cost; /**< cost of a constant shift instruction */
223 int cost_mul_start; /**< starting cost of a multiply instruction */
224 int cost_mul_bit; /**< cost of multiply for every set bit */
225 unsigned function_alignment; /**< logarithm for alignment of function labels */
226 unsigned label_alignment; /**< logarithm for alignment of loops labels */
227 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
230 /* costs for optimizing for size */
231 static const insn_const size_cost = {
232 2, /* cost of an add instruction */
233 3, /* cost of a lea instruction */
234 3, /* cost of a constant shift instruction */
235 4, /* starting cost of a multiply instruction */
236 0, /* cost of multiply for every set bit */
237 0, /* logarithm for alignment of function labels */
238 0, /* logarithm for alignment of loops labels */
239 0, /* maximum skip for alignment of loops labels */
242 /* costs for the i386 */
243 static const insn_const i386_cost = {
244 1, /* cost of an add instruction */
245 1, /* cost of a lea instruction */
246 3, /* cost of a constant shift instruction */
247 9, /* starting cost of a multiply instruction */
248 1, /* cost of multiply for every set bit */
249 2, /* logarithm for alignment of function labels */
250 2, /* logarithm for alignment of loops labels */
251 3, /* maximum skip for alignment of loops labels */
254 /* costs for the i486 */
255 static const insn_const i486_cost = {
256 1, /* cost of an add instruction */
257 1, /* cost of a lea instruction */
258 2, /* cost of a constant shift instruction */
259 12, /* starting cost of a multiply instruction */
260 1, /* cost of multiply for every set bit */
261 4, /* logarithm for alignment of function labels */
262 4, /* logarithm for alignment of loops labels */
263 15, /* maximum skip for alignment of loops labels */
266 /* costs for the Pentium */
267 static const insn_const pentium_cost = {
268 1, /* cost of an add instruction */
269 1, /* cost of a lea instruction */
270 1, /* cost of a constant shift instruction */
271 11, /* starting cost of a multiply instruction */
272 0, /* cost of multiply for every set bit */
273 4, /* logarithm for alignment of function labels */
274 4, /* logarithm for alignment of loops labels */
275 7, /* maximum skip for alignment of loops labels */
278 /* costs for the Pentium Pro */
279 static const insn_const pentiumpro_cost = {
280 1, /* cost of an add instruction */
281 1, /* cost of a lea instruction */
282 1, /* cost of a constant shift instruction */
283 4, /* starting cost of a multiply instruction */
284 0, /* cost of multiply for every set bit */
285 4, /* logarithm for alignment of function labels */
286 4, /* logarithm for alignment of loops labels */
287 10, /* maximum skip for alignment of loops labels */
290 /* costs for the K6 */
291 static const insn_const k6_cost = {
292 1, /* cost of an add instruction */
293 2, /* cost of a lea instruction */
294 1, /* cost of a constant shift instruction */
295 3, /* starting cost of a multiply instruction */
296 0, /* cost of multiply for every set bit */
297 5, /* logarithm for alignment of function labels */
298 5, /* logarithm for alignment of loops labels */
299 7, /* maximum skip for alignment of loops labels */
302 /* costs for the Geode */
303 static const insn_const geode_cost = {
304 1, /* cost of an add instruction */
305 1, /* cost of a lea instruction */
306 1, /* cost of a constant shift instruction */
307 7, /* starting cost of a multiply instruction */
308 0, /* cost of multiply for every set bit */
309 0, /* logarithm for alignment of function labels */
310 0, /* logarithm for alignment of loops labels */
311 0, /* maximum skip for alignment of loops labels */
314 /* costs for the Athlon */
315 static const insn_const athlon_cost = {
316 1, /* cost of an add instruction */
317 2, /* cost of a lea instruction */
318 1, /* cost of a constant shift instruction */
319 5, /* starting cost of a multiply instruction */
320 0, /* cost of multiply for every set bit */
321 4, /* logarithm for alignment of function labels */
322 4, /* logarithm for alignment of loops labels */
323 7, /* maximum skip for alignment of loops labels */
326 /* costs for the Opteron/K8/K10 */
327 static const insn_const k8_cost = {
328 1, /* cost of an add instruction */
329 2, /* cost of a lea instruction */
330 1, /* cost of a constant shift instruction */
331 3, /* starting cost of a multiply instruction */
332 0, /* cost of multiply for every set bit */
334 4, /* logarithm for alignment of function labels */
335 4, /* logarithm for alignment of loops labels */
336 7, /* maximum skip for alignment of loops labels */
344 /* costs for the K10 */
345 static const insn_const k10_cost = {
346 1, /* cost of an add instruction */
347 2, /* cost of a lea instruction */
348 1, /* cost of a constant shift instruction */
349 3, /* starting cost of a multiply instruction */
350 0, /* cost of multiply for every set bit */
351 5, /* logarithm for alignment of function labels */
352 5, /* logarithm for alignment of loops labels */
353 7, /* maximum skip for alignment of loops labels */
356 /* costs for the Pentium 4 */
357 static const insn_const netburst_cost = {
358 1, /* cost of an add instruction */
359 3, /* cost of a lea instruction */
360 4, /* cost of a constant shift instruction */
361 15, /* starting cost of a multiply instruction */
362 0, /* cost of multiply for every set bit */
363 4, /* logarithm for alignment of function labels */
364 4, /* logarithm for alignment of loops labels */
365 7, /* maximum skip for alignment of loops labels */
368 /* costs for the Nocona and Core */
369 static const insn_const nocona_cost = {
370 1, /* cost of an add instruction */
371 1, /* cost of a lea instruction */
372 1, /* cost of a constant shift instruction */
373 10, /* starting cost of a multiply instruction */
374 0, /* cost of multiply for every set bit */
375 4, /* logarithm for alignment of function labels */
376 4, /* logarithm for alignment of loops labels */
377 7, /* maximum skip for alignment of loops labels */
380 /* costs for the Core2 */
381 static const insn_const core2_cost = {
382 1, /* cost of an add instruction */
383 1, /* cost of a lea instruction */
384 1, /* cost of a constant shift instruction */
385 3, /* starting cost of a multiply instruction */
386 0, /* cost of multiply for every set bit */
387 4, /* logarithm for alignment of function labels */
388 4, /* logarithm for alignment of loops labels */
389 10, /* maximum skip for alignment of loops labels */
392 /* costs for the generic32 */
393 static const insn_const generic32_cost = {
394 1, /* cost of an add instruction */
395 2, /* cost of a lea instruction */
396 1, /* cost of a constant shift instruction */
397 4, /* starting cost of a multiply instruction */
398 0, /* cost of multiply for every set bit */
399 4, /* logarithm for alignment of function labels */
400 4, /* logarithm for alignment of loops labels */
401 7, /* maximum skip for alignment of loops labels */
404 static const insn_const *arch_costs = &generic32_cost;
406 static void set_arch_costs(void)
409 arch_costs = &size_cost;
412 switch (opt_arch & arch_mask) {
414 arch_costs = &i386_cost;
417 arch_costs = &i486_cost;
420 arch_costs = &pentium_cost;
423 arch_costs = &pentiumpro_cost;
426 arch_costs = &netburst_cost;
429 arch_costs = &nocona_cost;
432 arch_costs = &core2_cost;
435 arch_costs = &k6_cost;
438 arch_costs = &geode_cost;
441 arch_costs = &athlon_cost;
444 arch_costs = &k8_cost;
447 arch_costs = &k10_cost;
451 arch_costs = &generic32_cost;
456 * Evaluate a given simple instruction.
458 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
463 cost = arch_costs->cost_mul_start;
464 if (arch_costs->cost_mul_bit > 0) {
465 char *bitstr = get_tarval_bitpattern(tv);
468 for (i = 0; bitstr[i] != '\0'; ++i) {
469 if (bitstr[i] == '1') {
470 cost += arch_costs->cost_mul_bit;
477 return arch_costs->lea_cost;
480 return arch_costs->add_cost;
482 return arch_costs->const_shf_cost;
484 return arch_costs->add_cost;
490 void ia32_setup_cg_config(void)
492 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
496 ia32_cg_config.optimize_size = opt_size != 0;
497 /* on newer intel cpus mov, pop is often faster then leave although it has a
499 ia32_cg_config.use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2);
500 /* P4s don't like inc/decs because they only partially write the flags
501 register which produces false dependencies */
502 ia32_cg_config.use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
503 ia32_cg_config.use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
504 ia32_cg_config.use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
505 ia32_cg_config.use_ftst = !FLAGS(arch, arch_feature_p6_insn);
506 ia32_cg_config.use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
507 FLAGS(arch, arch_feature_mmx | arch_all_amd);
508 ia32_cg_config.use_fucomi = FLAGS(arch, arch_feature_p6_insn);
509 ia32_cg_config.use_cmov = FLAGS(arch, arch_feature_p6_insn);
510 ia32_cg_config.use_modeD_moves = FLAGS(opt_arch, arch_athlon_plus | arch_geode | arch_ppro |
511 arch_netburst | arch_nocona | arch_core2 | arch_generic32);
512 ia32_cg_config.use_add_esp_4 = FLAGS(opt_arch, arch_geode | arch_athlon_plus |
513 arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
515 ia32_cg_config.use_add_esp_8 = FLAGS(opt_arch, arch_geode | arch_athlon_plus |
516 arch_i386 | arch_i486 | arch_ppro | arch_netburst |
517 arch_nocona | arch_core2 | arch_generic32) &&
519 ia32_cg_config.use_sub_esp_4 = FLAGS(opt_arch, arch_athlon_plus | arch_ppro |
520 arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
522 ia32_cg_config.use_sub_esp_8 = FLAGS(opt_arch, arch_athlon_plus | arch_i386 | arch_i486 |
523 arch_ppro | arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
525 ia32_cg_config.use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
526 ia32_cg_config.use_pxor = FLAGS(opt_arch, arch_netburst);
527 ia32_cg_config.use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
528 ia32_cg_config.use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
529 ia32_cg_config.use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
530 ia32_cg_config.use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3);
531 ia32_cg_config.optimize_cc = opt_cc;
532 ia32_cg_config.use_unsafe_floatconv = opt_unsafe_floatconv;
534 ia32_cg_config.function_alignment = arch_costs->function_alignment;
535 ia32_cg_config.label_alignment = arch_costs->label_alignment;
536 ia32_cg_config.label_alignment_max_skip = arch_costs->label_alignment_max_skip;
538 if (opt_arch & (arch_i386 | arch_i486)) {
539 ia32_cg_config.label_alignment_factor = 0;
540 } else if (opt_arch & arch_all_amd) {
541 ia32_cg_config.label_alignment_factor = 3;
543 ia32_cg_config.label_alignment_factor = 2;
547 void ia32_init_architecture(void)
549 lc_opt_entry_t *be_grp, *ia32_grp;
551 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
553 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
554 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
556 lc_opt_add_table(ia32_grp, ia32_architecture_options);